mm: hugetlb: fix hugepage memory leak caused by wrong reserve count
[linux/fpc-iii.git] / arch / arm / boot / dts / omap3-zoom3.dts
blob7bc5fdd6981e25d76e3409533fbc46238177ce3f
1 /*
2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 /dts-v1/;
10 #include "omap36xx.dtsi"
11 #include "omap-zoom-common.dtsi"
13 / {
14         model = "TI Zoom3";
15         compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3";
17         cpus {
18                 cpu@0 {
19                         cpu0-supply = <&vcc>;
20                 };
21         };
23         memory {
24                 device_type = "memory";
25                 reg = <0x80000000 0x20000000>; /* 512 MB */
26         };
28         vddvario: regulator-vddvario {
29                   compatible = "regulator-fixed";
30                   regulator-name = "vddvario";
31                   regulator-always-on;
32         };
34         vdd33a: regulator-vdd33a {
35                 compatible = "regulator-fixed";
36                 regulator-name = "vdd33a";
37                 regulator-always-on;
38         };
40         wl12xx_vmmc: wl12xx_vmmc {
41                 pinctrl-names = "default";
42                 pinctrl-0 = <&wl12xx_gpio>;
43                 compatible = "regulator-fixed";
44                 regulator-name = "vwl1271";
45                 regulator-min-microvolt = <1800000>;
46                 regulator-max-microvolt = <1800000>;
47                 gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;     /* gpio101 */
48                 startup-delay-us = <70000>;
49                 enable-active-high;
50         };
53 &omap3_pmx_core {
54         /* REVISIT: twl gpio0 is mmc0_cd */
55         mmc1_pins: pinmux_mmc1_pins {
56                 pinctrl-single,pins = <
57                         0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* sdmmc1_clk.sdmmc1_clk */
58                         0x116 (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* sdmmc1_cmd.sdmmc1_cmd */
59                         0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat0.sdmmc1_dat0 */
60                         0x11a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat1.sdmmc1_dat1 */
61                         0x11c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat2.sdmmc1_dat2 */
62                         0x11e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat3.sdmmc1_dat3 */
63                 >;
64         };
66         mmc2_pins: pinmux_mmc2_pins {
67                 pinctrl-single,pins = <
68                         0x128 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_clk.sdmmc2_clk */
69                         0x12a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_cmd.sdmmc2_cmd */
70                         0x12c (PIN_INPUT | MUX_MODE0)           /* sdmmc2_dat0.sdmmc2_dat0 */
71                         0x12e (PIN_INPUT | MUX_MODE0)           /* sdmmc2_dat1.sdmmc2_dat1 */
72                         0x130 (PIN_INPUT | MUX_MODE0)           /* sdmmc2_dat2.sdmmc2_dat2 */
73                         0x132 (PIN_INPUT | MUX_MODE0)           /* sdmmc2_dat3.sdmmc2_dat3 */
74                         0x134 (PIN_INPUT | MUX_MODE0)           /* sdmmc2_dat4.sdmmc2_dat4 */
75                         0x136 (PIN_INPUT | MUX_MODE0)           /* sdmmc2_dat5.sdmmc2_dat5 */
76                         0x138 (PIN_INPUT | MUX_MODE0)           /* sdmmc2_dat6.sdmmc2_dat6 */
77                         0x13a (PIN_INPUT | MUX_MODE0)           /* sdmmc2_dat7.sdmmc2_dat7 */
78                 >;
79         };
81         mmc3_pins: pinmux_mmc3_pins {
82                 pinctrl-single,pins = <
83                         OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4)        /* mcbsp1_clkx.gpio_162 WLAN IRQ */
84                         OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
85                 >;
86         };
88         uart1_pins: pinmux_uart1_pins {
89                 pinctrl-single,pins = <
90                         0x150 (PIN_INPUT | MUX_MODE0)           /* uart1_cts.uart1_cts */
91                         0x14e (PIN_OUTPUT | MUX_MODE0)          /* uart1_rts.uart1_rts */
92                         0x152 (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
93                         0x14c (PIN_OUTPUT | MUX_MODE0)          /* uart1_tx.uart1_tx */
94                 >;
95         };
97         uart2_pins: pinmux_uart2_pins {
98                 pinctrl-single,pins = <
99                         0x144 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart2_cts.uart2_cts */
100                         0x146 (PIN_OUTPUT | MUX_MODE0)          /* uart2_rts.uart2_rts */
101                         0x14a (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
102                         0x148 (PIN_OUTPUT | MUX_MODE0)          /* uart2_tx.uart2_tx */
103                 >;
104         };
106         uart3_pins: pinmux_uart3_pins {
107                 pinctrl-single,pins = <
108                         0x16a (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* uart3_cts_rctx.uart3_cts_rctx */
109                         0x16c (PIN_OUTPUT | MUX_MODE0)          /* uart3_rts_sd.uart3_rts_sd */
110                         0x16e (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
111                         0x170 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx_irtx.uart3_tx_irtx */
112                 >;
113         };
115         /* wl12xx GPIO output for WLAN_EN */
116         wl12xx_gpio: pinmux_wl12xx_gpio {
117                 pinctrl-single,pins = <
118                         0xea (PIN_OUTPUT| MUX_MODE4)            /* cam_d2.gpio_101 */
119                 >;
120         };
123 &omap3_pmx_core2 {
124         mmc3_2_pins: pinmux_mmc3_2_pins {
125                 pinctrl-single,pins = <
126                         OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_clk.sdmmc3_clk */
127                         OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d4.sdmmc3_dat0 */
128                         OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
129                         OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d6.sdmmc3_dat2 */
130                         OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d3.sdmmc3_dat3 */
131                 >;
132         };
135 &omap3_pmx_wkup {
136         wlan_host_wkup: pinmux_wlan_host_wkup_pins {
137                 pinctrl-single,pins = <
138                         0x1a (PIN_INPUT_PULLUP | MUX_MODE4)     /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */
139                 >;
140         };
143 &i2c1 {
144         clock-frequency = <2600000>;
146         twl: twl@48 {
147                 reg = <0x48>;
148                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
149                 interrupt-parent = <&intc>;
150         };
153 #include "twl4030.dtsi"
155 &i2c2 {
156         clock-frequency = <400000>;
159 &i2c3 {
160         clock-frequency = <400000>;
162         /*
163          * TVP5146 Video decoder-in for analog input support.
164          */
165         tvp5146@5c {
166                 compatible = "ti,tvp5146m2";
167                 reg = <0x5c>;
168         };
171 &twl_gpio {
172         ti,use-leds;
175 &mmc1 {
176         vmmc-supply = <&vmmc1>;
177         vmmc_aux-supply = <&vsim>;
178         bus-width = <4>;
179         pinctrl-names = "default";
180         pinctrl-0 = <&mmc1_pins>;
183 &mmc2 {
184         vmmc-supply = <&vmmc2>;
185         ti,non-removable;
186         bus-width = <8>;
187         pinctrl-names = "default";
188         pinctrl-0 = <&mmc2_pins>;
191 &mmc3 {
192         vmmc-supply = <&wl12xx_vmmc>;
193         non-removable;
194         bus-width = <4>;
195         cap-power-off-card;
196         pinctrl-names = "default";
197         pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
199         #address-cells = <1>;
200         #size-cells = <0>;
201         wlcore: wlcore@2 {
202                 compatible = "ti,wl1271";
203                 reg = <2>;
204                 interrupt-parent = <&gpio6>;
205                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 162 */
206                 ref-clock-frequency = <26000000>;
207         };
210 &uart1 {
211        pinctrl-names = "default";
212        pinctrl-0 = <&uart1_pins>;
215 &uart2 {
216        pinctrl-names = "default";
217        pinctrl-0 = <&uart2_pins>;
220 &uart3 {
221        pinctrl-names = "default";
222        pinctrl-0 = <&uart3_pins>;
225 &uart4 {
226        status = "disabled";
229 &usb_otg_hs {
230         interface-type = <0>;
231         usb-phy = <&usb2_phy>;
232         mode = <3>;
233         power = <50>;