2 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 * Copyright (C) Sylver Bruneau <sylver.bruneau@googlemail.com>
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include "orion5x-mv88f5182.dtsi"
18 model = "Maxtor Shared Storage II";
19 compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x";
22 reg = <0x00000000 0x4000000>; /* 64 MB */
26 bootargs = "console=ttyS0,115200n8 earlyprintk";
27 linux,stdout-path = &uart0;
31 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
32 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
33 <MBUS_ID(0x01, 0x0f) 0 0xff800000 0x40000>;
37 compatible = "gpio-keys";
38 pinctrl-0 = <&pmx_buttons>;
39 pinctrl-names = "default";
44 linux,code = <KEY_POWER>;
45 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
50 linux,code = <KEY_RESTART>;
51 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
62 * Currently the MTD code does not recognize the MX29LV400CBCT
63 * as a bottom-type device. This could cause risks of
64 * accidentally erasing critical flash sectors. We thus define
65 * a single, write-protected partition covering the whole
66 * flash. TODO: once the flash part TOP/BOTTOM detection
67 * issue is sorted out in the MTD code, break this into at
68 * least three partitions: 'u-boot code', 'u-boot environment'
69 * and 'whatever is left'.
72 compatible = "cfi-flash";
83 ethphy: ethernet-phy {
96 phy-handle = <ðphy>;
102 clock-frequency = <100000>;
103 #address-cells = <1>;
106 compatible = "st,m41t81";
108 pinctrl-0 = <&pmx_rtc>;
109 pinctrl-names = "default";
110 interrupt-parent = <&gpio0>;
111 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
116 pinctrl-0 = <&pmx_leds &pmx_misc>;
117 pinctrl-names = "default";
119 pmx_buttons: pmx-buttons {
120 marvell,pins = "mpp11", "mpp12";
121 marvell,function = "gpio";
129 marvell,pins = "mpp0", "mpp1";
130 marvell,function = "gpio";
134 * MPP4: HDD ind. (Single/Dual)
135 * MPP5: HD0 5V control
136 * MPP6: HD0 12V control
137 * MPP7: HD1 5V control
138 * MPP8: HD1 12V control
141 marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10";
142 marvell,function = "gpio";
146 marvell,pins = "mpp3";
147 marvell,function = "gpio";
150 pmx_sata0_led_active: pmx-sata0-led-active {
151 marvell,pins = "mpp14";
152 marvell,function = "sata0";
155 pmx_sata1_led_active: pmx-sata1-led-active {
156 marvell,pins = "mpp15";
157 marvell,function = "sata1";
162 * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok)
163 * GPIO 23: Blue front LED off
164 * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled)
169 pinctrl-0 = <&pmx_sata0_led_active
170 &pmx_sata1_led_active>;
171 pinctrl-names = "default";