| blob | 1ca1a9aa953f7ee893fddf8b5a9217ddab7e2956 |
1 /*
2 * DTS file for CSR SiRFprimaII SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
9 /include/ "skeleton.dtsi"
10 / {
11 compatible = "sirf,prima2";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
20 cpu@0 {
21 compatible = "arm,cortex-a9";
22 device_type = "cpu";
23 reg = <0x0>;
24 d-cache-line-size = <32>;
25 i-cache-line-size = <32>;
26 d-cache-size = <32768>;
27 i-cache-size = <32768>;
28 /* from bootloader */
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 clocks = <&clks 12>;
33 operating-points = <
34 /* kHz uV */
35 200000 1025000
36 400000 1025000
37 664000 1050000
38 800000 1100000
39 >;
40 clock-latency = <150000>;
41 };
42 };
44 arm-pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <29>;
47 };
49 axi {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges = <0x40000000 0x40000000 0x80000000>;
55 l2-cache-controller@80040000 {
56 compatible = "arm,pl310-cache";
57 reg = <0x80040000 0x1000>;
58 interrupts = <59>;
59 arm,tag-latency = <1 1 1>;
60 arm,data-latency = <1 1 1>;
61 arm,filter-ranges = <0 0x40000000>;
62 };
64 intc: interrupt-controller@80020000 {
65 #interrupt-cells = <1>;
66 interrupt-controller;
67 compatible = "sirf,prima2-intc";
68 reg = <0x80020000 0x1000>;
69 };
71 sys-iobg {
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges = <0x88000000 0x88000000 0x40000>;
77 clks: clock-controller@88000000 {
78 compatible = "sirf,prima2-clkc";
79 reg = <0x88000000 0x1000>;
80 interrupts = <3>;
81 #clock-cells = <1>;
82 };
84 rstc: reset-controller@88010000 {
85 compatible = "sirf,prima2-rstc";
86 reg = <0x88010000 0x1000>;
87 #reset-cells = <1>;
88 };
90 rsc-controller@88020000 {
91 compatible = "sirf,prima2-rsc";
92 reg = <0x88020000 0x1000>;
93 };
95 cphifbg@88030000 {
96 compatible = "sirf,prima2-cphifbg";
97 reg = <0x88030000 0x1000>;
98 clocks = <&clks 42>;
99 };
100 };
102 mem-iobg {
103 compatible = "simple-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 ranges = <0x90000000 0x90000000 0x10000>;
108 memory-controller@90000000 {
109 compatible = "sirf,prima2-memc";
110 reg = <0x90000000 0x2000>;
111 interrupts = <27>;
112 clocks = <&clks 5>;
113 };
115 memc-monitor {
116 compatible = "sirf,prima2-memcmon";
117 reg = <0x90002000 0x200>;
118 interrupts = <4>;
119 clocks = <&clks 32>;
120 };
121 };
123 disp-iobg {
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0x90010000 0x90010000 0x30000>;
129 display@90010000 {
130 compatible = "sirf,prima2-lcd";
131 reg = <0x90010000 0x20000>;
132 interrupts = <30>;
133 };
135 vpp@90020000 {
136 compatible = "sirf,prima2-vpp";
137 reg = <0x90020000 0x10000>;
138 interrupts = <31>;
139 clocks = <&clks 35>;
140 resets = <&rstc 6>;
141 };
142 };
144 graphics-iobg {
145 compatible = "simple-bus";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 ranges = <0x98000000 0x98000000 0x8000000>;
150 graphics@98000000 {
151 compatible = "powervr,sgx531";
152 reg = <0x98000000 0x8000000>;
153 interrupts = <6>;
154 clocks = <&clks 32>;
155 };
156 };
158 multimedia-iobg {
159 compatible = "simple-bus";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 ranges = <0xa0000000 0xa0000000 0x8000000>;
164 multimedia@a0000000 {
165 compatible = "sirf,prima2-video-codec";
166 reg = <0xa0000000 0x8000000>;
167 interrupts = <5>;
168 clocks = <&clks 33>;
169 };
170 };
172 dsp-iobg {
173 compatible = "simple-bus";
174 #address-cells = <1>;
175 #size-cells = <1>;
176 ranges = <0xa8000000 0xa8000000 0x2000000>;
178 dspif@a8000000 {
179 compatible = "sirf,prima2-dspif";
180 reg = <0xa8000000 0x10000>;
181 interrupts = <9>;
182 resets = <&rstc 1>;
183 };
185 gps@a8010000 {
186 compatible = "sirf,prima2-gps";
187 reg = <0xa8010000 0x10000>;
188 interrupts = <7>;
189 clocks = <&clks 9>;
190 resets = <&rstc 2>;
191 };
193 dsp@a9000000 {
194 compatible = "sirf,prima2-dsp";
195 reg = <0xa9000000 0x1000000>;
196 interrupts = <8>;
197 clocks = <&clks 8>;
198 resets = <&rstc 0>;
199 };
200 };
202 peri-iobg {
203 compatible = "simple-bus";
204 #address-cells = <1>;
205 #size-cells = <1>;
206 ranges = <0xb0000000 0xb0000000 0x180000>,
207 <0x56000000 0x56000000 0x1b00000>;
209 timer@b0020000 {
210 compatible = "sirf,prima2-tick";
211 reg = <0xb0020000 0x1000>;
212 interrupts = <0>;
213 clocks = <&clks 11>;
214 };
216 nand@b0030000 {
217 compatible = "sirf,prima2-nand";
218 reg = <0xb0030000 0x10000>;
219 interrupts = <41>;
220 clocks = <&clks 26>;
221 };
223 audio@b0040000 {
224 compatible = "sirf,prima2-audio";
225 reg = <0xb0040000 0x10000>;
226 interrupts = <35>;
227 clocks = <&clks 27>;
228 };
230 uart0: uart@b0050000 {
231 cell-index = <0>;
232 compatible = "sirf,prima2-uart";
233 reg = <0xb0050000 0x1000>;
234 interrupts = <17>;
235 fifosize = <128>;
236 clocks = <&clks 13>;
237 dmas = <&dmac1 5>, <&dmac0 2>;
238 dma-names = "rx", "tx";
239 };
241 uart1: uart@b0060000 {
242 cell-index = <1>;
243 compatible = "sirf,prima2-uart";
244 reg = <0xb0060000 0x1000>;
245 interrupts = <18>;
246 fifosize = <32>;
247 clocks = <&clks 14>;
248 };
250 uart2: uart@b0070000 {
251 cell-index = <2>;
252 compatible = "sirf,prima2-uart";
253 reg = <0xb0070000 0x1000>;
254 interrupts = <19>;
255 fifosize = <128>;
256 clocks = <&clks 15>;
257 dmas = <&dmac0 6>, <&dmac0 7>;
258 dma-names = "rx", "tx";
259 };
261 usp0: usp@b0080000 {
262 cell-index = <0>;
263 compatible = "sirf,prima2-usp";
264 reg = <0xb0080000 0x10000>;
265 interrupts = <20>;
266 fifosize = <128>;
267 clocks = <&clks 28>;
268 dmas = <&dmac1 1>, <&dmac1 2>;
269 dma-names = "rx", "tx";
270 };
272 usp1: usp@b0090000 {
273 cell-index = <1>;
274 compatible = "sirf,prima2-usp";
275 reg = <0xb0090000 0x10000>;
276 interrupts = <21>;
277 fifosize = <128>;
278 clocks = <&clks 29>;
279 dmas = <&dmac0 14>, <&dmac0 15>;
280 dma-names = "rx", "tx";
281 };
283 usp2: usp@b00a0000 {
284 cell-index = <2>;
285 compatible = "sirf,prima2-usp";
286 reg = <0xb00a0000 0x10000>;
287 interrupts = <22>;
288 fifosize = <128>;
289 clocks = <&clks 30>;
290 dmas = <&dmac0 10>, <&dmac0 11>;
291 dma-names = "rx", "tx";
292 };
294 dmac0: dma-controller@b00b0000 {
295 cell-index = <0>;
296 compatible = "sirf,prima2-dmac";
297 reg = <0xb00b0000 0x10000>;
298 interrupts = <12>;
299 clocks = <&clks 24>;
300 #dma-cells = <1>;
301 };
303 dmac1: dma-controller@b0160000 {
304 cell-index = <1>;
305 compatible = "sirf,prima2-dmac";
306 reg = <0xb0160000 0x10000>;
307 interrupts = <13>;
308 clocks = <&clks 25>;
309 #dma-cells = <1>;
310 };
312 vip@b00C0000 {
313 compatible = "sirf,prima2-vip";
314 reg = <0xb00C0000 0x10000>;
315 clocks = <&clks 31>;
316 interrupts = <14>;
317 sirf,vip-dma-rx-channel = <16>;
318 };
320 spi0: spi@b00d0000 {
321 cell-index = <0>;
322 compatible = "sirf,prima2-spi";
323 reg = <0xb00d0000 0x10000>;
324 interrupts = <15>;
325 sirf,spi-num-chipselects = <1>;
326 dmas = <&dmac1 9>,
327 <&dmac1 4>;
328 dma-names = "rx", "tx";
329 #address-cells = <1>;
330 #size-cells = <0>;
331 clocks = <&clks 19>;
332 status = "disabled";
333 };
335 spi1: spi@b0170000 {
336 cell-index = <1>;
337 compatible = "sirf,prima2-spi";
338 reg = <0xb0170000 0x10000>;
339 interrupts = <16>;
340 sirf,spi-num-chipselects = <1>;
341 dmas = <&dmac0 12>,
342 <&dmac0 13>;
343 dma-names = "rx", "tx";
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clocks = <&clks 20>;
347 status = "disabled";
348 };
350 i2c0: i2c@b00e0000 {
351 cell-index = <0>;
352 compatible = "sirf,prima2-i2c";
353 reg = <0xb00e0000 0x10000>;
354 interrupts = <24>;
355 clocks = <&clks 17>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358 };
360 i2c1: i2c@b00f0000 {
361 cell-index = <1>;
362 compatible = "sirf,prima2-i2c";
363 reg = <0xb00f0000 0x10000>;
364 interrupts = <25>;
365 clocks = <&clks 18>;
366 #address-cells = <1>;
367 #size-cells = <0>;
368 };
370 tsc@b0110000 {
371 compatible = "sirf,prima2-tsc";
372 reg = <0xb0110000 0x10000>;
373 interrupts = <33>;
374 clocks = <&clks 16>;
375 };
377 gpio: pinctrl@b0120000 {
378 #gpio-cells = <2>;
379 #interrupt-cells = <2>;
380 compatible = "sirf,prima2-pinctrl";
381 reg = <0xb0120000 0x10000>;
382 interrupts = <43 44 45 46 47>;
383 gpio-controller;
384 interrupt-controller;
386 lcd_16pins_a: lcd0@0 {
387 lcd {
388 sirf,pins = "lcd_16bitsgrp";
389 sirf,function = "lcd_16bits";
390 };
391 };
392 lcd_18pins_a: lcd0@1 {
393 lcd {
394 sirf,pins = "lcd_18bitsgrp";
395 sirf,function = "lcd_18bits";
396 };
397 };
398 lcd_24pins_a: lcd0@2 {
399 lcd {
400 sirf,pins = "lcd_24bitsgrp";
401 sirf,function = "lcd_24bits";
402 };
403 };
404 lcdrom_pins_a: lcdrom0@0 {
405 lcd {
406 sirf,pins = "lcdromgrp";
407 sirf,function = "lcdrom";
408 };
409 };
410 uart0_pins_a: uart0@0 {
411 uart {
412 sirf,pins = "uart0grp";
413 sirf,function = "uart0";
414 };
415 };
416 uart0_noflow_pins_a: uart0@1 {
417 uart {
418 sirf,pins = "uart0_nostreamctrlgrp";
419 sirf,function = "uart0_nostreamctrl";
420 };
421 };
422 uart1_pins_a: uart1@0 {
423 uart {
424 sirf,pins = "uart1grp";
425 sirf,function = "uart1";
426 };
427 };
428 uart2_pins_a: uart2@0 {
429 uart {
430 sirf,pins = "uart2grp";
431 sirf,function = "uart2";
432 };
433 };
434 uart2_noflow_pins_a: uart2@1 {
435 uart {
436 sirf,pins = "uart2_nostreamctrlgrp";
437 sirf,function = "uart2_nostreamctrl";
438 };
439 };
440 spi0_pins_a: spi0@0 {
441 spi {
442 sirf,pins = "spi0grp";
443 sirf,function = "spi0";
444 };
445 };
446 spi1_pins_a: spi1@0 {
447 spi {
448 sirf,pins = "spi1grp";
449 sirf,function = "spi1";
450 };
451 };
452 i2c0_pins_a: i2c0@0 {
453 i2c {
454 sirf,pins = "i2c0grp";
455 sirf,function = "i2c0";
456 };
457 };
458 i2c1_pins_a: i2c1@0 {
459 i2c {
460 sirf,pins = "i2c1grp";
461 sirf,function = "i2c1";
462 };
463 };
464 pwm0_pins_a: pwm0@0 {
465 pwm {
466 sirf,pins = "pwm0grp";
467 sirf,function = "pwm0";
468 };
469 };
470 pwm1_pins_a: pwm1@0 {
471 pwm {
472 sirf,pins = "pwm1grp";
473 sirf,function = "pwm1";
474 };
475 };
476 pwm2_pins_a: pwm2@0 {
477 pwm {
478 sirf,pins = "pwm2grp";
479 sirf,function = "pwm2";
480 };
481 };
482 pwm3_pins_a: pwm3@0 {
483 pwm {
484 sirf,pins = "pwm3grp";
485 sirf,function = "pwm3";
486 };
487 };
488 gps_pins_a: gps@0 {
489 gps {
490 sirf,pins = "gpsgrp";
491 sirf,function = "gps";
492 };
493 };
494 vip_pins_a: vip@0 {
495 vip {
496 sirf,pins = "vipgrp";
497 sirf,function = "vip";
498 };
499 };
500 sdmmc0_pins_a: sdmmc0@0 {
501 sdmmc0 {
502 sirf,pins = "sdmmc0grp";
503 sirf,function = "sdmmc0";
504 };
505 };
506 sdmmc1_pins_a: sdmmc1@0 {
507 sdmmc1 {
508 sirf,pins = "sdmmc1grp";
509 sirf,function = "sdmmc1";
510 };
511 };
512 sdmmc2_pins_a: sdmmc2@0 {
513 sdmmc2 {
514 sirf,pins = "sdmmc2grp";
515 sirf,function = "sdmmc2";
516 };
517 };
518 sdmmc3_pins_a: sdmmc3@0 {
519 sdmmc3 {
520 sirf,pins = "sdmmc3grp";
521 sirf,function = "sdmmc3";
522 };
523 };
524 sdmmc4_pins_a: sdmmc4@0 {
525 sdmmc4 {
526 sirf,pins = "sdmmc4grp";
527 sirf,function = "sdmmc4";
528 };
529 };
530 sdmmc5_pins_a: sdmmc5@0 {
531 sdmmc5 {
532 sirf,pins = "sdmmc5grp";
533 sirf,function = "sdmmc5";
534 };
535 };
536 i2s_mclk_pins_a: i2s_mclk@0 {
537 i2s_mclk {
538 sirf,pins = "i2smclkgrp";
539 sirf,function = "i2s_mclk";
540 };
541 };
542 i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
543 i2s_ext_clk_input {
544 sirf,pins = "i2s_ext_clk_inputgrp";
545 sirf,function = "i2s_ext_clk_input";
546 };
547 };
548 i2s_pins_a: i2s@0 {
549 i2s {
550 sirf,pins = "i2sgrp";
551 sirf,function = "i2s";
552 };
553 };
554 i2s_no_din_pins_a: i2s_no_din@0 {
555 i2s_no_din {
556 sirf,pins = "i2s_no_dingrp";
557 sirf,function = "i2s_no_din";
558 };
559 };
560 i2s_6chn_pins_a: i2s_6chn@0 {
561 i2s_6chn {
562 sirf,pins = "i2s_6chngrp";
563 sirf,function = "i2s_6chn";
564 };
565 };
566 ac97_pins_a: ac97@0 {
567 ac97 {
568 sirf,pins = "ac97grp";
569 sirf,function = "ac97";
570 };
571 };
572 nand_pins_a: nand@0 {
573 nand {
574 sirf,pins = "nandgrp";
575 sirf,function = "nand";
576 };
577 };
578 usp0_pins_a: usp0@0 {
579 usp0 {
580 sirf,pins = "usp0grp";
581 sirf,function = "usp0";
582 };
583 };
584 usp0_uart_nostreamctrl_pins_a: usp0@1 {
585 usp0 {
586 sirf,pins =
587 "usp0_uart_nostreamctrl_grp";
588 sirf,function =
589 "usp0_uart_nostreamctrl";
590 };
591 };
592 usp0_only_utfs_pins_a: usp0@2 {
593 usp0 {
594 sirf,pins = "usp0_only_utfs_grp";
595 sirf,function = "usp0_only_utfs";
596 };
597 };
598 usp0_only_urfs_pins_a: usp0@3 {
599 usp0 {
600 sirf,pins = "usp0_only_urfs_grp";
601 sirf,function = "usp0_only_urfs";
602 };
603 };
604 usp1_pins_a: usp1@0 {
605 usp1 {
606 sirf,pins = "usp1grp";
607 sirf,function = "usp1";
608 };
609 };
610 usp1_uart_nostreamctrl_pins_a: usp1@1 {
611 usp1 {
612 sirf,pins =
613 "usp1_uart_nostreamctrl_grp";
614 sirf,function =
615 "usp1_uart_nostreamctrl";
616 };
617 };
618 usp2_pins_a: usp2@0 {
619 usp2 {
620 sirf,pins = "usp2grp";
621 sirf,function = "usp2";
622 };
623 };
624 usp2_uart_nostreamctrl_pins_a: usp2@1 {
625 usp2 {
626 sirf,pins =
627 "usp2_uart_nostreamctrl_grp";
628 sirf,function =
629 "usp2_uart_nostreamctrl";
630 };
631 };
632 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
633 usb0_utmi_drvbus {
634 sirf,pins = "usb0_utmi_drvbusgrp";
635 sirf,function = "usb0_utmi_drvbus";
636 };
637 };
638 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
639 usb1_utmi_drvbus {
640 sirf,pins = "usb1_utmi_drvbusgrp";
641 sirf,function = "usb1_utmi_drvbus";
642 };
643 };
644 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
645 usb1_dp_dn {
646 sirf,pins = "usb1_dp_dngrp";
647 sirf,function = "usb1_dp_dn";
648 };
649 };
650 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
651 uart1_route_io_usb1 {
652 sirf,pins = "uart1_route_io_usb1grp";
653 sirf,function = "uart1_route_io_usb1";
654 };
655 };
656 warm_rst_pins_a: warm_rst@0 {
657 warm_rst {
658 sirf,pins = "warm_rstgrp";
659 sirf,function = "warm_rst";
660 };
661 };
662 pulse_count_pins_a: pulse_count@0 {
663 pulse_count {
664 sirf,pins = "pulse_countgrp";
665 sirf,function = "pulse_count";
666 };
667 };
668 cko0_pins_a: cko0@0 {
669 cko0 {
670 sirf,pins = "cko0grp";
671 sirf,function = "cko0";
672 };
673 };
674 cko1_pins_a: cko1@0 {
675 cko1 {
676 sirf,pins = "cko1grp";
677 sirf,function = "cko1";
678 };
679 };
680 };
682 pwm@b0130000 {
683 compatible = "sirf,prima2-pwm";
684 reg = <0xb0130000 0x10000>;
685 clocks = <&clks 21>;
686 };
688 efusesys@b0140000 {
689 compatible = "sirf,prima2-efuse";
690 reg = <0xb0140000 0x10000>;
691 clocks = <&clks 22>;
692 };
694 pulsec@b0150000 {
695 compatible = "sirf,prima2-pulsec";
696 reg = <0xb0150000 0x10000>;
697 interrupts = <48>;
698 clocks = <&clks 23>;
699 };
701 pci-iobg {
702 compatible = "sirf,prima2-pciiobg", "simple-bus";
703 #address-cells = <1>;
704 #size-cells = <1>;
705 ranges = <0x56000000 0x56000000 0x1b00000>;
707 sd0: sdhci@56000000 {
708 cell-index = <0>;
709 compatible = "sirf,prima2-sdhc";
710 reg = <0x56000000 0x100000>;
711 interrupts = <38>;
712 status = "disabled";
713 bus-width = <8>;
714 clocks = <&clks 36>;
715 };
717 sd1: sdhci@56100000 {
718 cell-index = <1>;
719 compatible = "sirf,prima2-sdhc";
720 reg = <0x56100000 0x100000>;
721 interrupts = <38>;
722 status = "disabled";
723 bus-width = <4>;
724 clocks = <&clks 36>;
725 };
727 sd2: sdhci@56200000 {
728 cell-index = <2>;
729 compatible = "sirf,prima2-sdhc";
730 reg = <0x56200000 0x100000>;
731 interrupts = <23>;
732 status = "disabled";
733 clocks = <&clks 37>;
734 };
736 sd3: sdhci@56300000 {
737 cell-index = <3>;
738 compatible = "sirf,prima2-sdhc";
739 reg = <0x56300000 0x100000>;
740 interrupts = <23>;
741 status = "disabled";
742 clocks = <&clks 37>;
743 };
745 sd4: sdhci@56400000 {
746 cell-index = <4>;
747 compatible = "sirf,prima2-sdhc";
748 reg = <0x56400000 0x100000>;
749 interrupts = <39>;
750 status = "disabled";
751 clocks = <&clks 38>;
752 };
754 sd5: sdhci@56500000 {
755 cell-index = <5>;
756 compatible = "sirf,prima2-sdhc";
757 reg = <0x56500000 0x100000>;
758 interrupts = <39>;
759 clocks = <&clks 38>;
760 };
762 pci-copy@57900000 {
763 compatible = "sirf,prima2-pcicp";
764 reg = <0x57900000 0x100000>;
765 interrupts = <40>;
766 };
768 rom-interface@57a00000 {
769 compatible = "sirf,prima2-romif";
770 reg = <0x57a00000 0x100000>;
771 };
772 };
773 };
775 rtc-iobg {
776 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
777 #address-cells = <1>;
778 #size-cells = <1>;
779 reg = <0x80030000 0x10000>;
781 gpsrtc@1000 {
782 compatible = "sirf,prima2-gpsrtc";
783 reg = <0x1000 0x1000>;
784 interrupts = <55 56 57>;
785 };
787 sysrtc@2000 {
788 compatible = "sirf,prima2-sysrtc";
789 reg = <0x2000 0x1000>;
790 interrupts = <52 53 54>;
791 };
793 minigpsrtc@2000 {
794 compatible = "sirf,prima2-minigpsrtc";
795 reg = <0x2000 0x1000>;
796 interrupts = <54>;
797 };
799 pwrc@3000 {
800 compatible = "sirf,prima2-pwrc";
801 reg = <0x3000 0x1000>;
802 interrupts = <32>;
803 };
804 };
806 uus-iobg {
807 compatible = "simple-bus";
808 #address-cells = <1>;
809 #size-cells = <1>;
810 ranges = <0xb8000000 0xb8000000 0x40000>;
812 usb0: usb@b00e0000 {
813 compatible = "chipidea,ci13611a-prima2";
814 reg = <0xb8000000 0x10000>;
815 interrupts = <10>;
816 clocks = <&clks 40>;
817 };
819 usb1: usb@b00f0000 {
820 compatible = "chipidea,ci13611a-prima2";
821 reg = <0xb8010000 0x10000>;
822 interrupts = <11>;
823 clocks = <&clks 41>;
824 };
826 sata@b00f0000 {
827 compatible = "synopsys,dwc-ahsata";
828 reg = <0xb8020000 0x10000>;
829 interrupts = <37>;
830 };
832 security@b00f0000 {
833 compatible = "sirf,prima2-security";
834 reg = <0xb8030000 0x10000>;
835 interrupts = <42>;
836 clocks = <&clks 7>;
837 };
838 };
839 };
840 };