arch/arm/boot/dts/qcom-msm8660.dtsi

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8
   9 / {
  10         model = "Qualcomm MSM8660";
  11         compatible = "qcom,msm8660";
  12         interrupt-parent = <&intc>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         compatible = "qcom,scorpion";
  20                         enable-method = "qcom,gcc-msm8660";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                 };
  25
  26                 cpu@1 {
  27                         compatible = "qcom,scorpion";
  28                         enable-method = "qcom,gcc-msm8660";
  29                         device_type = "cpu";
  30                         reg = <1>;
  31                         next-level-cache = <&L2>;
  32                 };
  33
  34                 L2: l2-cache {
  35                         compatible = "cache";
  36                         cache-level = <2>;
  37                 };
  38         };
  39
  40         cpu-pmu {
  41                 compatible = "qcom,scorpion-mp-pmu";
  42                 interrupts = <1 9 0x304>;
  43         };
  44
  45         soc: soc {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges;
  49                 compatible = "simple-bus";
  50
  51                 intc: interrupt-controller@2080000 {
  52                         compatible = "qcom,msm-8660-qgic";
  53                         interrupt-controller;
  54                         #interrupt-cells = <3>;
  55                         reg = < 0x02080000 0x1000 >,
  56                               < 0x02081000 0x1000 >;
  57                 };
  58
  59                 timer@2000000 {
  60                         compatible = "qcom,scss-timer", "qcom,msm-timer";
  61                         interrupts = <1 0 0x301>,
  62                                      <1 1 0x301>,
  63                                      <1 2 0x301>;
  64                         reg = <0x02000000 0x100>;
  65                         clock-frequency = <27000000>,
  66                                           <32768>;
  67                         cpu-offset = <0x40000>;
  68                 };
  69
  70                 tlmm: pinctrl@800000 {
  71                         compatible = "qcom,msm8660-pinctrl";
  72                         reg = <0x800000 0x4000>;
  73
  74                         gpio-controller;
  75                         #gpio-cells = <2>;
  76                         interrupts = <0 16 0x4>;
  77                         interrupt-controller;
  78                         #interrupt-cells = <2>;
  79
  80                 };
  81
  82                 gcc: clock-controller@900000 {
  83                         compatible = "qcom,gcc-msm8660";
  84                         #clock-cells = <1>;
  85                         #reset-cells = <1>;
  86                         reg = <0x900000 0x4000>;
  87                 };
  88
  89                 gsbi12: gsbi@19c00000 {
  90                         compatible = "qcom,gsbi-v1.0.0";
  91                         cell-index = <12>;
  92                         reg = <0x19c00000 0x100>;
  93                         clocks = <&gcc GSBI12_H_CLK>;
  94                         clock-names = "iface";
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97                         ranges;
  98
  99                         syscon-tcsr = <&tcsr>;
 100
 101                         gsbi12_serial: serial@19c40000 {
 102                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 103                                 reg = <0x19c40000 0x1000>,
 104                                       <0x19c00000 0x1000>;
 105                                 interrupts = <0 195 0x0>;
 106                                 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 107                                 clock-names = "core", "iface";
 108                                 status = "disabled";
 109                         };
 110                 };
 111
 112                 qcom,ssbi@500000 {
 113                         compatible = "qcom,ssbi";
 114                         reg = <0x500000 0x1000>;
 115                         qcom,controller-type = "pmic-arbiter";
 116
 117                         pmicintc: pmic@0 {
 118                                 compatible = "qcom,pm8058";
 119                                 interrupt-parent = <&tlmm>;
 120                                 interrupts = <88 8>;
 121                                 #interrupt-cells = <2>;
 122                                 interrupt-controller;
 123                                 #address-cells = <1>;
 124                                 #size-cells = <0>;
 125
 126                                 pwrkey@1c {
 127                                         compatible = "qcom,pm8058-pwrkey";
 128                                         reg = <0x1c>;
 129                                         interrupt-parent = <&pmicintc>;
 130                                         interrupts = <50 1>, <51 1>;
 131                                         debounce = <15625>;
 132                                         pull-up;
 133                                 };
 134
 135                                 keypad@148 {
 136                                         compatible = "qcom,pm8058-keypad";
 137                                         reg = <0x148>;
 138                                         interrupt-parent = <&pmicintc>;
 139                                         interrupts = <74 1>, <75 1>;
 140                                         debounce = <15>;
 141                                         scan-delay = <32>;
 142                                         row-hold = <91500>;
 143                                 };
 144
 145                                 rtc@11d {
 146                                         compatible = "qcom,pm8058-rtc";
 147                                         interrupt-parent = <&pmicintc>;
 148                                         interrupts = <39 1>;
 149                                         reg = <0x11d>;
 150                                         allow-set-time;
 151                                 };
 152
 153                                 vibrator@4a {
 154                                         compatible = "qcom,pm8058-vib";
 155                                         reg = <0x4a>;
 156                                 };
 157                         };
 158                 };
 159
 160                 /* Temporary fixed regulator */
 161                 vsdcc_fixed: vsdcc-regulator {
 162                         compatible = "regulator-fixed";
 163                         regulator-name = "SDCC Power";
 164                         regulator-min-microvolt = <2700000>;
 165                         regulator-max-microvolt = <2700000>;
 166                         regulator-always-on;
 167                 };
 168
 169                 amba {
 170                         compatible = "arm,amba-bus";
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173                         ranges;
 174                         sdcc1: sdcc@12400000 {
 175                                 status          = "disabled";
 176                                 compatible      = "arm,pl18x", "arm,primecell";
 177                                 arm,primecell-periphid = <0x00051180>;
 178                                 reg             = <0x12400000 0x8000>;
 179                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 180                                 interrupt-names = "cmd_irq";
 181                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 182                                 clock-names     = "mclk", "apb_pclk";
 183                                 bus-width       = <8>;
 184                                 max-frequency   = <48000000>;
 185                                 non-removable;
 186                                 cap-sd-highspeed;
 187                                 cap-mmc-highspeed;
 188                                 vmmc-supply = <&vsdcc_fixed>;
 189                         };
 190
 191                         sdcc3: sdcc@12180000 {
 192                                 compatible      = "arm,pl18x", "arm,primecell";
 193                                 arm,primecell-periphid = <0x00051180>;
 194                                 status          = "disabled";
 195                                 reg             = <0x12180000 0x8000>;
 196                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 197                                 interrupt-names = "cmd_irq";
 198                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 199                                 clock-names     = "mclk", "apb_pclk";
 200                                 bus-width       = <4>;
 201                                 cap-sd-highspeed;
 202                                 cap-mmc-highspeed;
 203                                 max-frequency   = <48000000>;
 204                                 no-1-8-v;
 205                                 vmmc-supply = <&vsdcc_fixed>;
 206                         };
 207                 };
 208
 209                 tcsr: syscon@1a400000 {
 210                         compatible = "qcom,tcsr-msm8660", "syscon";
 211                         reg = <0x1a400000 0x100>;
 212                 };
 213         };
 214
 215 };