arch/arm/boot/dts/qcom-msm8960.dtsi

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/mfd/qcom-rpm.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9
  10 / {
  11         model = "Qualcomm MSM8960";
  12         compatible = "qcom,msm8960";
  13         interrupt-parent = <&intc>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18                 interrupts = <1 14 0x304>;
  19
  20                 cpu@0 {
  21                         compatible = "qcom,krait";
  22                         enable-method = "qcom,kpss-acc-v1";
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         next-level-cache = <&L2>;
  26                         qcom,acc = <&acc0>;
  27                         qcom,saw = <&saw0>;
  28                 };
  29
  30                 cpu@1 {
  31                         compatible = "qcom,krait";
  32                         enable-method = "qcom,kpss-acc-v1";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         next-level-cache = <&L2>;
  36                         qcom,acc = <&acc1>;
  37                         qcom,saw = <&saw1>;
  38                 };
  39
  40                 L2: l2-cache {
  41                         compatible = "cache";
  42                         cache-level = <2>;
  43                 };
  44         };
  45
  46         cpu-pmu {
  47                 compatible = "qcom,krait-pmu";
  48                 interrupts = <1 10 0x304>;
  49                 qcom,no-pc-write;
  50         };
  51
  52         soc: soc {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 ranges;
  56                 compatible = "simple-bus";
  57
  58                 intc: interrupt-controller@2000000 {
  59                         compatible = "qcom,msm-qgic2";
  60                         interrupt-controller;
  61                         #interrupt-cells = <3>;
  62                         reg = <0x02000000 0x1000>,
  63                               <0x02002000 0x1000>;
  64                 };
  65
  66                 timer@200a000 {
  67                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
  68                         interrupts = <1 1 0x301>,
  69                                      <1 2 0x301>,
  70                                      <1 3 0x301>;
  71                         reg = <0x0200a000 0x100>;
  72                         clock-frequency = <27000000>,
  73                                           <32768>;
  74                         cpu-offset = <0x80000>;
  75                 };
  76
  77                 msmgpio: pinctrl@800000 {
  78                         compatible = "qcom,msm8960-pinctrl";
  79                         gpio-controller;
  80                         #gpio-cells = <2>;
  81                         interrupts = <0 16 0x4>;
  82                         interrupt-controller;
  83                         #interrupt-cells = <2>;
  84                         reg = <0x800000 0x4000>;
  85                 };
  86
  87                 gcc: clock-controller@900000 {
  88                         compatible = "qcom,gcc-msm8960";
  89                         #clock-cells = <1>;
  90                         #reset-cells = <1>;
  91                         reg = <0x900000 0x4000>;
  92                 };
  93
  94                 lcc: clock-controller@28000000 {
  95                         compatible = "qcom,lcc-msm8960";
  96                         reg = <0x28000000 0x1000>;
  97                         #clock-cells = <1>;
  98                         #reset-cells = <1>;
  99                 };
 100
 101                 clock-controller@4000000 {
 102                         compatible = "qcom,mmcc-msm8960";
 103                         reg = <0x4000000 0x1000>;
 104                         #clock-cells = <1>;
 105                         #reset-cells = <1>;
 106                 };
 107
 108                 l2cc: clock-controller@2011000 {
 109                         compatible      = "syscon";
 110                         reg             = <0x2011000 0x1000>;
 111                 };
 112
 113                 rpm@108000 {
 114                         compatible      = "qcom,rpm-msm8960";
 115                         reg             = <0x108000 0x1000>;
 116                         qcom,ipc        = <&l2cc 0x8 2>;
 117
 118                         interrupts      = <0 19 0>, <0 21 0>, <0 22 0>;
 119                         interrupt-names = "ack", "err", "wakeup";
 120
 121                         regulators {
 122                                 compatible = "qcom,rpm-pm8921-regulators";
 123                         };
 124                 };
 125
 126                 acc0: clock-controller@2088000 {
 127                         compatible = "qcom,kpss-acc-v1";
 128                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 129                 };
 130
 131                 acc1: clock-controller@2098000 {
 132                         compatible = "qcom,kpss-acc-v1";
 133                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 134                 };
 135
 136                 saw0: regulator@2089000 {
 137                         compatible = "qcom,saw2";
 138                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 139                         regulator;
 140                 };
 141
 142                 saw1: regulator@2099000 {
 143                         compatible = "qcom,saw2";
 144                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 145                         regulator;
 146                 };
 147
 148                 gsbi5: gsbi@16400000 {
 149                         compatible = "qcom,gsbi-v1.0.0";
 150                         cell-index = <5>;
 151                         reg = <0x16400000 0x100>;
 152                         clocks = <&gcc GSBI5_H_CLK>;
 153                         clock-names = "iface";
 154                         #address-cells = <1>;
 155                         #size-cells = <1>;
 156                         ranges;
 157
 158                         syscon-tcsr = <&tcsr>;
 159
 160                         gsbi5_serial: serial@16440000 {
 161                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 162                                 reg = <0x16440000 0x1000>,
 163                                       <0x16400000 0x1000>;
 164                                 interrupts = <0 154 0x0>;
 165                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 166                                 clock-names = "core", "iface";
 167                                 status = "disabled";
 168                         };
 169                 };
 170
 171                 qcom,ssbi@500000 {
 172                         compatible = "qcom,ssbi";
 173                         reg = <0x500000 0x1000>;
 174                         qcom,controller-type = "pmic-arbiter";
 175
 176                         pmicintc: pmic@0 {
 177                                 compatible = "qcom,pm8921";
 178                                 interrupt-parent = <&msmgpio>;
 179                                 interrupts = <104 8>;
 180                                 #interrupt-cells = <2>;
 181                                 interrupt-controller;
 182                                 #address-cells = <1>;
 183                                 #size-cells = <0>;
 184
 185                                 pwrkey@1c {
 186                                         compatible = "qcom,pm8921-pwrkey";
 187                                         reg = <0x1c>;
 188                                         interrupt-parent = <&pmicintc>;
 189                                         interrupts = <50 1>, <51 1>;
 190                                         debounce = <15625>;
 191                                         pull-up;
 192                                 };
 193
 194                                 keypad@148 {
 195                                         compatible = "qcom,pm8921-keypad";
 196                                         reg = <0x148>;
 197                                         interrupt-parent = <&pmicintc>;
 198                                         interrupts = <74 1>, <75 1>;
 199                                         debounce = <15>;
 200                                         scan-delay = <32>;
 201                                         row-hold = <91500>;
 202                                 };
 203
 204                                 rtc@11d {
 205                                         compatible = "qcom,pm8921-rtc";
 206                                         interrupt-parent = <&pmicintc>;
 207                                         interrupts = <39 1>;
 208                                         reg = <0x11d>;
 209                                         allow-set-time;
 210                                 };
 211                         };
 212                 };
 213
 214                 rng@1a500000 {
 215                         compatible = "qcom,prng";
 216                         reg = <0x1a500000 0x200>;
 217                         clocks = <&gcc PRNG_CLK>;
 218                         clock-names = "core";
 219                 };
 220
 221                 /* Temporary fixed regulator */
 222                 vsdcc_fixed: vsdcc-regulator {
 223                         compatible = "regulator-fixed";
 224                         regulator-name = "SDCC Power";
 225                         regulator-min-microvolt = <2700000>;
 226                         regulator-max-microvolt = <2700000>;
 227                         regulator-always-on;
 228                 };
 229
 230                 amba {
 231                         compatible = "arm,amba-bus";
 232                         #address-cells = <1>;
 233                         #size-cells = <1>;
 234                         ranges;
 235                         sdcc1: sdcc@12400000 {
 236                                 status          = "disabled";
 237                                 compatible      = "arm,pl18x", "arm,primecell";
 238                                 arm,primecell-periphid = <0x00051180>;
 239                                 reg             = <0x12400000 0x8000>;
 240                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 241                                 interrupt-names = "cmd_irq";
 242                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 243                                 clock-names     = "mclk", "apb_pclk";
 244                                 bus-width       = <8>;
 245                                 max-frequency   = <96000000>;
 246                                 non-removable;
 247                                 cap-sd-highspeed;
 248                                 cap-mmc-highspeed;
 249                                 vmmc-supply = <&vsdcc_fixed>;
 250                         };
 251
 252                         sdcc3: sdcc@12180000 {
 253                                 compatible      = "arm,pl18x", "arm,primecell";
 254                                 arm,primecell-periphid = <0x00051180>;
 255                                 status          = "disabled";
 256                                 reg             = <0x12180000 0x8000>;
 257                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 258                                 interrupt-names = "cmd_irq";
 259                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 260                                 clock-names     = "mclk", "apb_pclk";
 261                                 bus-width       = <4>;
 262                                 cap-sd-highspeed;
 263                                 cap-mmc-highspeed;
 264                                 max-frequency   = <192000000>;
 265                                 no-1-8-v;
 266                                 vmmc-supply = <&vsdcc_fixed>;
 267                         };
 268                 };
 269
 270                 tcsr: syscon@1a400000 {
 271                         compatible = "qcom,tcsr-msm8960", "syscon";
 272                         reg = <0x1a400000 0x100>;
 273                 };
 274
 275                 gsbi@16000000 {
 276                         compatible = "qcom,gsbi-v1.0.0";
 277                         cell-index = <1>;
 278                         reg = <0x16000000 0x100>;
 279                         clocks = <&gcc GSBI1_H_CLK>;
 280                         clock-names = "iface";
 281                         #address-cells = <1>;
 282                         #size-cells = <1>;
 283                         ranges;
 284
 285                         spi@16080000 {
 286                                 compatible = "qcom,spi-qup-v1.1.1";
 287                                 #address-cells = <1>;
 288                                 #size-cells = <0>;
 289                                 reg = <0x16080000 0x1000>;
 290                                 interrupts = <0 147 0>;
 291                                 spi-max-frequency = <24000000>;
 292                                 cs-gpios = <&msmgpio 8 0>;
 293
 294                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 295                                 clock-names = "core", "iface";
 296                                 status = "disabled";
 297                         };
 298                 };
 299         };
 300 };