| blob | cb4f7b2798fe23be13facdffaef64430cf168ab1 |
1 /*
2 * Device Tree Source for the r8a73a4 SoC
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
12 #include <dt-bindings/clock/r8a73a4-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
16 / {
17 compatible = "renesas,r8a73a4";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a15";
29 reg = <0>;
30 clock-frequency = <1500000000>;
31 power-domains = <&pd_a2sl>;
32 };
33 };
35 ptm {
36 compatible = "arm,coresight-etm3x";
37 power-domains = <&pd_d4>;
38 };
40 timer {
41 compatible = "arm,armv7-timer";
42 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
43 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
44 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
45 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
46 };
48 dbsc1: memory-controller@e6790000 {
49 compatible = "renesas,dbsc-r8a73a4";
50 reg = <0 0xe6790000 0 0x10000>;
51 power-domains = <&pd_a3bc>;
52 };
54 dbsc2: memory-controller@e67a0000 {
55 compatible = "renesas,dbsc-r8a73a4";
56 reg = <0 0xe67a0000 0 0x10000>;
57 power-domains = <&pd_a3bc>;
58 };
60 dmac: dma-multiplexer {
61 compatible = "renesas,shdma-mux";
62 #dma-cells = <1>;
63 dma-channels = <20>;
64 dma-requests = <256>;
65 #address-cells = <2>;
66 #size-cells = <2>;
67 ranges;
69 dma0: dma-controller@e6700020 {
70 compatible = "renesas,shdma-r8a73a4";
71 reg = <0 0xe6700020 0 0x89e0>;
72 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
73 0 200 IRQ_TYPE_LEVEL_HIGH
74 0 201 IRQ_TYPE_LEVEL_HIGH
75 0 202 IRQ_TYPE_LEVEL_HIGH
76 0 203 IRQ_TYPE_LEVEL_HIGH
77 0 204 IRQ_TYPE_LEVEL_HIGH
78 0 205 IRQ_TYPE_LEVEL_HIGH
79 0 206 IRQ_TYPE_LEVEL_HIGH
80 0 207 IRQ_TYPE_LEVEL_HIGH
81 0 208 IRQ_TYPE_LEVEL_HIGH
82 0 209 IRQ_TYPE_LEVEL_HIGH
83 0 210 IRQ_TYPE_LEVEL_HIGH
84 0 211 IRQ_TYPE_LEVEL_HIGH
85 0 212 IRQ_TYPE_LEVEL_HIGH
86 0 213 IRQ_TYPE_LEVEL_HIGH
87 0 214 IRQ_TYPE_LEVEL_HIGH
88 0 215 IRQ_TYPE_LEVEL_HIGH
89 0 216 IRQ_TYPE_LEVEL_HIGH
90 0 217 IRQ_TYPE_LEVEL_HIGH
91 0 218 IRQ_TYPE_LEVEL_HIGH
92 0 219 IRQ_TYPE_LEVEL_HIGH>;
93 interrupt-names = "error",
94 "ch0", "ch1", "ch2", "ch3",
95 "ch4", "ch5", "ch6", "ch7",
96 "ch8", "ch9", "ch10", "ch11",
97 "ch12", "ch13", "ch14", "ch15",
98 "ch16", "ch17", "ch18", "ch19";
99 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
100 power-domains = <&pd_a3sp>;
101 };
102 };
104 i2c5: i2c@e60b0000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
108 reg = <0 0xe60b0000 0 0x428>;
109 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
111 power-domains = <&pd_a3sp>;
113 status = "disabled";
114 };
116 cmt1: timer@e6130000 {
117 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
118 reg = <0 0xe6130000 0 0x1004>;
119 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
121 clock-names = "fck";
122 power-domains = <&pd_c5>;
124 renesas,channels-mask = <0xff>;
126 status = "disabled";
127 };
129 irqc0: interrupt-controller@e61c0000 {
130 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
131 #interrupt-cells = <2>;
132 interrupt-controller;
133 reg = <0 0xe61c0000 0 0x200>;
134 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
135 <0 1 IRQ_TYPE_LEVEL_HIGH>,
136 <0 2 IRQ_TYPE_LEVEL_HIGH>,
137 <0 3 IRQ_TYPE_LEVEL_HIGH>,
138 <0 4 IRQ_TYPE_LEVEL_HIGH>,
139 <0 5 IRQ_TYPE_LEVEL_HIGH>,
140 <0 6 IRQ_TYPE_LEVEL_HIGH>,
141 <0 7 IRQ_TYPE_LEVEL_HIGH>,
142 <0 8 IRQ_TYPE_LEVEL_HIGH>,
143 <0 9 IRQ_TYPE_LEVEL_HIGH>,
144 <0 10 IRQ_TYPE_LEVEL_HIGH>,
145 <0 11 IRQ_TYPE_LEVEL_HIGH>,
146 <0 12 IRQ_TYPE_LEVEL_HIGH>,
147 <0 13 IRQ_TYPE_LEVEL_HIGH>,
148 <0 14 IRQ_TYPE_LEVEL_HIGH>,
149 <0 15 IRQ_TYPE_LEVEL_HIGH>,
150 <0 16 IRQ_TYPE_LEVEL_HIGH>,
151 <0 17 IRQ_TYPE_LEVEL_HIGH>,
152 <0 18 IRQ_TYPE_LEVEL_HIGH>,
153 <0 19 IRQ_TYPE_LEVEL_HIGH>,
154 <0 20 IRQ_TYPE_LEVEL_HIGH>,
155 <0 21 IRQ_TYPE_LEVEL_HIGH>,
156 <0 22 IRQ_TYPE_LEVEL_HIGH>,
157 <0 23 IRQ_TYPE_LEVEL_HIGH>,
158 <0 24 IRQ_TYPE_LEVEL_HIGH>,
159 <0 25 IRQ_TYPE_LEVEL_HIGH>,
160 <0 26 IRQ_TYPE_LEVEL_HIGH>,
161 <0 27 IRQ_TYPE_LEVEL_HIGH>,
162 <0 28 IRQ_TYPE_LEVEL_HIGH>,
163 <0 29 IRQ_TYPE_LEVEL_HIGH>,
164 <0 30 IRQ_TYPE_LEVEL_HIGH>,
165 <0 31 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
167 power-domains = <&pd_c4>;
168 };
170 irqc1: interrupt-controller@e61c0200 {
171 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
172 #interrupt-cells = <2>;
173 interrupt-controller;
174 reg = <0 0xe61c0200 0 0x200>;
175 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
176 <0 33 IRQ_TYPE_LEVEL_HIGH>,
177 <0 34 IRQ_TYPE_LEVEL_HIGH>,
178 <0 35 IRQ_TYPE_LEVEL_HIGH>,
179 <0 36 IRQ_TYPE_LEVEL_HIGH>,
180 <0 37 IRQ_TYPE_LEVEL_HIGH>,
181 <0 38 IRQ_TYPE_LEVEL_HIGH>,
182 <0 39 IRQ_TYPE_LEVEL_HIGH>,
183 <0 40 IRQ_TYPE_LEVEL_HIGH>,
184 <0 41 IRQ_TYPE_LEVEL_HIGH>,
185 <0 42 IRQ_TYPE_LEVEL_HIGH>,
186 <0 43 IRQ_TYPE_LEVEL_HIGH>,
187 <0 44 IRQ_TYPE_LEVEL_HIGH>,
188 <0 45 IRQ_TYPE_LEVEL_HIGH>,
189 <0 46 IRQ_TYPE_LEVEL_HIGH>,
190 <0 47 IRQ_TYPE_LEVEL_HIGH>,
191 <0 48 IRQ_TYPE_LEVEL_HIGH>,
192 <0 49 IRQ_TYPE_LEVEL_HIGH>,
193 <0 50 IRQ_TYPE_LEVEL_HIGH>,
194 <0 51 IRQ_TYPE_LEVEL_HIGH>,
195 <0 52 IRQ_TYPE_LEVEL_HIGH>,
196 <0 53 IRQ_TYPE_LEVEL_HIGH>,
197 <0 54 IRQ_TYPE_LEVEL_HIGH>,
198 <0 55 IRQ_TYPE_LEVEL_HIGH>,
199 <0 56 IRQ_TYPE_LEVEL_HIGH>,
200 <0 57 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
202 power-domains = <&pd_c4>;
203 };
205 pfc: pfc@e6050000 {
206 compatible = "renesas,pfc-r8a73a4";
207 reg = <0 0xe6050000 0 0x9000>;
208 gpio-controller;
209 #gpio-cells = <2>;
210 gpio-ranges =
211 <&pfc 0 0 31>, <&pfc 32 32 9>,
212 <&pfc 64 64 22>, <&pfc 96 96 31>,
213 <&pfc 128 128 7>, <&pfc 160 160 19>,
214 <&pfc 192 192 31>, <&pfc 224 224 27>,
215 <&pfc 256 256 28>, <&pfc 288 288 21>,
216 <&pfc 320 320 10>;
217 interrupts-extended =
218 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
219 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
220 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
221 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
222 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
223 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
224 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
225 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
226 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
227 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
228 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
229 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
230 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
231 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
232 <&irqc1 24 0>, <&irqc1 25 0>;
233 power-domains = <&pd_c5>;
234 };
236 thermal@e61f0000 {
237 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
238 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
239 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
240 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
242 power-domains = <&pd_c5>;
243 };
245 i2c0: i2c@e6500000 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
249 reg = <0 0xe6500000 0 0x428>;
250 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
252 power-domains = <&pd_a3sp>;
253 status = "disabled";
254 };
256 i2c1: i2c@e6510000 {
257 #address-cells = <1>;
258 #size-cells = <0>;
259 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
260 reg = <0 0xe6510000 0 0x428>;
261 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
263 power-domains = <&pd_a3sp>;
264 status = "disabled";
265 };
267 i2c2: i2c@e6520000 {
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
271 reg = <0 0xe6520000 0 0x428>;
272 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
274 power-domains = <&pd_a3sp>;
275 status = "disabled";
276 };
278 i2c3: i2c@e6530000 {
279 #address-cells = <1>;
280 #size-cells = <0>;
281 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
282 reg = <0 0xe6530000 0 0x428>;
283 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
285 power-domains = <&pd_a3sp>;
286 status = "disabled";
287 };
289 i2c4: i2c@e6540000 {
290 #address-cells = <1>;
291 #size-cells = <0>;
292 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
293 reg = <0 0xe6540000 0 0x428>;
294 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
296 power-domains = <&pd_a3sp>;
297 status = "disabled";
298 };
300 i2c6: i2c@e6550000 {
301 #address-cells = <1>;
302 #size-cells = <0>;
303 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
304 reg = <0 0xe6550000 0 0x428>;
305 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
307 power-domains = <&pd_a3sp>;
308 status = "disabled";
309 };
311 i2c7: i2c@e6560000 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
315 reg = <0 0xe6560000 0 0x428>;
316 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
318 power-domains = <&pd_a3sp>;
319 status = "disabled";
320 };
322 i2c8: i2c@e6570000 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
326 reg = <0 0xe6570000 0 0x428>;
327 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
329 power-domains = <&pd_a3sp>;
330 status = "disabled";
331 };
333 scifb0: serial@e6c20000 {
334 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
335 reg = <0 0xe6c20000 0 0x100>;
336 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
338 clock-names = "sci_ick";
339 power-domains = <&pd_a3sp>;
340 status = "disabled";
341 };
343 scifb1: serial@e6c30000 {
344 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
345 reg = <0 0xe6c30000 0 0x100>;
346 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
348 clock-names = "sci_ick";
349 power-domains = <&pd_a3sp>;
350 status = "disabled";
351 };
353 scifa0: serial@e6c40000 {
354 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
355 reg = <0 0xe6c40000 0 0x100>;
356 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
358 clock-names = "sci_ick";
359 power-domains = <&pd_a3sp>;
360 status = "disabled";
361 };
363 scifa1: serial@e6c50000 {
364 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
365 reg = <0 0xe6c50000 0 0x100>;
366 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
368 clock-names = "sci_ick";
369 power-domains = <&pd_a3sp>;
370 status = "disabled";
371 };
373 scifb2: serial@e6ce0000 {
374 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
375 reg = <0 0xe6ce0000 0 0x100>;
376 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
378 clock-names = "sci_ick";
379 power-domains = <&pd_a3sp>;
380 status = "disabled";
381 };
383 scifb3: serial@e6cf0000 {
384 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
385 reg = <0 0xe6cf0000 0 0x100>;
386 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
388 clock-names = "sci_ick";
389 power-domains = <&pd_c4>;
390 status = "disabled";
391 };
393 sdhi0: sd@ee100000 {
394 compatible = "renesas,sdhi-r8a73a4";
395 reg = <0 0xee100000 0 0x100>;
396 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
398 power-domains = <&pd_a3sp>;
399 cap-sd-highspeed;
400 status = "disabled";
401 };
403 sdhi1: sd@ee120000 {
404 compatible = "renesas,sdhi-r8a73a4";
405 reg = <0 0xee120000 0 0x100>;
406 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
408 power-domains = <&pd_a3sp>;
409 cap-sd-highspeed;
410 status = "disabled";
411 };
413 sdhi2: sd@ee140000 {
414 compatible = "renesas,sdhi-r8a73a4";
415 reg = <0 0xee140000 0 0x100>;
416 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
418 power-domains = <&pd_a3sp>;
419 cap-sd-highspeed;
420 status = "disabled";
421 };
423 mmcif0: mmc@ee200000 {
424 compatible = "renesas,sh-mmcif";
425 reg = <0 0xee200000 0 0x80>;
426 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
428 power-domains = <&pd_a3sp>;
429 reg-io-width = <4>;
430 status = "disabled";
431 };
433 mmcif1: mmc@ee220000 {
434 compatible = "renesas,sh-mmcif";
435 reg = <0 0xee220000 0 0x80>;
436 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
438 power-domains = <&pd_a3sp>;
439 reg-io-width = <4>;
440 status = "disabled";
441 };
443 gic: interrupt-controller@f1001000 {
444 compatible = "arm,gic-400";
445 #interrupt-cells = <3>;
446 #address-cells = <0>;
447 interrupt-controller;
448 reg = <0 0xf1001000 0 0x1000>,
449 <0 0xf1002000 0 0x1000>,
450 <0 0xf1004000 0 0x2000>,
451 <0 0xf1006000 0 0x2000>;
452 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
453 };
455 bsc: bus@fec10000 {
456 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
457 "simple-pm-bus";
458 #address-cells = <1>;
459 #size-cells = <1>;
460 ranges = <0 0 0 0x20000000>;
461 reg = <0 0xfec10000 0 0x400>;
462 clocks = <&zb_clk>;
463 power-domains = <&pd_c4>;
464 };
466 clocks {
467 #address-cells = <2>;
468 #size-cells = <2>;
469 ranges;
471 /* External root clocks */
472 extalr_clk: extalr_clk {
473 compatible = "fixed-clock";
474 #clock-cells = <0>;
475 clock-frequency = <32768>;
476 clock-output-names = "extalr";
477 };
478 extal1_clk: extal1_clk {
479 compatible = "fixed-clock";
480 #clock-cells = <0>;
481 clock-frequency = <25000000>;
482 clock-output-names = "extal1";
483 };
484 extal2_clk: extal2_clk {
485 compatible = "fixed-clock";
486 #clock-cells = <0>;
487 clock-frequency = <48000000>;
488 clock-output-names = "extal2";
489 };
490 fsiack_clk: fsiack_clk {
491 compatible = "fixed-clock";
492 #clock-cells = <0>;
493 /* This value must be overridden by the board. */
494 clock-frequency = <0>;
495 clock-output-names = "fsiack";
496 };
497 fsibck_clk: fsibck_clk {
498 compatible = "fixed-clock";
499 #clock-cells = <0>;
500 /* This value must be overridden by the board. */
501 clock-frequency = <0>;
502 clock-output-names = "fsibck";
503 };
505 /* Special CPG clocks */
506 cpg_clocks: cpg_clocks@e6150000 {
507 compatible = "renesas,r8a73a4-cpg-clocks";
508 reg = <0 0xe6150000 0 0x10000>;
509 clocks = <&extal1_clk>, <&extal2_clk>;
510 #clock-cells = <1>;
511 clock-output-names = "main", "pll0", "pll1", "pll2",
512 "pll2s", "pll2h", "z", "z2",
513 "i", "m3", "b", "m1", "m2",
514 "zx", "zs", "hp";
515 };
517 /* Variable factor clocks (DIV6) */
518 zb_clk: zb_clk@e6150010 {
519 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
520 reg = <0 0xe6150010 0 4>;
521 clocks = <&pll1_div2_clk>, <0>,
522 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
523 #clock-cells = <0>;
524 clock-output-names = "zb";
525 };
526 sdhi0_clk: sdhi0_clk@e6150074 {
527 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
528 reg = <0 0xe6150074 0 4>;
529 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
530 <0>, <&extal2_clk>;
531 #clock-cells = <0>;
532 clock-output-names = "sdhi0ck";
533 };
534 sdhi1_clk: sdhi1_clk@e6150078 {
535 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
536 reg = <0 0xe6150078 0 4>;
537 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
538 <0>, <&extal2_clk>;
539 #clock-cells = <0>;
540 clock-output-names = "sdhi1ck";
541 };
542 sdhi2_clk: sdhi2_clk@e615007c {
543 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
544 reg = <0 0xe615007c 0 4>;
545 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
546 <0>, <&extal2_clk>;
547 #clock-cells = <0>;
548 clock-output-names = "sdhi2ck";
549 };
550 mmc0_clk: mmc0_clk@e6150240 {
551 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
552 reg = <0 0xe6150240 0 4>;
553 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
554 <0>, <&extal2_clk>;
555 #clock-cells = <0>;
556 clock-output-names = "mmc0";
557 };
558 mmc1_clk: mmc1_clk@e6150244 {
559 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
560 reg = <0 0xe6150244 0 4>;
561 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
562 <0>, <&extal2_clk>;
563 #clock-cells = <0>;
564 clock-output-names = "mmc1";
565 };
566 vclk1_clk: vclk1_clk@e6150008 {
567 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
568 reg = <0 0xe6150008 0 4>;
569 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
570 <0>, <&extal2_clk>, <&main_div2_clk>,
571 <&extalr_clk>, <0>, <0>;
572 #clock-cells = <0>;
573 clock-output-names = "vclk1";
574 };
575 vclk2_clk: vclk2_clk@e615000c {
576 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
577 reg = <0 0xe615000c 0 4>;
578 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
579 <0>, <&extal2_clk>, <&main_div2_clk>,
580 <&extalr_clk>, <0>, <0>;
581 #clock-cells = <0>;
582 clock-output-names = "vclk2";
583 };
584 vclk3_clk: vclk3_clk@e615001c {
585 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
586 reg = <0 0xe615001c 0 4>;
587 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
588 <0>, <&extal2_clk>, <&main_div2_clk>,
589 <&extalr_clk>, <0>, <0>;
590 #clock-cells = <0>;
591 clock-output-names = "vclk3";
592 };
593 vclk4_clk: vclk4_clk@e6150014 {
594 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
595 reg = <0 0xe6150014 0 4>;
596 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
597 <0>, <&extal2_clk>, <&main_div2_clk>,
598 <&extalr_clk>, <0>, <0>;
599 #clock-cells = <0>;
600 clock-output-names = "vclk4";
601 };
602 vclk5_clk: vclk5_clk@e6150034 {
603 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
604 reg = <0 0xe6150034 0 4>;
605 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
606 <0>, <&extal2_clk>, <&main_div2_clk>,
607 <&extalr_clk>, <0>, <0>;
608 #clock-cells = <0>;
609 clock-output-names = "vclk5";
610 };
611 fsia_clk: fsia_clk@e6150018 {
612 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
613 reg = <0 0xe6150018 0 4>;
614 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
615 <&fsiack_clk>, <0>;
616 #clock-cells = <0>;
617 clock-output-names = "fsia";
618 };
619 fsib_clk: fsib_clk@e6150090 {
620 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
621 reg = <0 0xe6150090 0 4>;
622 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
623 <&fsibck_clk>, <0>;
624 #clock-cells = <0>;
625 clock-output-names = "fsib";
626 };
627 mp_clk: mp_clk@e6150080 {
628 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
629 reg = <0 0xe6150080 0 4>;
630 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
631 <&extal2_clk>, <&extal2_clk>;
632 #clock-cells = <0>;
633 clock-output-names = "mp";
634 };
635 m4_clk: m4_clk@e6150098 {
636 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
637 reg = <0 0xe6150098 0 4>;
638 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
639 #clock-cells = <0>;
640 clock-output-names = "m4";
641 };
642 hsi_clk: hsi_clk@e615026c {
643 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
644 reg = <0 0xe615026c 0 4>;
645 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
646 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
647 #clock-cells = <0>;
648 clock-output-names = "hsi";
649 };
650 spuv_clk: spuv_clk@e6150094 {
651 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
652 reg = <0 0xe6150094 0 4>;
653 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
654 <&extal2_clk>, <&extal2_clk>;
655 #clock-cells = <0>;
656 clock-output-names = "spuv";
657 };
659 /* Fixed factor clocks */
660 main_div2_clk: main_div2_clk {
661 compatible = "fixed-factor-clock";
662 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
663 #clock-cells = <0>;
664 clock-div = <2>;
665 clock-mult = <1>;
666 clock-output-names = "main_div2";
667 };
668 pll0_div2_clk: pll0_div2_clk {
669 compatible = "fixed-factor-clock";
670 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
671 #clock-cells = <0>;
672 clock-div = <2>;
673 clock-mult = <1>;
674 clock-output-names = "pll0_div2";
675 };
676 pll1_div2_clk: pll1_div2_clk {
677 compatible = "fixed-factor-clock";
678 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
679 #clock-cells = <0>;
680 clock-div = <2>;
681 clock-mult = <1>;
682 clock-output-names = "pll1_div2";
683 };
684 extal1_div2_clk: extal1_div2_clk {
685 compatible = "fixed-factor-clock";
686 clocks = <&extal1_clk>;
687 #clock-cells = <0>;
688 clock-div = <2>;
689 clock-mult = <1>;
690 clock-output-names = "extal1_div2";
691 };
693 /* Gate clocks */
694 mstp2_clks: mstp2_clks@e6150138 {
695 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
696 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
697 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
698 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
699 #clock-cells = <1>;
700 clock-indices = <
701 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
702 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
703 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
704 R8A73A4_CLK_DMAC
705 >;
706 clock-output-names =
707 "scifa0", "scifa1", "scifb0", "scifb1",
708 "scifb2", "scifb3", "dmac";
709 };
710 mstp3_clks: mstp3_clks@e615013c {
711 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
712 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
713 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
714 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
715 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
716 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
717 R8A73A4_CLK_HP>, <&cpg_clocks
718 R8A73A4_CLK_HP>, <&extalr_clk>;
719 #clock-cells = <1>;
720 clock-indices = <
721 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
722 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
723 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
724 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
725 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
726 R8A73A4_CLK_CMT1
727 >;
728 clock-output-names =
729 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
730 "mmcif0", "iic6", "iic7", "iic0", "iic1",
731 "cmt1";
732 };
733 mstp4_clks: mstp4_clks@e6150140 {
734 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
735 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
736 clocks = <&main_div2_clk>, <&main_div2_clk>,
737 <&cpg_clocks R8A73A4_CLK_HP>,
738 <&cpg_clocks R8A73A4_CLK_HP>;
739 #clock-cells = <1>;
740 clock-indices = <
741 R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5
742 R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3
743 >;
744 clock-output-names =
745 "irqc", "iic5", "iic4", "iic3";
746 };
747 mstp5_clks: mstp5_clks@e6150144 {
748 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
749 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
750 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
751 #clock-cells = <1>;
752 clock-indices = <
753 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
754 >;
755 clock-output-names =
756 "thermal", "iic8";
757 };
758 };
760 sysc: system-controller@e6180000 {
761 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
762 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
764 pm-domains {
765 pd_c5: c5 {
766 #address-cells = <1>;
767 #size-cells = <0>;
768 #power-domain-cells = <0>;
770 pd_c4: c4@0 {
771 reg = <0>;
772 #address-cells = <1>;
773 #size-cells = <0>;
774 #power-domain-cells = <0>;
776 pd_a3sg: a3sg@16 {
777 reg = <16>;
778 #power-domain-cells = <0>;
779 };
781 pd_a3ex: a3ex@17 {
782 reg = <17>;
783 #power-domain-cells = <0>;
784 };
786 pd_a3sp: a3sp@18 {
787 reg = <18>;
788 #address-cells = <1>;
789 #size-cells = <0>;
790 #power-domain-cells = <0>;
792 pd_a2us: a2us@19 {
793 reg = <19>;
794 #power-domain-cells = <0>;
795 };
796 };
798 pd_a3sm: a3sm@20 {
799 reg = <20>;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 #power-domain-cells = <0>;
804 pd_a2sl: a2sl@21 {
805 reg = <21>;
806 #power-domain-cells = <0>;
807 };
808 };
810 pd_a3km: a3km@22 {
811 reg = <22>;
812 #address-cells = <1>;
813 #size-cells = <0>;
814 #power-domain-cells = <0>;
816 pd_a2kl: a2kl@23 {
817 reg = <23>;
818 #power-domain-cells = <0>;
819 };
820 };
821 };
823 pd_c4ma: c4ma@1 {
824 reg = <1>;
825 #power-domain-cells = <0>;
826 };
828 pd_c4cl: c4cl@2 {
829 reg = <2>;
830 #power-domain-cells = <0>;
831 };
833 pd_d4: d4@3 {
834 reg = <3>;
835 #power-domain-cells = <0>;
836 };
838 pd_a4bc: a4bc@4 {
839 reg = <4>;
840 #address-cells = <1>;
841 #size-cells = <0>;
842 #power-domain-cells = <0>;
844 pd_a3bc: a3bc@5 {
845 reg = <5>;
846 #power-domain-cells = <0>;
847 };
848 };
850 pd_a4l: a4l@6 {
851 reg = <6>;
852 #power-domain-cells = <0>;
853 };
855 pd_a4lc: a4lc@7 {
856 reg = <7>;
857 #power-domain-cells = <0>;
858 };
860 pd_a4mp: a4mp@8 {
861 reg = <8>;
862 #address-cells = <1>;
863 #size-cells = <0>;
864 #power-domain-cells = <0>;
866 pd_a3mp: a3mp@9 {
867 reg = <9>;
868 #power-domain-cells = <0>;
869 };
871 pd_a3vc: a3vc@10 {
872 reg = <10>;
873 #power-domain-cells = <0>;
874 };
875 };
877 pd_a4sf: a4sf@11 {
878 reg = <11>;
879 #power-domain-cells = <0>;
880 };
882 pd_a3r: a3r@12 {
883 reg = <12>;
884 #address-cells = <1>;
885 #size-cells = <0>;
886 #power-domain-cells = <0>;
888 pd_a2rv: a2rv@13 {
889 reg = <13>;
890 #power-domain-cells = <0>;
891 };
893 pd_a2is: a2is@14 {
894 reg = <14>;
895 #power-domain-cells = <0>;
896 };
897 };
898 };
899 };
900 };
901 };