| blob | a9977d6ee81af21fbb3c2268a2deb8588c300ecf |
1 /*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
12 #include <dt-bindings/clock/r8a7794-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
16 / {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 spi0 = &qspi;
30 vin0 = &vin0;
31 vin1 = &vin1;
32 };
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a7";
41 reg = <0>;
42 clock-frequency = <1000000000>;
43 };
45 cpu1: cpu@1 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a7";
48 reg = <1>;
49 clock-frequency = <1000000000>;
50 };
51 };
53 gic: interrupt-controller@f1001000 {
54 compatible = "arm,gic-400";
55 #interrupt-cells = <3>;
56 #address-cells = <0>;
57 interrupt-controller;
58 reg = <0 0xf1001000 0 0x1000>,
59 <0 0xf1002000 0 0x1000>,
60 <0 0xf1004000 0 0x2000>,
61 <0 0xf1006000 0 0x2000>;
62 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
63 };
65 gpio0: gpio@e6050000 {
66 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
67 reg = <0 0xe6050000 0 0x50>;
68 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
69 #gpio-cells = <2>;
70 gpio-controller;
71 gpio-ranges = <&pfc 0 0 32>;
72 #interrupt-cells = <2>;
73 interrupt-controller;
74 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
75 power-domains = <&cpg_clocks>;
76 };
78 gpio1: gpio@e6051000 {
79 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
80 reg = <0 0xe6051000 0 0x50>;
81 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
82 #gpio-cells = <2>;
83 gpio-controller;
84 gpio-ranges = <&pfc 0 32 26>;
85 #interrupt-cells = <2>;
86 interrupt-controller;
87 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
88 power-domains = <&cpg_clocks>;
89 };
91 gpio2: gpio@e6052000 {
92 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
93 reg = <0 0xe6052000 0 0x50>;
94 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
95 #gpio-cells = <2>;
96 gpio-controller;
97 gpio-ranges = <&pfc 0 64 32>;
98 #interrupt-cells = <2>;
99 interrupt-controller;
100 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
101 power-domains = <&cpg_clocks>;
102 };
104 gpio3: gpio@e6053000 {
105 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
106 reg = <0 0xe6053000 0 0x50>;
107 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
108 #gpio-cells = <2>;
109 gpio-controller;
110 gpio-ranges = <&pfc 0 96 32>;
111 #interrupt-cells = <2>;
112 interrupt-controller;
113 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
114 power-domains = <&cpg_clocks>;
115 };
117 gpio4: gpio@e6054000 {
118 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
119 reg = <0 0xe6054000 0 0x50>;
120 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 gpio-ranges = <&pfc 0 128 32>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
127 power-domains = <&cpg_clocks>;
128 };
130 gpio5: gpio@e6055000 {
131 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
132 reg = <0 0xe6055000 0 0x50>;
133 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
134 #gpio-cells = <2>;
135 gpio-controller;
136 gpio-ranges = <&pfc 0 160 28>;
137 #interrupt-cells = <2>;
138 interrupt-controller;
139 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
140 power-domains = <&cpg_clocks>;
141 };
143 gpio6: gpio@e6055400 {
144 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
145 reg = <0 0xe6055400 0 0x50>;
146 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
147 #gpio-cells = <2>;
148 gpio-controller;
149 gpio-ranges = <&pfc 0 192 26>;
150 #interrupt-cells = <2>;
151 interrupt-controller;
152 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
153 power-domains = <&cpg_clocks>;
154 };
156 cmt0: timer@ffca0000 {
157 compatible = "renesas,cmt-48-gen2";
158 reg = <0 0xffca0000 0 0x1004>;
159 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
160 <0 143 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
162 clock-names = "fck";
163 power-domains = <&cpg_clocks>;
165 renesas,channels-mask = <0x60>;
167 status = "disabled";
168 };
170 cmt1: timer@e6130000 {
171 compatible = "renesas,cmt-48-gen2";
172 reg = <0 0xe6130000 0 0x1004>;
173 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
174 <0 121 IRQ_TYPE_LEVEL_HIGH>,
175 <0 122 IRQ_TYPE_LEVEL_HIGH>,
176 <0 123 IRQ_TYPE_LEVEL_HIGH>,
177 <0 124 IRQ_TYPE_LEVEL_HIGH>,
178 <0 125 IRQ_TYPE_LEVEL_HIGH>,
179 <0 126 IRQ_TYPE_LEVEL_HIGH>,
180 <0 127 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
182 clock-names = "fck";
183 power-domains = <&cpg_clocks>;
185 renesas,channels-mask = <0xff>;
187 status = "disabled";
188 };
190 timer {
191 compatible = "arm,armv7-timer";
192 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
193 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
194 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
195 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
196 };
198 irqc0: interrupt-controller@e61c0000 {
199 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 reg = <0 0xe61c0000 0 0x200>;
203 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
204 <0 1 IRQ_TYPE_LEVEL_HIGH>,
205 <0 2 IRQ_TYPE_LEVEL_HIGH>,
206 <0 3 IRQ_TYPE_LEVEL_HIGH>,
207 <0 12 IRQ_TYPE_LEVEL_HIGH>,
208 <0 13 IRQ_TYPE_LEVEL_HIGH>,
209 <0 14 IRQ_TYPE_LEVEL_HIGH>,
210 <0 15 IRQ_TYPE_LEVEL_HIGH>,
211 <0 16 IRQ_TYPE_LEVEL_HIGH>,
212 <0 17 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
214 power-domains = <&cpg_clocks>;
215 };
217 pfc: pin-controller@e6060000 {
218 compatible = "renesas,pfc-r8a7794";
219 reg = <0 0xe6060000 0 0x11c>;
220 #gpio-range-cells = <3>;
221 };
223 dmac0: dma-controller@e6700000 {
224 compatible = "renesas,rcar-dmac";
225 reg = <0 0xe6700000 0 0x20000>;
226 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
227 0 200 IRQ_TYPE_LEVEL_HIGH
228 0 201 IRQ_TYPE_LEVEL_HIGH
229 0 202 IRQ_TYPE_LEVEL_HIGH
230 0 203 IRQ_TYPE_LEVEL_HIGH
231 0 204 IRQ_TYPE_LEVEL_HIGH
232 0 205 IRQ_TYPE_LEVEL_HIGH
233 0 206 IRQ_TYPE_LEVEL_HIGH
234 0 207 IRQ_TYPE_LEVEL_HIGH
235 0 208 IRQ_TYPE_LEVEL_HIGH
236 0 209 IRQ_TYPE_LEVEL_HIGH
237 0 210 IRQ_TYPE_LEVEL_HIGH
238 0 211 IRQ_TYPE_LEVEL_HIGH
239 0 212 IRQ_TYPE_LEVEL_HIGH
240 0 213 IRQ_TYPE_LEVEL_HIGH
241 0 214 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-names = "error",
243 "ch0", "ch1", "ch2", "ch3",
244 "ch4", "ch5", "ch6", "ch7",
245 "ch8", "ch9", "ch10", "ch11",
246 "ch12", "ch13", "ch14";
247 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
248 clock-names = "fck";
249 power-domains = <&cpg_clocks>;
250 #dma-cells = <1>;
251 dma-channels = <15>;
252 };
254 dmac1: dma-controller@e6720000 {
255 compatible = "renesas,rcar-dmac";
256 reg = <0 0xe6720000 0 0x20000>;
257 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
258 0 216 IRQ_TYPE_LEVEL_HIGH
259 0 217 IRQ_TYPE_LEVEL_HIGH
260 0 218 IRQ_TYPE_LEVEL_HIGH
261 0 219 IRQ_TYPE_LEVEL_HIGH
262 0 308 IRQ_TYPE_LEVEL_HIGH
263 0 309 IRQ_TYPE_LEVEL_HIGH
264 0 310 IRQ_TYPE_LEVEL_HIGH
265 0 311 IRQ_TYPE_LEVEL_HIGH
266 0 312 IRQ_TYPE_LEVEL_HIGH
267 0 313 IRQ_TYPE_LEVEL_HIGH
268 0 314 IRQ_TYPE_LEVEL_HIGH
269 0 315 IRQ_TYPE_LEVEL_HIGH
270 0 316 IRQ_TYPE_LEVEL_HIGH
271 0 317 IRQ_TYPE_LEVEL_HIGH
272 0 318 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "error",
274 "ch0", "ch1", "ch2", "ch3",
275 "ch4", "ch5", "ch6", "ch7",
276 "ch8", "ch9", "ch10", "ch11",
277 "ch12", "ch13", "ch14";
278 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
279 clock-names = "fck";
280 power-domains = <&cpg_clocks>;
281 #dma-cells = <1>;
282 dma-channels = <15>;
283 };
285 scifa0: serial@e6c40000 {
286 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
287 reg = <0 0xe6c40000 0 64>;
288 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
290 clock-names = "sci_ick";
291 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
292 dma-names = "tx", "rx";
293 power-domains = <&cpg_clocks>;
294 status = "disabled";
295 };
297 scifa1: serial@e6c50000 {
298 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
299 reg = <0 0xe6c50000 0 64>;
300 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
302 clock-names = "sci_ick";
303 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
304 dma-names = "tx", "rx";
305 power-domains = <&cpg_clocks>;
306 status = "disabled";
307 };
309 scifa2: serial@e6c60000 {
310 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
311 reg = <0 0xe6c60000 0 64>;
312 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
314 clock-names = "sci_ick";
315 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
316 dma-names = "tx", "rx";
317 power-domains = <&cpg_clocks>;
318 status = "disabled";
319 };
321 scifa3: serial@e6c70000 {
322 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
323 reg = <0 0xe6c70000 0 64>;
324 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
326 clock-names = "sci_ick";
327 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
328 dma-names = "tx", "rx";
329 power-domains = <&cpg_clocks>;
330 status = "disabled";
331 };
333 scifa4: serial@e6c78000 {
334 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
335 reg = <0 0xe6c78000 0 64>;
336 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
338 clock-names = "sci_ick";
339 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
340 dma-names = "tx", "rx";
341 power-domains = <&cpg_clocks>;
342 status = "disabled";
343 };
345 scifa5: serial@e6c80000 {
346 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
347 reg = <0 0xe6c80000 0 64>;
348 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
350 clock-names = "sci_ick";
351 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
352 dma-names = "tx", "rx";
353 power-domains = <&cpg_clocks>;
354 status = "disabled";
355 };
357 scifb0: serial@e6c20000 {
358 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
359 reg = <0 0xe6c20000 0 64>;
360 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
362 clock-names = "sci_ick";
363 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
364 dma-names = "tx", "rx";
365 power-domains = <&cpg_clocks>;
366 status = "disabled";
367 };
369 scifb1: serial@e6c30000 {
370 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
371 reg = <0 0xe6c30000 0 64>;
372 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
374 clock-names = "sci_ick";
375 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
376 dma-names = "tx", "rx";
377 power-domains = <&cpg_clocks>;
378 status = "disabled";
379 };
381 scifb2: serial@e6ce0000 {
382 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
383 reg = <0 0xe6ce0000 0 64>;
384 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
386 clock-names = "sci_ick";
387 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
388 dma-names = "tx", "rx";
389 power-domains = <&cpg_clocks>;
390 status = "disabled";
391 };
393 scif0: serial@e6e60000 {
394 compatible = "renesas,scif-r8a7794", "renesas,scif";
395 reg = <0 0xe6e60000 0 64>;
396 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
398 clock-names = "sci_ick";
399 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
400 dma-names = "tx", "rx";
401 power-domains = <&cpg_clocks>;
402 status = "disabled";
403 };
405 scif1: serial@e6e68000 {
406 compatible = "renesas,scif-r8a7794", "renesas,scif";
407 reg = <0 0xe6e68000 0 64>;
408 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
410 clock-names = "sci_ick";
411 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
412 dma-names = "tx", "rx";
413 power-domains = <&cpg_clocks>;
414 status = "disabled";
415 };
417 scif2: serial@e6e58000 {
418 compatible = "renesas,scif-r8a7794", "renesas,scif";
419 reg = <0 0xe6e58000 0 64>;
420 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
422 clock-names = "sci_ick";
423 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
424 dma-names = "tx", "rx";
425 power-domains = <&cpg_clocks>;
426 status = "disabled";
427 };
429 scif3: serial@e6ea8000 {
430 compatible = "renesas,scif-r8a7794", "renesas,scif";
431 reg = <0 0xe6ea8000 0 64>;
432 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
434 clock-names = "sci_ick";
435 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
436 dma-names = "tx", "rx";
437 power-domains = <&cpg_clocks>;
438 status = "disabled";
439 };
441 scif4: serial@e6ee0000 {
442 compatible = "renesas,scif-r8a7794", "renesas,scif";
443 reg = <0 0xe6ee0000 0 64>;
444 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
446 clock-names = "sci_ick";
447 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
448 dma-names = "tx", "rx";
449 power-domains = <&cpg_clocks>;
450 status = "disabled";
451 };
453 scif5: serial@e6ee8000 {
454 compatible = "renesas,scif-r8a7794", "renesas,scif";
455 reg = <0 0xe6ee8000 0 64>;
456 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
458 clock-names = "sci_ick";
459 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
460 dma-names = "tx", "rx";
461 power-domains = <&cpg_clocks>;
462 status = "disabled";
463 };
465 hscif0: serial@e62c0000 {
466 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
467 reg = <0 0xe62c0000 0 96>;
468 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
470 clock-names = "sci_ick";
471 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
472 dma-names = "tx", "rx";
473 power-domains = <&cpg_clocks>;
474 status = "disabled";
475 };
477 hscif1: serial@e62c8000 {
478 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
479 reg = <0 0xe62c8000 0 96>;
480 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
482 clock-names = "sci_ick";
483 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
484 dma-names = "tx", "rx";
485 power-domains = <&cpg_clocks>;
486 status = "disabled";
487 };
489 hscif2: serial@e62d0000 {
490 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
491 reg = <0 0xe62d0000 0 96>;
492 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
494 clock-names = "sci_ick";
495 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
496 dma-names = "tx", "rx";
497 power-domains = <&cpg_clocks>;
498 status = "disabled";
499 };
501 ether: ethernet@ee700000 {
502 compatible = "renesas,ether-r8a7794";
503 reg = <0 0xee700000 0 0x400>;
504 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
506 power-domains = <&cpg_clocks>;
507 phy-mode = "rmii";
508 #address-cells = <1>;
509 #size-cells = <0>;
510 status = "disabled";
511 };
513 /* The memory map in the User's Manual maps the cores to bus numbers */
514 i2c0: i2c@e6508000 {
515 compatible = "renesas,i2c-r8a7794";
516 reg = <0 0xe6508000 0 0x40>;
517 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
519 power-domains = <&cpg_clocks>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522 status = "disabled";
523 };
525 i2c1: i2c@e6518000 {
526 compatible = "renesas,i2c-r8a7794";
527 reg = <0 0xe6518000 0 0x40>;
528 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
530 power-domains = <&cpg_clocks>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 status = "disabled";
534 };
536 i2c2: i2c@e6530000 {
537 compatible = "renesas,i2c-r8a7794";
538 reg = <0 0xe6530000 0 0x40>;
539 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
541 power-domains = <&cpg_clocks>;
542 #address-cells = <1>;
543 #size-cells = <0>;
544 status = "disabled";
545 };
547 i2c3: i2c@e6540000 {
548 compatible = "renesas,i2c-r8a7794";
549 reg = <0 0xe6540000 0 0x40>;
550 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
552 power-domains = <&cpg_clocks>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 status = "disabled";
556 };
558 i2c4: i2c@e6520000 {
559 compatible = "renesas,i2c-r8a7794";
560 reg = <0 0xe6520000 0 0x40>;
561 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
563 power-domains = <&cpg_clocks>;
564 #address-cells = <1>;
565 #size-cells = <0>;
566 status = "disabled";
567 };
569 i2c5: i2c@e6528000 {
570 compatible = "renesas,i2c-r8a7794";
571 reg = <0 0xe6528000 0 0x40>;
572 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
574 power-domains = <&cpg_clocks>;
575 #address-cells = <1>;
576 #size-cells = <0>;
577 status = "disabled";
578 };
580 mmcif0: mmc@ee200000 {
581 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
582 reg = <0 0xee200000 0 0x80>;
583 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
585 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
586 dma-names = "tx", "rx";
587 power-domains = <&cpg_clocks>;
588 reg-io-width = <4>;
589 status = "disabled";
590 };
592 sdhi0: sd@ee100000 {
593 compatible = "renesas,sdhi-r8a7794";
594 reg = <0 0xee100000 0 0x200>;
595 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
597 power-domains = <&cpg_clocks>;
598 status = "disabled";
599 };
601 sdhi1: sd@ee140000 {
602 compatible = "renesas,sdhi-r8a7794";
603 reg = <0 0xee140000 0 0x100>;
604 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
606 power-domains = <&cpg_clocks>;
607 status = "disabled";
608 };
610 sdhi2: sd@ee160000 {
611 compatible = "renesas,sdhi-r8a7794";
612 reg = <0 0xee160000 0 0x100>;
613 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
615 power-domains = <&cpg_clocks>;
616 status = "disabled";
617 };
619 qspi: spi@e6b10000 {
620 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
621 reg = <0 0xe6b10000 0 0x2c>;
622 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
624 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
625 dma-names = "tx", "rx";
626 power-domains = <&cpg_clocks>;
627 num-cs = <1>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630 status = "disabled";
631 };
633 vin0: video@e6ef0000 {
634 compatible = "renesas,vin-r8a7794";
635 reg = <0 0xe6ef0000 0 0x1000>;
636 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
638 power-domains = <&cpg_clocks>;
639 status = "disabled";
640 };
642 vin1: video@e6ef1000 {
643 compatible = "renesas,vin-r8a7794";
644 reg = <0 0xe6ef1000 0 0x1000>;
645 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
647 power-domains = <&cpg_clocks>;
648 status = "disabled";
649 };
651 pci0: pci@ee090000 {
652 compatible = "renesas,pci-r8a7794";
653 device_type = "pci";
654 reg = <0 0xee090000 0 0xc00>,
655 <0 0xee080000 0 0x1100>;
656 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
658 power-domains = <&cpg_clocks>;
659 status = "disabled";
661 bus-range = <0 0>;
662 #address-cells = <3>;
663 #size-cells = <2>;
664 #interrupt-cells = <1>;
665 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
666 interrupt-map-mask = <0xff00 0 0 0x7>;
667 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
668 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
669 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
671 usb@0,1 {
672 reg = <0x800 0 0 0 0>;
673 device_type = "pci";
674 phys = <&usb0 0>;
675 phy-names = "usb";
676 };
678 usb@0,2 {
679 reg = <0x1000 0 0 0 0>;
680 device_type = "pci";
681 phys = <&usb0 0>;
682 phy-names = "usb";
683 };
684 };
686 pci1: pci@ee0d0000 {
687 compatible = "renesas,pci-r8a7794";
688 device_type = "pci";
689 reg = <0 0xee0d0000 0 0xc00>,
690 <0 0xee0c0000 0 0x1100>;
691 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
693 power-domains = <&cpg_clocks>;
694 status = "disabled";
696 bus-range = <1 1>;
697 #address-cells = <3>;
698 #size-cells = <2>;
699 #interrupt-cells = <1>;
700 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
701 interrupt-map-mask = <0xff00 0 0 0x7>;
702 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
703 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
704 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
706 usb@0,1 {
707 reg = <0x800 0 0 0 0>;
708 device_type = "pci";
709 phys = <&usb2 0>;
710 phy-names = "usb";
711 };
713 usb@0,2 {
714 reg = <0x1000 0 0 0 0>;
715 device_type = "pci";
716 phys = <&usb2 0>;
717 phy-names = "usb";
718 };
719 };
721 hsusb: usb@e6590000 {
722 compatible = "renesas,usbhs-r8a7794";
723 reg = <0 0xe6590000 0 0x100>;
724 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
726 power-domains = <&cpg_clocks>;
727 renesas,buswait = <4>;
728 phys = <&usb0 1>;
729 phy-names = "usb";
730 status = "disabled";
731 };
733 usbphy: usb-phy@e6590100 {
734 compatible = "renesas,usb-phy-r8a7794";
735 reg = <0 0xe6590100 0 0x100>;
736 #address-cells = <1>;
737 #size-cells = <0>;
738 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
739 clock-names = "usbhs";
740 power-domains = <&cpg_clocks>;
741 status = "disabled";
743 usb0: usb-channel@0 {
744 reg = <0>;
745 #phy-cells = <1>;
746 };
747 usb2: usb-channel@2 {
748 reg = <2>;
749 #phy-cells = <1>;
750 };
751 };
753 clocks {
754 #address-cells = <2>;
755 #size-cells = <2>;
756 ranges;
758 /* External root clock */
759 extal_clk: extal_clk {
760 compatible = "fixed-clock";
761 #clock-cells = <0>;
762 /* This value must be overriden by the board. */
763 clock-frequency = <0>;
764 clock-output-names = "extal";
765 };
767 /* Special CPG clocks */
768 cpg_clocks: cpg_clocks@e6150000 {
769 compatible = "renesas,r8a7794-cpg-clocks",
770 "renesas,rcar-gen2-cpg-clocks";
771 reg = <0 0xe6150000 0 0x1000>;
772 clocks = <&extal_clk>;
773 #clock-cells = <1>;
774 clock-output-names = "main", "pll0", "pll1", "pll3",
775 "lb", "qspi", "sdh", "sd0", "z";
776 #power-domain-cells = <0>;
777 };
778 /* Variable factor clocks */
779 sd2_clk: sd2_clk@e6150078 {
780 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
781 reg = <0 0xe6150078 0 4>;
782 clocks = <&pll1_div2_clk>;
783 #clock-cells = <0>;
784 clock-output-names = "sd2";
785 };
786 sd3_clk: sd3_clk@e615026c {
787 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
788 reg = <0 0xe615026c 0 4>;
789 clocks = <&pll1_div2_clk>;
790 #clock-cells = <0>;
791 clock-output-names = "sd3";
792 };
793 mmc0_clk: mmc0_clk@e6150240 {
794 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
795 reg = <0 0xe6150240 0 4>;
796 clocks = <&pll1_div2_clk>;
797 #clock-cells = <0>;
798 clock-output-names = "mmc0";
799 };
801 /* Fixed factor clocks */
802 pll1_div2_clk: pll1_div2_clk {
803 compatible = "fixed-factor-clock";
804 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
805 #clock-cells = <0>;
806 clock-div = <2>;
807 clock-mult = <1>;
808 clock-output-names = "pll1_div2";
809 };
810 zg_clk: zg_clk {
811 compatible = "fixed-factor-clock";
812 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
813 #clock-cells = <0>;
814 clock-div = <6>;
815 clock-mult = <1>;
816 clock-output-names = "zg";
817 };
818 zx_clk: zx_clk {
819 compatible = "fixed-factor-clock";
820 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
821 #clock-cells = <0>;
822 clock-div = <3>;
823 clock-mult = <1>;
824 clock-output-names = "zx";
825 };
826 zs_clk: zs_clk {
827 compatible = "fixed-factor-clock";
828 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
829 #clock-cells = <0>;
830 clock-div = <6>;
831 clock-mult = <1>;
832 clock-output-names = "zs";
833 };
834 hp_clk: hp_clk {
835 compatible = "fixed-factor-clock";
836 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
837 #clock-cells = <0>;
838 clock-div = <12>;
839 clock-mult = <1>;
840 clock-output-names = "hp";
841 };
842 i_clk: i_clk {
843 compatible = "fixed-factor-clock";
844 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
845 #clock-cells = <0>;
846 clock-div = <2>;
847 clock-mult = <1>;
848 clock-output-names = "i";
849 };
850 b_clk: b_clk {
851 compatible = "fixed-factor-clock";
852 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
853 #clock-cells = <0>;
854 clock-div = <12>;
855 clock-mult = <1>;
856 clock-output-names = "b";
857 };
858 p_clk: p_clk {
859 compatible = "fixed-factor-clock";
860 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
861 #clock-cells = <0>;
862 clock-div = <24>;
863 clock-mult = <1>;
864 clock-output-names = "p";
865 };
866 cl_clk: cl_clk {
867 compatible = "fixed-factor-clock";
868 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
869 #clock-cells = <0>;
870 clock-div = <48>;
871 clock-mult = <1>;
872 clock-output-names = "cl";
873 };
874 m2_clk: m2_clk {
875 compatible = "fixed-factor-clock";
876 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
877 #clock-cells = <0>;
878 clock-div = <8>;
879 clock-mult = <1>;
880 clock-output-names = "m2";
881 };
882 imp_clk: imp_clk {
883 compatible = "fixed-factor-clock";
884 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
885 #clock-cells = <0>;
886 clock-div = <4>;
887 clock-mult = <1>;
888 clock-output-names = "imp";
889 };
890 rclk_clk: rclk_clk {
891 compatible = "fixed-factor-clock";
892 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
893 #clock-cells = <0>;
894 clock-div = <(48 * 1024)>;
895 clock-mult = <1>;
896 clock-output-names = "rclk";
897 };
898 oscclk_clk: oscclk_clk {
899 compatible = "fixed-factor-clock";
900 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
901 #clock-cells = <0>;
902 clock-div = <(12 * 1024)>;
903 clock-mult = <1>;
904 clock-output-names = "oscclk";
905 };
906 zb3_clk: zb3_clk {
907 compatible = "fixed-factor-clock";
908 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
909 #clock-cells = <0>;
910 clock-div = <4>;
911 clock-mult = <1>;
912 clock-output-names = "zb3";
913 };
914 zb3d2_clk: zb3d2_clk {
915 compatible = "fixed-factor-clock";
916 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
917 #clock-cells = <0>;
918 clock-div = <8>;
919 clock-mult = <1>;
920 clock-output-names = "zb3d2";
921 };
922 ddr_clk: ddr_clk {
923 compatible = "fixed-factor-clock";
924 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
925 #clock-cells = <0>;
926 clock-div = <8>;
927 clock-mult = <1>;
928 clock-output-names = "ddr";
929 };
930 mp_clk: mp_clk {
931 compatible = "fixed-factor-clock";
932 clocks = <&pll1_div2_clk>;
933 #clock-cells = <0>;
934 clock-div = <15>;
935 clock-mult = <1>;
936 clock-output-names = "mp";
937 };
938 cp_clk: cp_clk {
939 compatible = "fixed-factor-clock";
940 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
941 #clock-cells = <0>;
942 clock-div = <48>;
943 clock-mult = <1>;
944 clock-output-names = "cp";
945 };
947 acp_clk: acp_clk {
948 compatible = "fixed-factor-clock";
949 clocks = <&extal_clk>;
950 #clock-cells = <0>;
951 clock-div = <2>;
952 clock-mult = <1>;
953 clock-output-names = "acp";
954 };
956 /* Gate clocks */
957 mstp0_clks: mstp0_clks@e6150130 {
958 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
959 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
960 clocks = <&mp_clk>;
961 #clock-cells = <1>;
962 clock-indices = <R8A7794_CLK_MSIOF0>;
963 clock-output-names = "msiof0";
964 };
965 mstp1_clks: mstp1_clks@e6150134 {
966 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
967 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
968 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
969 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
970 <&zs_clk>, <&zs_clk>;
971 #clock-cells = <1>;
972 clock-indices = <
973 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
974 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
975 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
976 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
977 >;
978 clock-output-names =
979 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
980 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
981 };
982 mstp2_clks: mstp2_clks@e6150138 {
983 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
984 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
985 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
986 <&mp_clk>, <&mp_clk>, <&mp_clk>,
987 <&zs_clk>, <&zs_clk>;
988 #clock-cells = <1>;
989 clock-indices = <
990 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
991 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
992 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
993 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
994 >;
995 clock-output-names =
996 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
997 "scifb1", "msiof1", "scifb2",
998 "sys-dmac1", "sys-dmac0";
999 };
1000 mstp3_clks: mstp3_clks@e615013c {
1001 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1002 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1003 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1004 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1005 #clock-cells = <1>;
1006 clock-indices = <
1007 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1008 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
1009 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1010 >;
1011 clock-output-names =
1012 "sdhi2", "sdhi1", "sdhi0",
1013 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
1014 };
1015 mstp4_clks: mstp4_clks@e6150140 {
1016 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1017 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1018 clocks = <&cp_clk>;
1019 #clock-cells = <1>;
1020 clock-indices = <R8A7794_CLK_IRQC>;
1021 clock-output-names = "irqc";
1022 };
1023 mstp7_clks: mstp7_clks@e615014c {
1024 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1025 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1026 clocks = <&mp_clk>, <&mp_clk>,
1027 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1028 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
1029 #clock-cells = <1>;
1030 clock-indices = <
1031 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1032 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1033 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1034 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1035 R8A7794_CLK_SCIF0
1036 >;
1037 clock-output-names =
1038 "ehci", "hsusb",
1039 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1040 "scif3", "scif2", "scif1", "scif0";
1041 };
1042 mstp8_clks: mstp8_clks@e6150990 {
1043 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1044 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1045 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
1046 #clock-cells = <1>;
1047 clock-indices = <
1048 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
1049 >;
1050 clock-output-names =
1051 "vin1", "vin0", "ether";
1052 };
1053 mstp9_clks: mstp9_clks@e6150994 {
1054 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1055 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1056 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1057 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1058 <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
1059 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1060 #clock-cells = <1>;
1061 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1062 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1063 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1064 R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
1065 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1066 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1067 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1068 clock-output-names =
1069 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1070 "gpio1", "gpio0", "qspi_mod",
1071 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1072 };
1073 mstp11_clks: mstp11_clks@e615099c {
1074 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1075 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1076 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1077 #clock-cells = <1>;
1078 clock-indices = <
1079 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1080 >;
1081 clock-output-names = "scifa3", "scifa4", "scifa5";
1082 };
1083 };
1085 ipmmu_sy0: mmu@e6280000 {
1086 compatible = "renesas,ipmmu-vmsa";
1087 reg = <0 0xe6280000 0 0x1000>;
1088 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1089 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1090 #iommu-cells = <1>;
1091 status = "disabled";
1092 };
1094 ipmmu_sy1: mmu@e6290000 {
1095 compatible = "renesas,ipmmu-vmsa";
1096 reg = <0 0xe6290000 0 0x1000>;
1097 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1098 #iommu-cells = <1>;
1099 status = "disabled";
1100 };
1102 ipmmu_ds: mmu@e6740000 {
1103 compatible = "renesas,ipmmu-vmsa";
1104 reg = <0 0xe6740000 0 0x1000>;
1105 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1106 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1107 #iommu-cells = <1>;
1108 };
1110 ipmmu_mp: mmu@ec680000 {
1111 compatible = "renesas,ipmmu-vmsa";
1112 reg = <0 0xec680000 0 0x1000>;
1113 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1114 #iommu-cells = <1>;
1115 status = "disabled";
1116 };
1118 ipmmu_mx: mmu@fe951000 {
1119 compatible = "renesas,ipmmu-vmsa";
1120 reg = <0 0xfe951000 0 0x1000>;
1121 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1122 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1123 #iommu-cells = <1>;
1124 };
1126 ipmmu_gp: mmu@e62a0000 {
1127 compatible = "renesas,ipmmu-vmsa";
1128 reg = <0 0xe62a0000 0 0x1000>;
1129 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1130 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1131 #iommu-cells = <1>;
1132 status = "disabled";
1133 };
1134 };