arch/arm/boot/dts/rk3288-veyron-speedy.dts

   1 /*
   2  * Google Veyron Speedy Rev 1+ board device tree source
   3  *
   4  * Copyright 2015 Google, Inc
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *  Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "rk3288-veyron-chromebook.dtsi"
  47 #include "cros-ec-sbs.dtsi"
  48
  49 / {
  50         model = "Google Speedy";
  51         compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
  52                      "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
  53                      "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
  54                      "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
  55                      "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
  56
  57         panel_regulator: panel-regulator {
  58                 compatible = "regulator-fixed";
  59                 enable-active-high;
  60                 gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&lcd_enable_h>;
  63                 regulator-name = "panel_regulator";
  64                 vin-supply = <&vcc33_sys>;
  65         };
  66
  67         vcc18_lcd: vcc18-lcd {
  68                 compatible = "regulator-fixed";
  69                 enable-active-high;
  70                 gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
  71                 pinctrl-names = "default";
  72                 pinctrl-0 = <&avdd_1v8_disp_en>;
  73                 regulator-name = "vcc18_lcd";
  74                 regulator-always-on;
  75                 regulator-boot-on;
  76                 vin-supply = <&vcc18_wl>;
  77         };
  78
  79         backlight_regulator: backlight-regulator {
  80                 compatible = "regulator-fixed";
  81                 enable-active-high;
  82                 gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
  83                 pinctrl-names = "default";
  84                 pinctrl-0 = <&bl_pwr_en>;
  85                 regulator-name = "backlight_regulator";
  86                 vin-supply = <&vcc33_sys>;
  87                 startup-delay-us = <15000>;
  88         };
  89 };
  90
  91 &rk808 {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pmic_int_l>;
  94 };
  95
  96 &sdmmc {
  97         disable-wp;
  98         pinctrl-names = "default";
  99         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
 100                         &sdmmc_bus4>;
 101 };
 102
 103 &vcc_5v {
 104         enable-active-high;
 105         gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
 106         pinctrl-names = "default";
 107         pinctrl-0 = <&drv_5v>;
 108 };
 109
 110 &vcc50_hdmi {
 111         enable-active-high;
 112         gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&vcc50_hdmi_en>;
 115 };
 116
 117 &pinctrl {
 118         backlight {
 119                 bl_pwr_en: bl_pwr_en {
 120                         rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
 121                 };
 122         };
 123
 124         buck-5v {
 125                 drv_5v: drv-5v {
 126                         rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
 127                 };
 128         };
 129
 130         hdmi {
 131                 vcc50_hdmi_en: vcc50-hdmi-en {
 132                         rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
 133                 };
 134         };
 135
 136         lcd {
 137                 lcd_enable_h: lcd-en {
 138                         rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
 139                 };
 140
 141                 avdd_1v8_disp_en: avdd-1v8-disp-en {
 142                         rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
 143                 };
 144         };
 145
 146         pmic {
 147                 dvs_1: dvs-1 {
 148                         rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
 149                 };
 150
 151                 dvs_2: dvs-2 {
 152                         rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
 153                 };
 154         };
 155 };