| blob | ff7c8f298f30a58d3ea987f2375acfe3f6e9be34 |
1 /*
2 * Device Tree Source for the SH73A0 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
11 /include/ "skeleton.dtsi"
13 #include <dt-bindings/clock/sh73a0-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
17 / {
18 compatible = "renesas,sh73a0";
19 interrupt-parent = <&gic>;
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <0>;
29 clock-frequency = <1196000000>;
30 power-domains = <&pd_a2sl>;
31 };
32 cpu@1 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a9";
35 reg = <1>;
36 clock-frequency = <1196000000>;
37 power-domains = <&pd_a2sl>;
38 };
39 };
41 timer@f0000600 {
42 compatible = "arm,cortex-a9-twd-timer";
43 reg = <0xf0000600 0x20>;
44 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
45 clocks = <&twd_clk>;
46 };
48 gic: interrupt-controller@f0001000 {
49 compatible = "arm,cortex-a9-gic";
50 #interrupt-cells = <3>;
51 interrupt-controller;
52 reg = <0xf0001000 0x1000>,
53 <0xf0000100 0x100>;
54 };
56 sbsc2: memory-controller@fb400000 {
57 compatible = "renesas,sbsc-sh73a0";
58 reg = <0xfb400000 0x400>;
59 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
60 <0 38 IRQ_TYPE_LEVEL_HIGH>;
61 interrupt-names = "sec", "temp";
62 power-domains = <&pd_a4bc1>;
63 };
65 sbsc1: memory-controller@fe400000 {
66 compatible = "renesas,sbsc-sh73a0";
67 reg = <0xfe400000 0x400>;
68 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
69 <0 36 IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-names = "sec", "temp";
71 power-domains = <&pd_a4bc0>;
72 };
74 pmu {
75 compatible = "arm,cortex-a9-pmu";
76 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
77 <0 56 IRQ_TYPE_LEVEL_HIGH>;
78 };
80 cmt1: timer@e6138000 {
81 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
82 reg = <0xe6138000 0x200>;
83 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
85 clock-names = "fck";
86 power-domains = <&pd_c5>;
88 renesas,channels-mask = <0x3f>;
90 status = "disabled";
91 };
93 irqpin0: interrupt-controller@e6900000 {
94 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
95 #interrupt-cells = <2>;
96 interrupt-controller;
97 reg = <0xe6900000 4>,
98 <0xe6900010 4>,
99 <0xe6900020 1>,
100 <0xe6900040 1>,
101 <0xe6900060 1>;
102 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
103 0 2 IRQ_TYPE_LEVEL_HIGH
104 0 3 IRQ_TYPE_LEVEL_HIGH
105 0 4 IRQ_TYPE_LEVEL_HIGH
106 0 5 IRQ_TYPE_LEVEL_HIGH
107 0 6 IRQ_TYPE_LEVEL_HIGH
108 0 7 IRQ_TYPE_LEVEL_HIGH
109 0 8 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
111 power-domains = <&pd_a4s>;
112 control-parent;
113 };
115 irqpin1: interrupt-controller@e6900004 {
116 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
117 #interrupt-cells = <2>;
118 interrupt-controller;
119 reg = <0xe6900004 4>,
120 <0xe6900014 4>,
121 <0xe6900024 1>,
122 <0xe6900044 1>,
123 <0xe6900064 1>;
124 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
125 0 10 IRQ_TYPE_LEVEL_HIGH
126 0 11 IRQ_TYPE_LEVEL_HIGH
127 0 12 IRQ_TYPE_LEVEL_HIGH
128 0 13 IRQ_TYPE_LEVEL_HIGH
129 0 14 IRQ_TYPE_LEVEL_HIGH
130 0 15 IRQ_TYPE_LEVEL_HIGH
131 0 16 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
133 power-domains = <&pd_a4s>;
134 control-parent;
135 };
137 irqpin2: interrupt-controller@e6900008 {
138 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 reg = <0xe6900008 4>,
142 <0xe6900018 4>,
143 <0xe6900028 1>,
144 <0xe6900048 1>,
145 <0xe6900068 1>;
146 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
147 0 18 IRQ_TYPE_LEVEL_HIGH
148 0 19 IRQ_TYPE_LEVEL_HIGH
149 0 20 IRQ_TYPE_LEVEL_HIGH
150 0 21 IRQ_TYPE_LEVEL_HIGH
151 0 22 IRQ_TYPE_LEVEL_HIGH
152 0 23 IRQ_TYPE_LEVEL_HIGH
153 0 24 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
155 power-domains = <&pd_a4s>;
156 control-parent;
157 };
159 irqpin3: interrupt-controller@e690000c {
160 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
161 #interrupt-cells = <2>;
162 interrupt-controller;
163 reg = <0xe690000c 4>,
164 <0xe690001c 4>,
165 <0xe690002c 1>,
166 <0xe690004c 1>,
167 <0xe690006c 1>;
168 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
169 0 26 IRQ_TYPE_LEVEL_HIGH
170 0 27 IRQ_TYPE_LEVEL_HIGH
171 0 28 IRQ_TYPE_LEVEL_HIGH
172 0 29 IRQ_TYPE_LEVEL_HIGH
173 0 30 IRQ_TYPE_LEVEL_HIGH
174 0 31 IRQ_TYPE_LEVEL_HIGH
175 0 32 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
177 power-domains = <&pd_a4s>;
178 control-parent;
179 };
181 i2c0: i2c@e6820000 {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
185 reg = <0xe6820000 0x425>;
186 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
187 0 168 IRQ_TYPE_LEVEL_HIGH
188 0 169 IRQ_TYPE_LEVEL_HIGH
189 0 170 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
191 power-domains = <&pd_a3sp>;
192 status = "disabled";
193 };
195 i2c1: i2c@e6822000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
199 reg = <0xe6822000 0x425>;
200 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
201 0 52 IRQ_TYPE_LEVEL_HIGH
202 0 53 IRQ_TYPE_LEVEL_HIGH
203 0 54 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
205 power-domains = <&pd_a3sp>;
206 status = "disabled";
207 };
209 i2c2: i2c@e6824000 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
213 reg = <0xe6824000 0x425>;
214 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
215 0 172 IRQ_TYPE_LEVEL_HIGH
216 0 173 IRQ_TYPE_LEVEL_HIGH
217 0 174 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
219 power-domains = <&pd_a3sp>;
220 status = "disabled";
221 };
223 i2c3: i2c@e6826000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
227 reg = <0xe6826000 0x425>;
228 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
229 0 184 IRQ_TYPE_LEVEL_HIGH
230 0 185 IRQ_TYPE_LEVEL_HIGH
231 0 186 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
233 power-domains = <&pd_a3sp>;
234 status = "disabled";
235 };
237 i2c4: i2c@e6828000 {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
241 reg = <0xe6828000 0x425>;
242 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
243 0 188 IRQ_TYPE_LEVEL_HIGH
244 0 189 IRQ_TYPE_LEVEL_HIGH
245 0 190 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
247 power-domains = <&pd_c5>;
248 status = "disabled";
249 };
251 mmcif: mmc@e6bd0000 {
252 compatible = "renesas,sh-mmcif";
253 reg = <0xe6bd0000 0x100>;
254 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
255 0 141 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
257 power-domains = <&pd_a3sp>;
258 reg-io-width = <4>;
259 status = "disabled";
260 };
262 sdhi0: sd@ee100000 {
263 compatible = "renesas,sdhi-sh73a0";
264 reg = <0xee100000 0x100>;
265 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
266 0 84 IRQ_TYPE_LEVEL_HIGH
267 0 85 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
269 power-domains = <&pd_a3sp>;
270 cap-sd-highspeed;
271 status = "disabled";
272 };
274 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
275 sdhi1: sd@ee120000 {
276 compatible = "renesas,sdhi-sh73a0";
277 reg = <0xee120000 0x100>;
278 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
279 0 89 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
281 power-domains = <&pd_a3sp>;
282 toshiba,mmc-wrprotect-disable;
283 cap-sd-highspeed;
284 status = "disabled";
285 };
287 sdhi2: sd@ee140000 {
288 compatible = "renesas,sdhi-sh73a0";
289 reg = <0xee140000 0x100>;
290 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
291 0 105 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
293 power-domains = <&pd_a3sp>;
294 toshiba,mmc-wrprotect-disable;
295 cap-sd-highspeed;
296 status = "disabled";
297 };
299 scifa0: serial@e6c40000 {
300 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
301 reg = <0xe6c40000 0x100>;
302 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
304 clock-names = "sci_ick";
305 power-domains = <&pd_a3sp>;
306 status = "disabled";
307 };
309 scifa1: serial@e6c50000 {
310 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
311 reg = <0xe6c50000 0x100>;
312 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
314 clock-names = "sci_ick";
315 power-domains = <&pd_a3sp>;
316 status = "disabled";
317 };
319 scifa2: serial@e6c60000 {
320 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
321 reg = <0xe6c60000 0x100>;
322 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
324 clock-names = "sci_ick";
325 power-domains = <&pd_a3sp>;
326 status = "disabled";
327 };
329 scifa3: serial@e6c70000 {
330 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
331 reg = <0xe6c70000 0x100>;
332 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
334 clock-names = "sci_ick";
335 power-domains = <&pd_a3sp>;
336 status = "disabled";
337 };
339 scifa4: serial@e6c80000 {
340 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
341 reg = <0xe6c80000 0x100>;
342 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
344 clock-names = "sci_ick";
345 power-domains = <&pd_a3sp>;
346 status = "disabled";
347 };
349 scifa5: serial@e6cb0000 {
350 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
351 reg = <0xe6cb0000 0x100>;
352 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
354 clock-names = "sci_ick";
355 power-domains = <&pd_a3sp>;
356 status = "disabled";
357 };
359 scifa6: serial@e6cc0000 {
360 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
361 reg = <0xe6cc0000 0x100>;
362 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
364 clock-names = "sci_ick";
365 power-domains = <&pd_a3sp>;
366 status = "disabled";
367 };
369 scifa7: serial@e6cd0000 {
370 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
371 reg = <0xe6cd0000 0x100>;
372 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
374 clock-names = "sci_ick";
375 power-domains = <&pd_a3sp>;
376 status = "disabled";
377 };
379 scifb: serial@e6c30000 {
380 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
381 reg = <0xe6c30000 0x100>;
382 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
384 clock-names = "sci_ick";
385 power-domains = <&pd_a3sp>;
386 status = "disabled";
387 };
389 pfc: pfc@e6050000 {
390 compatible = "renesas,pfc-sh73a0";
391 reg = <0xe6050000 0x8000>,
392 <0xe605801c 0x1c>;
393 gpio-controller;
394 #gpio-cells = <2>;
395 gpio-ranges =
396 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
397 <&pfc 288 288 22>;
398 interrupts-extended =
399 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
400 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
401 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
402 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
403 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
404 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
405 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
406 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
407 power-domains = <&pd_c5>;
408 };
410 sysc: system-controller@e6180000 {
411 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
412 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
414 pm-domains {
415 pd_c5: c5 {
416 #address-cells = <1>;
417 #size-cells = <0>;
418 #power-domain-cells = <0>;
420 pd_c4: c4@0 {
421 reg = <0>;
422 #power-domain-cells = <0>;
423 };
425 pd_d4: d4@1 {
426 reg = <1>;
427 #power-domain-cells = <0>;
428 };
430 pd_a4bc0: a4bc0@4 {
431 reg = <4>;
432 #power-domain-cells = <0>;
433 };
435 pd_a4bc1: a4bc1@5 {
436 reg = <5>;
437 #power-domain-cells = <0>;
438 };
440 pd_a4lc0: a4lc0@6 {
441 reg = <6>;
442 #power-domain-cells = <0>;
443 };
445 pd_a4lc1: a4lc1@7 {
446 reg = <7>;
447 #power-domain-cells = <0>;
448 };
450 pd_a4mp: a4mp@8 {
451 reg = <8>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 #power-domain-cells = <0>;
456 pd_a3mp: a3mp@9 {
457 reg = <9>;
458 #power-domain-cells = <0>;
459 };
461 pd_a3vc: a3vc@10 {
462 reg = <10>;
463 #power-domain-cells = <0>;
464 };
465 };
467 pd_a4rm: a4rm@12 {
468 reg = <12>;
469 #address-cells = <1>;
470 #size-cells = <0>;
471 #power-domain-cells = <0>;
473 pd_a3r: a3r@13 {
474 reg = <13>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 #power-domain-cells = <0>;
479 pd_a2rv: a2rv@14 {
480 reg = <14>;
481 #address-cells = <1>;
482 #size-cells = <0>;
483 #power-domain-cells = <0>;
484 };
485 };
486 };
488 pd_a4s: a4s@16 {
489 reg = <16>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 #power-domain-cells = <0>;
494 pd_a3sp: a3sp@17 {
495 reg = <17>;
496 #power-domain-cells = <0>;
497 };
499 pd_a3sg: a3sg@18 {
500 reg = <18>;
501 #power-domain-cells = <0>;
502 };
504 pd_a3sm: a3sm@19 {
505 reg = <19>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508 #power-domain-cells = <0>;
510 pd_a2sl: a2sl@20 {
511 reg = <20>;
512 #power-domain-cells = <0>;
513 };
514 };
515 };
516 };
517 };
518 };
520 sh_fsi2: sound@ec230000 {
521 #sound-dai-cells = <1>;
522 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
523 reg = <0xec230000 0x400>;
524 interrupts = <0 146 0x4>;
525 power-domains = <&pd_a4mp>;
526 status = "disabled";
527 };
529 bsc: bus@fec10000 {
530 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
531 "simple-pm-bus";
532 #address-cells = <1>;
533 #size-cells = <1>;
534 ranges = <0 0 0x20000000>;
535 reg = <0xfec10000 0x400>;
536 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&zb_clk>;
538 power-domains = <&pd_a4s>;
539 };
541 clocks {
542 #address-cells = <1>;
543 #size-cells = <1>;
544 ranges;
546 /* External root clocks */
547 extalr_clk: extalr_clk {
548 compatible = "fixed-clock";
549 #clock-cells = <0>;
550 clock-frequency = <32768>;
551 clock-output-names = "extalr";
552 };
553 extal1_clk: extal1_clk {
554 compatible = "fixed-clock";
555 #clock-cells = <0>;
556 clock-frequency = <26000000>;
557 clock-output-names = "extal1";
558 };
559 extal2_clk: extal2_clk {
560 compatible = "fixed-clock";
561 #clock-cells = <0>;
562 clock-output-names = "extal2";
563 };
564 extcki_clk: extcki_clk {
565 compatible = "fixed-clock";
566 #clock-cells = <0>;
567 clock-output-names = "extcki";
568 };
569 fsiack_clk: fsiack_clk {
570 compatible = "fixed-clock";
571 #clock-cells = <0>;
572 clock-frequency = <0>;
573 clock-output-names = "fsiack";
574 };
575 fsibck_clk: fsibck_clk {
576 compatible = "fixed-clock";
577 #clock-cells = <0>;
578 clock-frequency = <0>;
579 clock-output-names = "fsibck";
580 };
582 /* Special CPG clocks */
583 cpg_clocks: cpg_clocks@e6150000 {
584 compatible = "renesas,sh73a0-cpg-clocks";
585 reg = <0xe6150000 0x10000>;
586 clocks = <&extal1_clk>, <&extal2_clk>;
587 #clock-cells = <1>;
588 clock-output-names = "main", "pll0", "pll1", "pll2",
589 "pll3", "dsi0phy", "dsi1phy",
590 "zg", "m3", "b", "m1", "m2",
591 "z", "zx", "hp";
592 };
594 /* Variable factor clocks (DIV6) */
595 vclk1_clk: vclk1_clk@e6150008 {
596 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
597 reg = <0xe6150008 4>;
598 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
599 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
600 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
601 <0>;
602 #clock-cells = <0>;
603 clock-output-names = "vclk1";
604 };
605 vclk2_clk: vclk2_clk@e615000c {
606 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
607 reg = <0xe615000c 4>;
608 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
609 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
610 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
611 <0>;
612 #clock-cells = <0>;
613 clock-output-names = "vclk2";
614 };
615 vclk3_clk: vclk3_clk@e615001c {
616 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
617 reg = <0xe615001c 4>;
618 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
619 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
620 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
621 <0>;
622 #clock-cells = <0>;
623 clock-output-names = "vclk3";
624 };
625 zb_clk: zb_clk@e6150010 {
626 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
627 reg = <0xe6150010 4>;
628 clocks = <&pll1_div2_clk>, <0>,
629 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
630 #clock-cells = <0>;
631 clock-output-names = "zb";
632 };
633 flctl_clk: flctl_clk@e6150014 {
634 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
635 reg = <0xe6150014 4>;
636 clocks = <&pll1_div2_clk>, <0>,
637 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
638 #clock-cells = <0>;
639 clock-output-names = "flctlck";
640 };
641 sdhi0_clk: sdhi0_clk@e6150074 {
642 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
643 reg = <0xe6150074 4>;
644 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
645 <&pll1_div13_clk>, <0>;
646 #clock-cells = <0>;
647 clock-output-names = "sdhi0ck";
648 };
649 sdhi1_clk: sdhi1_clk@e6150078 {
650 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
651 reg = <0xe6150078 4>;
652 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
653 <&pll1_div13_clk>, <0>;
654 #clock-cells = <0>;
655 clock-output-names = "sdhi1ck";
656 };
657 sdhi2_clk: sdhi2_clk@e615007c {
658 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
659 reg = <0xe615007c 4>;
660 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
661 <&pll1_div13_clk>, <0>;
662 #clock-cells = <0>;
663 clock-output-names = "sdhi2ck";
664 };
665 fsia_clk: fsia_clk@e6150018 {
666 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
667 reg = <0xe6150018 4>;
668 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
669 <&fsiack_clk>, <&fsiack_clk>;
670 #clock-cells = <0>;
671 clock-output-names = "fsia";
672 };
673 fsib_clk: fsib_clk@e6150090 {
674 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
675 reg = <0xe6150090 4>;
676 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
677 <&fsibck_clk>, <&fsibck_clk>;
678 #clock-cells = <0>;
679 clock-output-names = "fsib";
680 };
681 sub_clk: sub_clk@e6150080 {
682 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
683 reg = <0xe6150080 4>;
684 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
685 <&extal2_clk>, <&extal2_clk>;
686 #clock-cells = <0>;
687 clock-output-names = "sub";
688 };
689 spua_clk: spua_clk@e6150084 {
690 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
691 reg = <0xe6150084 4>;
692 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
693 <&extal2_clk>, <&extal2_clk>;
694 #clock-cells = <0>;
695 clock-output-names = "spua";
696 };
697 spuv_clk: spuv_clk@e6150094 {
698 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
699 reg = <0xe6150094 4>;
700 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
701 <&extal2_clk>, <&extal2_clk>;
702 #clock-cells = <0>;
703 clock-output-names = "spuv";
704 };
705 msu_clk: msu_clk@e6150088 {
706 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
707 reg = <0xe6150088 4>;
708 clocks = <&pll1_div2_clk>, <0>,
709 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
710 #clock-cells = <0>;
711 clock-output-names = "msu";
712 };
713 hsi_clk: hsi_clk@e615008c {
714 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
715 reg = <0xe615008c 4>;
716 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
717 <&pll1_div7_clk>, <0>;
718 #clock-cells = <0>;
719 clock-output-names = "hsi";
720 };
721 mfg1_clk: mfg1_clk@e6150098 {
722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
723 reg = <0xe6150098 4>;
724 clocks = <&pll1_div2_clk>, <0>,
725 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
726 #clock-cells = <0>;
727 clock-output-names = "mfg1";
728 };
729 mfg2_clk: mfg2_clk@e615009c {
730 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
731 reg = <0xe615009c 4>;
732 clocks = <&pll1_div2_clk>, <0>,
733 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
734 #clock-cells = <0>;
735 clock-output-names = "mfg2";
736 };
737 dsit_clk: dsit_clk@e6150060 {
738 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
739 reg = <0xe6150060 4>;
740 clocks = <&pll1_div2_clk>, <0>,
741 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
742 #clock-cells = <0>;
743 clock-output-names = "dsit";
744 };
745 dsi0p_clk: dsi0p_clk@e6150064 {
746 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
747 reg = <0xe6150064 4>;
748 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
749 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
750 <&extcki_clk>, <0>, <0>, <0>;
751 #clock-cells = <0>;
752 clock-output-names = "dsi0pck";
753 };
755 /* Fixed factor clocks */
756 main_div2_clk: main_div2_clk {
757 compatible = "fixed-factor-clock";
758 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
759 #clock-cells = <0>;
760 clock-div = <2>;
761 clock-mult = <1>;
762 clock-output-names = "main_div2";
763 };
764 pll1_div2_clk: pll1_div2_clk {
765 compatible = "fixed-factor-clock";
766 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
767 #clock-cells = <0>;
768 clock-div = <2>;
769 clock-mult = <1>;
770 clock-output-names = "pll1_div2";
771 };
772 pll1_div7_clk: pll1_div7_clk {
773 compatible = "fixed-factor-clock";
774 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
775 #clock-cells = <0>;
776 clock-div = <7>;
777 clock-mult = <1>;
778 clock-output-names = "pll1_div7";
779 };
780 pll1_div13_clk: pll1_div13_clk {
781 compatible = "fixed-factor-clock";
782 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
783 #clock-cells = <0>;
784 clock-div = <13>;
785 clock-mult = <1>;
786 clock-output-names = "pll1_div13";
787 };
788 twd_clk: twd_clk {
789 compatible = "fixed-factor-clock";
790 clocks = <&cpg_clocks SH73A0_CLK_Z>;
791 #clock-cells = <0>;
792 clock-div = <4>;
793 clock-mult = <1>;
794 clock-output-names = "twd";
795 };
797 /* Gate clocks */
798 mstp0_clks: mstp0_clks@e6150130 {
799 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
800 reg = <0xe6150130 4>, <0xe6150030 4>;
801 clocks = <&cpg_clocks SH73A0_CLK_HP>;
802 #clock-cells = <1>;
803 clock-indices = <
804 SH73A0_CLK_IIC2
805 >;
806 clock-output-names =
807 "iic2";
808 };
809 mstp1_clks: mstp1_clks@e6150134 {
810 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
811 reg = <0xe6150134 4>, <0xe6150038 4>;
812 clocks = <&cpg_clocks SH73A0_CLK_B>,
813 <&cpg_clocks SH73A0_CLK_B>,
814 <&cpg_clocks SH73A0_CLK_B>,
815 <&cpg_clocks SH73A0_CLK_B>,
816 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
817 <&cpg_clocks SH73A0_CLK_HP>,
818 <&cpg_clocks SH73A0_CLK_ZG>,
819 <&cpg_clocks SH73A0_CLK_B>;
820 #clock-cells = <1>;
821 clock-indices = <
822 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
823 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
824 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
825 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
826 SH73A0_CLK_LCDC0
827 >;
828 clock-output-names =
829 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
830 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
831 };
832 mstp2_clks: mstp2_clks@e6150138 {
833 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
834 reg = <0xe6150138 4>, <0xe6150040 4>;
835 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
836 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
837 <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
838 <&sub_clk>, <&sub_clk>;
839 #clock-cells = <1>;
840 clock-indices = <
841 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
842 SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
843 SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
844 SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
845 SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
846 >;
847 clock-output-names =
848 "scifa7", "sy_dmac", "mp_dmac", "scifa5",
849 "scifb", "scifa0", "scifa1", "scifa2",
850 "scifa3", "scifa4";
851 };
852 mstp3_clks: mstp3_clks@e615013c {
853 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
854 reg = <0xe615013c 4>, <0xe6150048 4>;
855 clocks = <&sub_clk>, <&extalr_clk>,
856 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
857 <&cpg_clocks SH73A0_CLK_HP>,
858 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
859 <&sdhi0_clk>, <&sdhi1_clk>,
860 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
861 <&main_div2_clk>, <&main_div2_clk>,
862 <&main_div2_clk>, <&main_div2_clk>,
863 <&main_div2_clk>;
864 #clock-cells = <1>;
865 clock-indices = <
866 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
867 SH73A0_CLK_FSI SH73A0_CLK_IRDA
868 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
869 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
870 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
871 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
872 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
873 SH73A0_CLK_TPU4
874 >;
875 clock-output-names =
876 "scifa6", "cmt1", "fsi", "irda", "iic1",
877 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
878 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
879 };
880 mstp4_clks: mstp4_clks@e6150140 {
881 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
882 reg = <0xe6150140 4>, <0xe615004c 4>;
883 clocks = <&cpg_clocks SH73A0_CLK_HP>,
884 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
885 #clock-cells = <1>;
886 clock-indices = <
887 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
888 SH73A0_CLK_KEYSC
889 >;
890 clock-output-names =
891 "iic3", "iic4", "keysc";
892 };
893 mstp5_clks: mstp5_clks@e6150144 {
894 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
895 reg = <0xe6150144 4>, <0xe615003c 4>;
896 clocks = <&cpg_clocks SH73A0_CLK_HP>;
897 #clock-cells = <1>;
898 clock-indices = <
899 SH73A0_CLK_INTCA0
900 >;
901 clock-output-names =
902 "intca0";
903 };
904 };
905 };