2 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include "skeleton.dtsi"
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
33 enable-method = "altr,socfpga-a10-smp";
36 compatible = "arm,cortex-a9";
39 next-level-cache = <&L2>;
42 compatible = "arm,cortex-a9";
45 next-level-cache = <&L2>;
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
53 reg = <0xffffd000 0x1000>,
60 compatible = "simple-bus";
62 interrupt-parent = <&intc>;
66 compatible = "arm,amba-bus";
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffda1000 0x1000>;
74 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
75 <0 84 IRQ_TYPE_LEVEL_HIGH>,
76 <0 85 IRQ_TYPE_LEVEL_HIGH>,
77 <0 86 IRQ_TYPE_LEVEL_HIGH>,
78 <0 87 IRQ_TYPE_LEVEL_HIGH>,
79 <0 88 IRQ_TYPE_LEVEL_HIGH>,
80 <0 89 IRQ_TYPE_LEVEL_HIGH>,
81 <0 90 IRQ_TYPE_LEVEL_HIGH>;
89 compatible = "altr,clk-mgr";
90 reg = <0xffd04000 0x1000>;
96 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
98 compatible = "fixed-clock";
101 cb_intosc_ls_clk: cb_intosc_ls_clk {
103 compatible = "fixed-clock";
106 f2s_free_clk: f2s_free_clk {
108 compatible = "fixed-clock";
113 compatible = "fixed-clock";
117 #address-cells = <1>;
120 compatible = "altr,socfpga-a10-pll-clock";
121 clocks = <&osc1>, <&cb_intosc_ls_clk>,
125 main_mpu_base_clk: main_mpu_base_clk {
127 compatible = "altr,socfpga-a10-perip-clk";
128 clocks = <&main_pll>;
129 div-reg = <0x140 0 11>;
132 main_noc_base_clk: main_noc_base_clk {
134 compatible = "altr,socfpga-a10-perip-clk";
135 clocks = <&main_pll>;
136 div-reg = <0x144 0 11>;
139 main_emaca_clk: main_emaca_clk {
141 compatible = "altr,socfpga-a10-perip-clk";
142 clocks = <&main_pll>;
146 main_emacb_clk: main_emacb_clk {
148 compatible = "altr,socfpga-a10-perip-clk";
149 clocks = <&main_pll>;
153 main_emac_ptp_clk: main_emac_ptp_clk {
155 compatible = "altr,socfpga-a10-perip-clk";
156 clocks = <&main_pll>;
160 main_gpio_db_clk: main_gpio_db_clk {
162 compatible = "altr,socfpga-a10-perip-clk";
163 clocks = <&main_pll>;
167 main_sdmmc_clk: main_sdmmc_clk {
169 compatible = "altr,socfpga-a10-perip-clk"
171 clocks = <&main_pll>;
175 main_s2f_usr0_clk: main_s2f_usr0_clk {
177 compatible = "altr,socfpga-a10-perip-clk";
178 clocks = <&main_pll>;
182 main_s2f_usr1_clk: main_s2f_usr1_clk {
184 compatible = "altr,socfpga-a10-perip-clk";
185 clocks = <&main_pll>;
189 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
191 compatible = "altr,socfpga-a10-perip-clk";
192 clocks = <&main_pll>;
196 main_periph_ref_clk: main_periph_ref_clk {
198 compatible = "altr,socfpga-a10-perip-clk";
199 clocks = <&main_pll>;
204 periph_pll: periph_pll {
205 #address-cells = <1>;
208 compatible = "altr,socfpga-a10-pll-clock";
209 clocks = <&osc1>, <&cb_intosc_ls_clk>,
210 <&f2s_free_clk>, <&main_periph_ref_clk>;
213 peri_mpu_base_clk: peri_mpu_base_clk {
215 compatible = "altr,socfpga-a10-perip-clk";
216 clocks = <&periph_pll>;
217 div-reg = <0x140 16 11>;
220 peri_noc_base_clk: peri_noc_base_clk {
222 compatible = "altr,socfpga-a10-perip-clk";
223 clocks = <&periph_pll>;
224 div-reg = <0x144 16 11>;
227 peri_emaca_clk: peri_emaca_clk {
229 compatible = "altr,socfpga-a10-perip-clk";
230 clocks = <&periph_pll>;
234 peri_emacb_clk: peri_emacb_clk {
236 compatible = "altr,socfpga-a10-perip-clk";
237 clocks = <&periph_pll>;
241 peri_emac_ptp_clk: peri_emac_ptp_clk {
243 compatible = "altr,socfpga-a10-perip-clk";
244 clocks = <&periph_pll>;
248 peri_gpio_db_clk: peri_gpio_db_clk {
250 compatible = "altr,socfpga-a10-perip-clk";
251 clocks = <&periph_pll>;
255 peri_sdmmc_clk: peri_sdmmc_clk {
257 compatible = "altr,socfpga-a10-perip-clk";
258 clocks = <&periph_pll>;
262 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
264 compatible = "altr,socfpga-a10-perip-clk";
265 clocks = <&periph_pll>;
269 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
271 compatible = "altr,socfpga-a10-perip-clk";
272 clocks = <&periph_pll>;
276 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
278 compatible = "altr,socfpga-a10-perip-clk";
279 clocks = <&periph_pll>;
284 mpu_free_clk: mpu_free_clk {
286 compatible = "altr,socfpga-a10-perip-clk";
287 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
288 <&osc1>, <&cb_intosc_hs_div2_clk>,
293 noc_free_clk: noc_free_clk {
295 compatible = "altr,socfpga-a10-perip-clk";
296 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
297 <&osc1>, <&cb_intosc_hs_div2_clk>,
302 s2f_user1_free_clk: s2f_user1_free_clk {
304 compatible = "altr,socfpga-a10-perip-clk";
305 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
306 <&osc1>, <&cb_intosc_hs_div2_clk>,
311 sdmmc_free_clk: sdmmc_free_clk {
313 compatible = "altr,socfpga-a10-perip-clk";
314 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
315 <&osc1>, <&cb_intosc_hs_div2_clk>,
321 l4_sys_free_clk: l4_sys_free_clk {
323 compatible = "altr,socfpga-a10-perip-clk";
324 clocks = <&noc_free_clk>;
328 l4_main_clk: l4_main_clk {
330 compatible = "altr,socfpga-a10-gate-clk";
331 clocks = <&noc_free_clk>;
332 div-reg = <0xA8 0 2>;
336 l4_mp_clk: l4_mp_clk {
338 compatible = "altr,socfpga-a10-gate-clk";
339 clocks = <&noc_free_clk>;
340 div-reg = <0xA8 8 2>;
344 l4_sp_clk: l4_sp_clk {
346 compatible = "altr,socfpga-a10-gate-clk";
347 clocks = <&noc_free_clk>;
348 div-reg = <0xA8 16 2>;
352 mpu_periph_clk: mpu_periph_clk {
354 compatible = "altr,socfpga-a10-gate-clk";
355 clocks = <&mpu_free_clk>;
360 sdmmc_clk: sdmmc_clk {
362 compatible = "altr,socfpga-a10-gate-clk";
363 clocks = <&sdmmc_free_clk>;
369 compatible = "altr,socfpga-a10-gate-clk";
370 clocks = <&l4_main_clk>;
371 clk-gate = <0xC8 11>;
376 compatible = "altr,socfpga-a10-gate-clk";
377 clocks = <&l4_mp_clk>;
378 clk-gate = <0xC8 10>;
381 spi_m_clk: spi_m_clk {
383 compatible = "altr,socfpga-a10-gate-clk";
384 clocks = <&l4_main_clk>;
390 compatible = "altr,socfpga-a10-gate-clk";
391 clocks = <&l4_mp_clk>;
395 s2f_usr1_clk: s2f_usr1_clk {
397 compatible = "altr,socfpga-a10-gate-clk";
398 clocks = <&peri_s2f_usr1_clk>;
404 gmac0: ethernet@ff800000 {
405 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
406 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
407 reg = <0xff800000 0x2000>;
408 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-names = "macirq";
410 /* Filled in by bootloader */
411 mac-address = [00 00 00 00 00 00];
412 snps,multicast-filter-bins = <256>;
413 snps,perfect-filter-entries = <128>;
414 tx-fifo-depth = <4096>;
415 rx-fifo-depth = <16384>;
416 clocks = <&l4_mp_clk>;
417 clock-names = "stmmaceth";
418 resets = <&rst EMAC0_RESET>;
419 reset-names = "stmmaceth";
423 gmac1: ethernet@ff802000 {
424 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
425 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
426 reg = <0xff802000 0x2000>;
427 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "macirq";
429 /* Filled in by bootloader */
430 mac-address = [00 00 00 00 00 00];
431 snps,multicast-filter-bins = <256>;
432 snps,perfect-filter-entries = <128>;
433 tx-fifo-depth = <4096>;
434 rx-fifo-depth = <16384>;
435 clocks = <&l4_mp_clk>;
436 clock-names = "stmmaceth";
437 resets = <&rst EMAC1_RESET>;
438 reset-names = "stmmaceth";
442 gmac2: ethernet@ff804000 {
443 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
444 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
445 reg = <0xff804000 0x2000>;
446 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "macirq";
448 /* Filled in by bootloader */
449 mac-address = [00 00 00 00 00 00];
450 snps,multicast-filter-bins = <256>;
451 snps,perfect-filter-entries = <128>;
452 tx-fifo-depth = <4096>;
453 rx-fifo-depth = <16384>;
454 clocks = <&l4_mp_clk>;
455 clock-names = "stmmaceth";
459 gpio0: gpio@ffc02900 {
460 #address-cells = <1>;
462 compatible = "snps,dw-apb-gpio";
463 reg = <0xffc02900 0x100>;
466 porta: gpio-controller@0 {
467 compatible = "snps,dw-apb-gpio-port";
470 snps,nr-gpios = <29>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
478 gpio1: gpio@ffc02a00 {
479 #address-cells = <1>;
481 compatible = "snps,dw-apb-gpio";
482 reg = <0xffc02a00 0x100>;
485 portb: gpio-controller@0 {
486 compatible = "snps,dw-apb-gpio-port";
489 snps,nr-gpios = <29>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
493 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
497 gpio2: gpio@ffc02b00 {
498 #address-cells = <1>;
500 compatible = "snps,dw-apb-gpio";
501 reg = <0xffc02b00 0x100>;
504 portc: gpio-controller@0 {
505 compatible = "snps,dw-apb-gpio-port";
508 snps,nr-gpios = <27>;
510 interrupt-controller;
511 #interrupt-cells = <2>;
512 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
519 compatible = "snps,designware-i2c";
520 reg = <0xffc02200 0x100>;
521 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&l4_sp_clk>;
527 #address-cells = <1>;
529 compatible = "snps,designware-i2c";
530 reg = <0xffc02300 0x100>;
531 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&l4_sp_clk>;
537 #address-cells = <1>;
539 compatible = "snps,designware-i2c";
540 reg = <0xffc02400 0x100>;
541 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&l4_sp_clk>;
547 #address-cells = <1>;
549 compatible = "snps,designware-i2c";
550 reg = <0xffc02500 0x100>;
551 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&l4_sp_clk>;
557 #address-cells = <1>;
559 compatible = "snps,designware-i2c";
560 reg = <0xffc02600 0x100>;
561 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&l4_sp_clk>;
567 compatible = "syscon";
568 reg = <0xffcfb100 0x80>;
572 compatible = "altr,sdram-edac-a10";
573 altr,sdr-syscon = <&sdr>;
574 interrupts = <0 2 4>, <0 0 4>;
577 L2: l2-cache@fffff000 {
578 compatible = "arm,pl310-cache";
579 reg = <0xfffff000 0x1000>;
580 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
585 mmc: dwmmc0@ff808000 {
586 #address-cells = <1>;
588 compatible = "altr,socfpga-dw-mshc";
589 reg = <0xff808000 0x1000>;
590 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
591 fifo-depth = <0x400>;
592 clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
593 clock-names = "biu", "ciu";
597 ocram: sram@ffe00000 {
598 compatible = "mmio-sram";
599 reg = <0xffe00000 0x40000>;
602 rst: rstmgr@ffd05000 {
604 compatible = "altr,rst-mgr";
605 reg = <0xffd05000 0x100>;
606 altr,modrst-offset = <0x20>;
609 scu: snoop-control-unit@ffffc000 {
610 compatible = "arm,cortex-a9-scu";
611 reg = <0xffffc000 0x100>;
614 sysmgr: sysmgr@ffd06000 {
615 compatible = "altr,sys-mgr", "syscon";
616 reg = <0xffd06000 0x300>;
617 cpu1-start-addr = <0xffd06230>;
622 compatible = "arm,cortex-a9-twd-timer";
623 reg = <0xffffc600 0x100>;
624 interrupts = <1 13 0xf04>;
625 clocks = <&mpu_periph_clk>;
628 timer0: timer0@ffc02700 {
629 compatible = "snps,dw-apb-timer";
630 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
631 reg = <0xffc02700 0x100>;
632 clocks = <&l4_sp_clk>;
633 clock-names = "timer";
636 timer1: timer1@ffc02800 {
637 compatible = "snps,dw-apb-timer";
638 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
639 reg = <0xffc02800 0x100>;
640 clocks = <&l4_sp_clk>;
641 clock-names = "timer";
644 timer2: timer2@ffd00000 {
645 compatible = "snps,dw-apb-timer";
646 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
647 reg = <0xffd00000 0x100>;
648 clocks = <&l4_sys_free_clk>;
649 clock-names = "timer";
652 timer3: timer3@ffd00100 {
653 compatible = "snps,dw-apb-timer";
654 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
655 reg = <0xffd01000 0x100>;
656 clocks = <&l4_sys_free_clk>;
657 clock-names = "timer";
660 uart0: serial0@ffc02000 {
661 compatible = "snps,dw-apb-uart";
662 reg = <0xffc02000 0x100>;
663 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&l4_sp_clk>;
670 uart1: serial1@ffc02100 {
671 compatible = "snps,dw-apb-uart";
672 reg = <0xffc02100 0x100>;
673 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&l4_sp_clk>;
682 compatible = "usb-nop-xceiv";
687 compatible = "snps,dwc2";
688 reg = <0xffb00000 0xffff>;
689 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
693 phy-names = "usb2-phy";
698 compatible = "snps,dwc2";
699 reg = <0xffb40000 0xffff>;
700 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
704 phy-names = "usb2-phy";
708 watchdog0: watchdog@ffd00200 {
709 compatible = "snps,dw-wdt";
710 reg = <0xffd00200 0x100>;
711 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&l4_sys_free_clk>;
716 watchdog1: watchdog@ffd00300 {
717 compatible = "snps,dw-wdt";
718 reg = <0xffd00300 0x100>;
719 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&l4_sys_free_clk>;