| blob | 314f59c121620868fae063a8c9fc13d323b5400b |
1 /*
2 * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
3 */
5 #include <dt-bindings/gpio/gpio.h>
6 #include "skeleton.dtsi"
8 / {
9 #address-cells = <1>;
10 #size-cells = <1>;
12 memory {
13 reg = <0x00000000 0x04000000>,
14 <0x08000000 0x04000000>;
15 };
17 L2: l2-cache {
18 compatible = "arm,l210-cache";
19 reg = <0x10210000 0x1000>;
20 interrupt-parent = <&vica>;
21 interrupts = <30>;
22 cache-unified;
23 cache-level = <2>;
24 cache-size = <131072>;
25 cache-sets = <512>;
26 cache-line-size = <32>;
27 /* At full speed latency must be >=2 */
28 arm,tag-latency = <2>;
29 arm,data-latency = <2 2>;
30 arm,dirty-latency = <2>;
31 };
33 mtu0: mtu@101e2000 {
34 /* Nomadik system timer */
35 compatible = "st,nomadik-mtu";
36 reg = <0x101e2000 0x1000>;
37 interrupt-parent = <&vica>;
38 interrupts = <4>;
39 clocks = <&timclk>, <&pclk>;
40 clock-names = "timclk", "apb_pclk";
41 };
43 mtu1: mtu@101e3000 {
44 /* Secondary timer */
45 reg = <0x101e3000 0x1000>;
46 interrupt-parent = <&vica>;
47 interrupts = <5>;
48 clocks = <&timclk>, <&pclk>;
49 clock-names = "timclk", "apb_pclk";
50 };
52 gpio0: gpio@101e4000 {
53 compatible = "st,nomadik-gpio";
54 reg = <0x101e4000 0x80>;
55 interrupt-parent = <&vica>;
56 interrupts = <6>;
57 interrupt-controller;
58 #interrupt-cells = <2>;
59 gpio-controller;
60 #gpio-cells = <2>;
61 gpio-bank = <0>;
62 gpio-ranges = <&pinctrl 0 0 32>;
63 clocks = <&pclk>;
64 };
66 gpio1: gpio@101e5000 {
67 compatible = "st,nomadik-gpio";
68 reg = <0x101e5000 0x80>;
69 interrupt-parent = <&vica>;
70 interrupts = <7>;
71 interrupt-controller;
72 #interrupt-cells = <2>;
73 gpio-controller;
74 #gpio-cells = <2>;
75 gpio-bank = <1>;
76 gpio-ranges = <&pinctrl 0 32 32>;
77 clocks = <&pclk>;
78 };
80 gpio2: gpio@101e6000 {
81 compatible = "st,nomadik-gpio";
82 reg = <0x101e6000 0x80>;
83 interrupt-parent = <&vica>;
84 interrupts = <8>;
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 gpio-controller;
88 #gpio-cells = <2>;
89 gpio-bank = <2>;
90 gpio-ranges = <&pinctrl 0 64 32>;
91 clocks = <&pclk>;
92 };
94 gpio3: gpio@101e7000 {
95 compatible = "st,nomadik-gpio";
96 reg = <0x101e7000 0x80>;
97 ngpio = <28>;
98 interrupt-parent = <&vica>;
99 interrupts = <9>;
100 interrupt-controller;
101 #interrupt-cells = <2>;
102 gpio-controller;
103 #gpio-cells = <2>;
104 gpio-bank = <3>;
105 gpio-ranges = <&pinctrl 0 96 28>;
106 clocks = <&pclk>;
107 };
109 pinctrl: pinctrl {
110 compatible = "stericsson,stn8815-pinctrl";
111 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>;
112 /* Pin configurations */
113 uart1 {
114 uart1_default_mux: uart1_mux {
115 u1_default_mux {
116 function = "u1";
117 groups = "u1_a_1";
118 };
119 };
120 };
121 mmcsd {
122 mmcsd_default_mux: mmcsd_mux {
123 mmcsd_default_mux {
124 function = "mmcsd";
125 groups = "mmcsd_a_1", "mmcsd_b_1";
126 };
127 };
128 mmcsd_default_mode: mmcsd_default {
129 mmcsd_default_cfg1 {
130 /* MCCLK */
131 pins = "GPIO8_B10";
132 ste,output = <0>;
133 };
134 mmcsd_default_cfg2 {
135 /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */
136 pins = "GPIO10_C11", "GPIO15_A12",
137 "GPIO16_C13", "GPIO23_D15";
138 ste,output = <1>;
139 };
140 mmcsd_default_cfg3 {
141 /* MCCMD, MCDAT3-0, MCMSFBCLK */
142 pins = "GPIO9_A10", "GPIO11_B11",
143 "GPIO12_A11", "GPIO13_C12",
144 "GPIO14_B12", "GPIO24_C15";
145 ste,input = <1>;
146 };
147 };
148 };
149 i2c0 {
150 i2c0_default_mux: i2c0_mux {
151 i2c0_default_mux {
152 function = "i2c0";
153 groups = "i2c0_a_1";
154 };
155 };
156 i2c0_default_mode: i2c0_default {
157 i2c0_default_cfg {
158 pins = "GPIO62_D3", "GPIO63_D2";
159 ste,input = <0>;
160 };
161 };
162 };
163 i2c1 {
164 i2c1_default_mux: i2c1_mux {
165 i2c1_default_mux {
166 function = "i2c1";
167 groups = "i2c1_a_1";
168 };
169 };
170 i2c1_default_mode: i2c1_default {
171 i2c1_default_cfg {
172 pins = "GPIO53_L4", "GPIO54_L3";
173 ste,input = <0>;
174 };
175 };
176 };
177 };
179 src: src@101e0000 {
180 compatible = "stericsson,nomadik-src";
181 reg = <0x101e0000 0x1000>;
183 /*
184 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
185 * that is parent of TIMCLK, PLL1 and PLL2
186 */
187 mxtal: mxtal@19.2M {
188 #clock-cells = <0>;
189 compatible = "fixed-clock";
190 clock-frequency = <19200000>;
191 };
193 /*
194 * The 2.4 MHz TIMCLK reference clock is active at
195 * boot time, this is actually the MXTALCLK @19.2 MHz
196 * divided by 8. This clock is used by the timers and
197 * watchdog. See page 105 ff.
198 */
199 timclk: timclk@2.4M {
200 #clock-cells = <0>;
201 compatible = "fixed-factor-clock";
202 clock-div = <8>;
203 clock-mult = <1>;
204 clocks = <&mxtal>;
205 };
207 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
208 pll1: pll1@0 {
209 #clock-cells = <0>;
210 compatible = "st,nomadik-pll-clock";
211 pll-id = <1>;
212 clocks = <&mxtal>;
213 };
215 /* HCLK divides the PLL1 with 1,2,3 or 4 */
216 hclk: hclk@0 {
217 #clock-cells = <0>;
218 compatible = "st,nomadik-hclk-clock";
219 clocks = <&pll1>;
220 };
221 /* The PCLK domain uses HCLK right off */
222 pclk: pclk@0 {
223 #clock-cells = <0>;
224 compatible = "fixed-factor-clock";
225 clock-div = <1>;
226 clock-mult = <1>;
227 clocks = <&hclk>;
228 };
230 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
231 pll2: pll2@0 {
232 #clock-cells = <0>;
233 compatible = "st,nomadik-pll-clock";
234 pll-id = <2>;
235 clocks = <&mxtal>;
236 };
237 clk216: clk216@216M {
238 #clock-cells = <0>;
239 compatible = "fixed-factor-clock";
240 clock-div = <4>;
241 clock-mult = <1>;
242 clocks = <&pll2>;
243 };
244 clk108: clk108@108M {
245 #clock-cells = <0>;
246 compatible = "fixed-factor-clock";
247 clock-div = <2>;
248 clock-mult = <1>;
249 clocks = <&clk216>;
250 };
251 clk72: clk72@72M {
252 #clock-cells = <0>;
253 compatible = "fixed-factor-clock";
254 /* The data sheet does not say how this is derived */
255 clock-div = <12>;
256 clock-mult = <1>;
257 clocks = <&pll2>;
258 };
259 clk48: clk48@48M {
260 #clock-cells = <0>;
261 compatible = "fixed-factor-clock";
262 /* The data sheet does not say how this is derived */
263 clock-div = <18>;
264 clock-mult = <1>;
265 clocks = <&pll2>;
266 };
267 clk27: clk27@27M {
268 #clock-cells = <0>;
269 compatible = "fixed-factor-clock";
270 clock-div = <4>;
271 clock-mult = <1>;
272 clocks = <&clk108>;
273 };
275 /* This apparently exists as well */
276 ulpiclk: ulpiclk@60M {
277 #clock-cells = <0>;
278 compatible = "fixed-clock";
279 clock-frequency = <60000000>;
280 };
282 /*
283 * IP AMBA bus clocks, driving the bus side of the
284 * peripheral clocking, clock gates.
285 */
287 hclkdma0: hclkdma0@48M {
288 #clock-cells = <0>;
289 compatible = "st,nomadik-src-clock";
290 clock-id = <0>;
291 clocks = <&hclk>;
292 };
293 hclksmc: hclksmc@48M {
294 #clock-cells = <0>;
295 compatible = "st,nomadik-src-clock";
296 clock-id = <1>;
297 clocks = <&hclk>;
298 };
299 hclksdram: hclksdram@48M {
300 #clock-cells = <0>;
301 compatible = "st,nomadik-src-clock";
302 clock-id = <2>;
303 clocks = <&hclk>;
304 };
305 hclkdma1: hclkdma1@48M {
306 #clock-cells = <0>;
307 compatible = "st,nomadik-src-clock";
308 clock-id = <3>;
309 clocks = <&hclk>;
310 };
311 hclkclcd: hclkclcd@48M {
312 #clock-cells = <0>;
313 compatible = "st,nomadik-src-clock";
314 clock-id = <4>;
315 clocks = <&hclk>;
316 };
317 pclkirda: pclkirda@48M {
318 #clock-cells = <0>;
319 compatible = "st,nomadik-src-clock";
320 clock-id = <5>;
321 clocks = <&pclk>;
322 };
323 pclkssp: pclkssp@48M {
324 #clock-cells = <0>;
325 compatible = "st,nomadik-src-clock";
326 clock-id = <6>;
327 clocks = <&pclk>;
328 };
329 pclkuart0: pclkuart0@48M {
330 #clock-cells = <0>;
331 compatible = "st,nomadik-src-clock";
332 clock-id = <7>;
333 clocks = <&pclk>;
334 };
335 pclksdi: pclksdi@48M {
336 #clock-cells = <0>;
337 compatible = "st,nomadik-src-clock";
338 clock-id = <8>;
339 clocks = <&pclk>;
340 };
341 pclki2c0: pclki2c0@48M {
342 #clock-cells = <0>;
343 compatible = "st,nomadik-src-clock";
344 clock-id = <9>;
345 clocks = <&pclk>;
346 };
347 pclki2c1: pclki2c1@48M {
348 #clock-cells = <0>;
349 compatible = "st,nomadik-src-clock";
350 clock-id = <10>;
351 clocks = <&pclk>;
352 };
353 pclkuart1: pclkuart1@48M {
354 #clock-cells = <0>;
355 compatible = "st,nomadik-src-clock";
356 clock-id = <11>;
357 clocks = <&pclk>;
358 };
359 pclkmsp0: pclkmsp0@48M {
360 #clock-cells = <0>;
361 compatible = "st,nomadik-src-clock";
362 clock-id = <12>;
363 clocks = <&pclk>;
364 };
365 hclkusb: hclkusb@48M {
366 #clock-cells = <0>;
367 compatible = "st,nomadik-src-clock";
368 clock-id = <13>;
369 clocks = <&hclk>;
370 };
371 hclkdif: hclkdif@48M {
372 #clock-cells = <0>;
373 compatible = "st,nomadik-src-clock";
374 clock-id = <14>;
375 clocks = <&hclk>;
376 };
377 hclksaa: hclksaa@48M {
378 #clock-cells = <0>;
379 compatible = "st,nomadik-src-clock";
380 clock-id = <15>;
381 clocks = <&hclk>;
382 };
383 hclksva: hclksva@48M {
384 #clock-cells = <0>;
385 compatible = "st,nomadik-src-clock";
386 clock-id = <16>;
387 clocks = <&hclk>;
388 };
389 pclkhsi: pclkhsi@48M {
390 #clock-cells = <0>;
391 compatible = "st,nomadik-src-clock";
392 clock-id = <17>;
393 clocks = <&pclk>;
394 };
395 pclkxti: pclkxti@48M {
396 #clock-cells = <0>;
397 compatible = "st,nomadik-src-clock";
398 clock-id = <18>;
399 clocks = <&pclk>;
400 };
401 pclkuart2: pclkuart2@48M {
402 #clock-cells = <0>;
403 compatible = "st,nomadik-src-clock";
404 clock-id = <19>;
405 clocks = <&pclk>;
406 };
407 pclkmsp1: pclkmsp1@48M {
408 #clock-cells = <0>;
409 compatible = "st,nomadik-src-clock";
410 clock-id = <20>;
411 clocks = <&pclk>;
412 };
413 pclkmsp2: pclkmsp2@48M {
414 #clock-cells = <0>;
415 compatible = "st,nomadik-src-clock";
416 clock-id = <21>;
417 clocks = <&pclk>;
418 };
419 pclkowm: pclkowm@48M {
420 #clock-cells = <0>;
421 compatible = "st,nomadik-src-clock";
422 clock-id = <22>;
423 clocks = <&pclk>;
424 };
425 hclkhpi: hclkhpi@48M {
426 #clock-cells = <0>;
427 compatible = "st,nomadik-src-clock";
428 clock-id = <23>;
429 clocks = <&hclk>;
430 };
431 pclkske: pclkske@48M {
432 #clock-cells = <0>;
433 compatible = "st,nomadik-src-clock";
434 clock-id = <24>;
435 clocks = <&pclk>;
436 };
437 pclkhsem: pclkhsem@48M {
438 #clock-cells = <0>;
439 compatible = "st,nomadik-src-clock";
440 clock-id = <25>;
441 clocks = <&pclk>;
442 };
443 hclk3d: hclk3d@48M {
444 #clock-cells = <0>;
445 compatible = "st,nomadik-src-clock";
446 clock-id = <26>;
447 clocks = <&hclk>;
448 };
449 hclkhash: hclkhash@48M {
450 #clock-cells = <0>;
451 compatible = "st,nomadik-src-clock";
452 clock-id = <27>;
453 clocks = <&hclk>;
454 };
455 hclkcryp: hclkcryp@48M {
456 #clock-cells = <0>;
457 compatible = "st,nomadik-src-clock";
458 clock-id = <28>;
459 clocks = <&hclk>;
460 };
461 pclkmshc: pclkmshc@48M {
462 #clock-cells = <0>;
463 compatible = "st,nomadik-src-clock";
464 clock-id = <29>;
465 clocks = <&pclk>;
466 };
467 hclkusbm: hclkusbm@48M {
468 #clock-cells = <0>;
469 compatible = "st,nomadik-src-clock";
470 clock-id = <30>;
471 clocks = <&hclk>;
472 };
473 hclkrng: hclkrng@48M {
474 #clock-cells = <0>;
475 compatible = "st,nomadik-src-clock";
476 clock-id = <31>;
477 clocks = <&hclk>;
478 };
480 /* IP kernel clocks */
481 clcdclk: clcdclk@0 {
482 #clock-cells = <0>;
483 compatible = "st,nomadik-src-clock";
484 clock-id = <36>;
485 clocks = <&clk72 &clk48>;
486 };
487 irdaclk: irdaclk@48M {
488 #clock-cells = <0>;
489 compatible = "st,nomadik-src-clock";
490 clock-id = <37>;
491 clocks = <&clk48>;
492 };
493 sspiclk: sspiclk@48M {
494 #clock-cells = <0>;
495 compatible = "st,nomadik-src-clock";
496 clock-id = <38>;
497 clocks = <&clk48>;
498 };
499 uart0clk: uart0clk@48M {
500 #clock-cells = <0>;
501 compatible = "st,nomadik-src-clock";
502 clock-id = <39>;
503 clocks = <&clk48>;
504 };
505 sdiclk: sdiclk@48M {
506 /* Also called MCCLK in some documents */
507 #clock-cells = <0>;
508 compatible = "st,nomadik-src-clock";
509 clock-id = <40>;
510 clocks = <&clk48>;
511 };
512 i2c0clk: i2c0clk@48M {
513 #clock-cells = <0>;
514 compatible = "st,nomadik-src-clock";
515 clock-id = <41>;
516 clocks = <&clk48>;
517 };
518 i2c1clk: i2c1clk@48M {
519 #clock-cells = <0>;
520 compatible = "st,nomadik-src-clock";
521 clock-id = <42>;
522 clocks = <&clk48>;
523 };
524 uart1clk: uart1clk@48M {
525 #clock-cells = <0>;
526 compatible = "st,nomadik-src-clock";
527 clock-id = <43>;
528 clocks = <&clk48>;
529 };
530 mspclk0: mspclk0@48M {
531 #clock-cells = <0>;
532 compatible = "st,nomadik-src-clock";
533 clock-id = <44>;
534 clocks = <&clk48>;
535 };
536 usbclk: usbclk@48M {
537 #clock-cells = <0>;
538 compatible = "st,nomadik-src-clock";
539 clock-id = <45>;
540 clocks = <&clk48>; /* 48 MHz not ULPI */
541 };
542 difclk: difclk@72M {
543 #clock-cells = <0>;
544 compatible = "st,nomadik-src-clock";
545 clock-id = <46>;
546 clocks = <&clk72>;
547 };
548 ipi2cclk: ipi2cclk@48M {
549 #clock-cells = <0>;
550 compatible = "st,nomadik-src-clock";
551 clock-id = <47>;
552 clocks = <&clk48>; /* Guess */
553 };
554 ipbmcclk: ipbmcclk@48M {
555 #clock-cells = <0>;
556 compatible = "st,nomadik-src-clock";
557 clock-id = <48>;
558 clocks = <&clk48>; /* Guess */
559 };
560 hsiclkrx: hsiclkrx@216M {
561 #clock-cells = <0>;
562 compatible = "st,nomadik-src-clock";
563 clock-id = <49>;
564 clocks = <&clk216>;
565 };
566 hsiclktx: hsiclktx@108M {
567 #clock-cells = <0>;
568 compatible = "st,nomadik-src-clock";
569 clock-id = <50>;
570 clocks = <&clk108>;
571 };
572 uart2clk: uart2clk@48M {
573 #clock-cells = <0>;
574 compatible = "st,nomadik-src-clock";
575 clock-id = <51>;
576 clocks = <&clk48>;
577 };
578 mspclk1: mspclk1@48M {
579 #clock-cells = <0>;
580 compatible = "st,nomadik-src-clock";
581 clock-id = <52>;
582 clocks = <&clk48>;
583 };
584 mspclk2: mspclk2@48M {
585 #clock-cells = <0>;
586 compatible = "st,nomadik-src-clock";
587 clock-id = <53>;
588 clocks = <&clk48>;
589 };
590 owmclk: owmclk@48M {
591 #clock-cells = <0>;
592 compatible = "st,nomadik-src-clock";
593 clock-id = <54>;
594 clocks = <&clk48>; /* Guess */
595 };
596 skeclk: skeclk@48M {
597 #clock-cells = <0>;
598 compatible = "st,nomadik-src-clock";
599 clock-id = <56>;
600 clocks = <&clk48>; /* Guess */
601 };
602 x3dclk: x3dclk@48M {
603 #clock-cells = <0>;
604 compatible = "st,nomadik-src-clock";
605 clock-id = <58>;
606 clocks = <&clk48>; /* Guess */
607 };
608 pclkmsp3: pclkmsp3@48M {
609 #clock-cells = <0>;
610 compatible = "st,nomadik-src-clock";
611 clock-id = <59>;
612 clocks = <&pclk>;
613 };
614 mspclk3: mspclk3@48M {
615 #clock-cells = <0>;
616 compatible = "st,nomadik-src-clock";
617 clock-id = <60>;
618 clocks = <&clk48>;
619 };
620 mshcclk: mshcclk@48M {
621 #clock-cells = <0>;
622 compatible = "st,nomadik-src-clock";
623 clock-id = <61>;
624 clocks = <&clk48>; /* Guess */
625 };
626 usbmclk: usbmclk@48M {
627 #clock-cells = <0>;
628 compatible = "st,nomadik-src-clock";
629 clock-id = <62>;
630 /* Stated as "48 MHz not ULPI clock" */
631 clocks = <&clk48>;
632 };
633 rngcclk: rngcclk@48M {
634 #clock-cells = <0>;
635 compatible = "st,nomadik-src-clock";
636 clock-id = <63>;
637 clocks = <&clk48>; /* Guess */
638 };
639 };
641 /* A NAND flash of 128 MiB */
642 fsmc: flash@40000000 {
643 compatible = "stericsson,fsmc-nand";
644 #address-cells = <1>;
645 #size-cells = <1>;
646 reg = <0x10100000 0x1000>, /* FSMC Register*/
647 <0x40000000 0x2000>, /* NAND Base DATA */
648 <0x41000000 0x2000>, /* NAND Base ADDR */
649 <0x40800000 0x2000>; /* NAND Base CMD */
650 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
651 clocks = <&hclksmc>;
652 status = "okay";
653 timings = /bits/ 8 <0 0 0 0x10 0x0a 0>;
655 partition@0 {
656 label = "X-Loader(NAND)";
657 reg = <0x0 0x40000>;
658 };
659 partition@40000 {
660 label = "MemInit(NAND)";
661 reg = <0x40000 0x40000>;
662 };
663 partition@80000 {
664 label = "BootLoader(NAND)";
665 reg = <0x80000 0x200000>;
666 };
667 partition@280000 {
668 label = "Kernel zImage(NAND)";
669 reg = <0x280000 0x300000>;
670 };
671 partition@580000 {
672 label = "Root Filesystem(NAND)";
673 reg = <0x580000 0x1600000>;
674 };
675 partition@1b80000 {
676 label = "User Filesystem(NAND)";
677 reg = <0x1b80000 0x6480000>;
678 };
679 };
681 /* I2C0 connected to the STw4811 power management chip */
682 i2c0 {
683 compatible = "st,nomadik-i2c", "arm,primecell";
684 reg = <0x101f8000 0x1000>;
685 interrupt-parent = <&vica>;
686 interrupts = <20>;
687 clock-frequency = <100000>;
688 #address-cells = <1>;
689 #size-cells = <0>;
690 clocks = <&i2c0clk>, <&pclki2c0>;
691 clock-names = "mclk", "apb_pclk";
692 pinctrl-names = "default";
693 pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>;
695 stw4811@2d {
696 compatible = "st,stw4811";
697 reg = <0x2d>;
698 vmmc_regulator: vmmc {
699 compatible = "st,stw481x-vmmc";
700 regulator-name = "VMMC";
701 regulator-min-microvolt = <1800000>;
702 regulator-max-microvolt = <3300000>;
703 };
704 };
705 };
707 /* I2C1 connected to various sensors */
708 i2c1 {
709 compatible = "st,nomadik-i2c", "arm,primecell";
710 reg = <0x101f7000 0x1000>;
711 interrupt-parent = <&vica>;
712 interrupts = <21>;
713 clock-frequency = <100000>;
714 #address-cells = <1>;
715 #size-cells = <0>;
716 clocks = <&i2c1clk>, <&pclki2c1>;
717 clock-names = "mclk", "apb_pclk";
718 pinctrl-names = "default";
719 pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>;
721 camera@2d {
722 compatible = "st,camera";
723 reg = <0x10>;
724 };
725 stw5095@1a {
726 compatible = "st,stw5095";
727 reg = <0x1a>;
728 };
729 };
731 amba {
732 compatible = "arm,amba-bus";
733 #address-cells = <1>;
734 #size-cells = <1>;
735 ranges;
737 vica: intc@10140000 {
738 compatible = "arm,versatile-vic";
739 interrupt-controller;
740 #interrupt-cells = <1>;
741 reg = <0x10140000 0x20>;
742 };
744 vicb: intc@10140020 {
745 compatible = "arm,versatile-vic";
746 interrupt-controller;
747 #interrupt-cells = <1>;
748 reg = <0x10140020 0x20>;
749 };
751 uart0: uart@101fd000 {
752 compatible = "arm,pl011", "arm,primecell";
753 reg = <0x101fd000 0x1000>;
754 interrupt-parent = <&vica>;
755 interrupts = <12>;
756 clocks = <&uart0clk>, <&pclkuart0>;
757 clock-names = "uartclk", "apb_pclk";
758 status = "disabled";
759 };
761 uart1: uart@101fb000 {
762 compatible = "arm,pl011", "arm,primecell";
763 reg = <0x101fb000 0x1000>;
764 interrupt-parent = <&vica>;
765 interrupts = <17>;
766 clocks = <&uart1clk>, <&pclkuart1>;
767 clock-names = "uartclk", "apb_pclk";
768 pinctrl-names = "default";
769 pinctrl-0 = <&uart1_default_mux>;
770 };
772 uart2: uart@101f2000 {
773 compatible = "arm,pl011", "arm,primecell";
774 reg = <0x101f2000 0x1000>;
775 interrupt-parent = <&vica>;
776 interrupts = <28>;
777 clocks = <&uart2clk>, <&pclkuart2>;
778 clock-names = "uartclk", "apb_pclk";
779 status = "disabled";
780 };
782 rng: rng@101b0000 {
783 compatible = "arm,primecell";
784 reg = <0x101b0000 0x1000>;
785 clocks = <&rngcclk>, <&hclkrng>;
786 clock-names = "rng", "apb_pclk";
787 };
789 rtc: rtc@101e8000 {
790 compatible = "arm,pl031", "arm,primecell";
791 reg = <0x101e8000 0x1000>;
792 clocks = <&pclk>;
793 clock-names = "apb_pclk";
794 interrupt-parent = <&vica>;
795 interrupts = <10>;
796 };
798 mmcsd: sdi@101f6000 {
799 compatible = "arm,pl18x", "arm,primecell";
800 reg = <0x101f6000 0x1000>;
801 clocks = <&sdiclk>, <&pclksdi>;
802 clock-names = "mclk", "apb_pclk";
803 interrupt-parent = <&vica>;
804 interrupts = <22>;
805 max-frequency = <48000000>;
806 bus-width = <4>;
807 cap-mmc-highspeed;
808 cap-sd-highspeed;
809 pinctrl-names = "default";
810 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
811 vmmc-supply = <&vmmc_regulator>;
812 };
813 };
814 };