arch/arm/boot/dts/stih407-clock.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics R&D Limited
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <dt-bindings/clock/stih407-clks.h>
   9 / {
  10         clocks {
  11                 #address-cells = <1>;
  12                 #size-cells = <1>;
  13                 ranges;
  14
  15                 /*
  16                  * Fixed 30MHz oscillator inputs to SoC
  17                  */
  18                 clk_sysin: clk-sysin {
  19                         #clock-cells = <0>;
  20                         compatible = "fixed-clock";
  21                         clock-frequency = <30000000>;
  22                 };
  23
  24                 /*
  25                  * ARM Peripheral clock for timers
  26                  */
  27                 arm_periph_clk: clk-m-a9-periphs {
  28                         #clock-cells = <0>;
  29                         compatible = "fixed-factor-clock";
  30
  31                         clocks = <&clk_m_a9>;
  32                         clock-div = <2>;
  33                         clock-mult = <1>;
  34                 };
  35
  36                 /*
  37                  * A9 PLL.
  38                  */
  39                 clockgen-a9@92b0000 {
  40                         compatible = "st,clkgen-c32";
  41                         reg = <0x92b0000 0xffff>;
  42
  43                         clockgen_a9_pll: clockgen-a9-pll {
  44                                 #clock-cells = <1>;
  45                                 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
  46
  47                                 clocks = <&clk_sysin>;
  48
  49                                 clock-output-names = "clockgen-a9-pll-odf";
  50                         };
  51                 };
  52
  53                 /*
  54                  * ARM CPU related clocks.
  55                  */
  56                 clk_m_a9: clk-m-a9@92b0000 {
  57                         #clock-cells = <0>;
  58                         compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
  59                         reg = <0x92b0000 0x10000>;
  60
  61                         clocks = <&clockgen_a9_pll 0>,
  62                                  <&clockgen_a9_pll 0>,
  63                                  <&clk_s_c0_flexgen 13>,
  64                                  <&clk_m_a9_ext2f_div2>;
  65                 };
  66
  67                 /*
  68                  * ARM Peripheral clock for timers
  69                  */
  70                 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
  71                         #clock-cells = <0>;
  72                         compatible = "fixed-factor-clock";
  73
  74                         clocks = <&clk_s_c0_flexgen 13>;
  75
  76                         clock-output-names = "clk-m-a9-ext2f-div2";
  77
  78                         clock-div = <2>;
  79                         clock-mult = <1>;
  80                 };
  81
  82                 /*
  83                  * Bootloader initialized system infrastructure clock for
  84                  * serial devices.
  85                  */
  86                 clk_ext2f_a9: clockgen-c0@13 {
  87                         #clock-cells = <0>;
  88                         compatible = "fixed-clock";
  89                         clock-frequency = <200000000>;
  90                         clock-output-names = "clk-s-icn-reg-0";
  91                 };
  92
  93                 clockgen-a@090ff000 {
  94                         compatible = "st,clkgen-c32";
  95                         reg = <0x90ff000 0x1000>;
  96
  97                         clk_s_a0_pll: clk-s-a0-pll {
  98                                 #clock-cells = <1>;
  99                                 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
 100
 101                                 clocks = <&clk_sysin>;
 102
 103                                 clock-output-names = "clk-s-a0-pll-ofd-0";
 104                         };
 105
 106                         clk_s_a0_flexgen: clk-s-a0-flexgen {
 107                                 compatible = "st,flexgen";
 108
 109                                 #clock-cells = <1>;
 110
 111                                 clocks = <&clk_s_a0_pll 0>,
 112                                          <&clk_sysin>;
 113
 114                                 clock-output-names = "clk-ic-lmi0";
 115                         };
 116                 };
 117
 118                 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
 119                         #clock-cells = <1>;
 120                         compatible = "st,stih407-quadfs660-C", "st,quadfs";
 121                         reg = <0x9103000 0x1000>;
 122
 123                         clocks = <&clk_sysin>;
 124
 125                         clock-output-names = "clk-s-c0-fs0-ch0",
 126                                              "clk-s-c0-fs0-ch1",
 127                                              "clk-s-c0-fs0-ch2",
 128                                              "clk-s-c0-fs0-ch3";
 129                 };
 130
 131                 clk_s_c0: clockgen-c@09103000 {
 132                         compatible = "st,clkgen-c32";
 133                         reg = <0x9103000 0x1000>;
 134
 135                         clk_s_c0_pll0: clk-s-c0-pll0 {
 136                                 #clock-cells = <1>;
 137                                 compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
 138
 139                                 clocks = <&clk_sysin>;
 140
 141                                 clock-output-names = "clk-s-c0-pll0-odf-0";
 142                         };
 143
 144                         clk_s_c0_pll1: clk-s-c0-pll1 {
 145                                 #clock-cells = <1>;
 146                                 compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
 147
 148                                 clocks = <&clk_sysin>;
 149
 150                                 clock-output-names = "clk-s-c0-pll1-odf-0";
 151                         };
 152
 153                         clk_s_c0_flexgen: clk-s-c0-flexgen {
 154                                 #clock-cells = <1>;
 155                                 compatible = "st,flexgen";
 156
 157                                 clocks = <&clk_s_c0_pll0 0>,
 158                                          <&clk_s_c0_pll1 0>,
 159                                          <&clk_s_c0_quadfs 0>,
 160                                          <&clk_s_c0_quadfs 1>,
 161                                          <&clk_s_c0_quadfs 2>,
 162                                          <&clk_s_c0_quadfs 3>,
 163                                          <&clk_sysin>;
 164
 165                                 clock-output-names = "clk-icn-gpu",
 166                                                      "clk-fdma",
 167                                                      "clk-nand",
 168                                                      "clk-hva",
 169                                                      "clk-proc-stfe",
 170                                                      "clk-proc-tp",
 171                                                      "clk-rx-icn-dmu",
 172                                                      "clk-rx-icn-hva",
 173                                                      "clk-icn-cpu",
 174                                                      "clk-tx-icn-dmu",
 175                                                      "clk-mmc-0",
 176                                                      "clk-mmc-1",
 177                                                      "clk-jpegdec",
 178                                                      "clk-ext2fa9",
 179                                                      "clk-ic-bdisp-0",
 180                                                      "clk-ic-bdisp-1",
 181                                                      "clk-pp-dmu",
 182                                                      "clk-vid-dmu",
 183                                                      "clk-dss-lpc",
 184                                                      "clk-st231-aud-0",
 185                                                      "clk-st231-gp-1",
 186                                                      "clk-st231-dmu",
 187                                                      "clk-icn-lmi",
 188                                                      "clk-tx-icn-disp-1",
 189                                                      "clk-icn-sbc",
 190                                                      "clk-stfe-frc2",
 191                                                      "clk-eth-phy",
 192                                                      "clk-eth-ref-phyclk",
 193                                                      "clk-flash-promip",
 194                                                      "clk-main-disp",
 195                                                      "clk-aux-disp",
 196                                                      "clk-compo-dvp";
 197                         };
 198                 };
 199
 200                 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
 201                         #clock-cells = <1>;
 202                         compatible = "st,stih407-quadfs660-D", "st,quadfs";
 203                         reg = <0x9104000 0x1000>;
 204
 205                         clocks = <&clk_sysin>;
 206
 207                         clock-output-names = "clk-s-d0-fs0-ch0",
 208                                              "clk-s-d0-fs0-ch1",
 209                                              "clk-s-d0-fs0-ch2",
 210                                              "clk-s-d0-fs0-ch3";
 211                 };
 212
 213                 clockgen-d0@09104000 {
 214                         compatible = "st,clkgen-c32";
 215                         reg = <0x9104000 0x1000>;
 216
 217                         clk_s_d0_flexgen: clk-s-d0-flexgen {
 218                                 #clock-cells = <1>;
 219                                 compatible = "st,flexgen";
 220
 221                                 clocks = <&clk_s_d0_quadfs 0>,
 222                                          <&clk_s_d0_quadfs 1>,
 223                                          <&clk_s_d0_quadfs 2>,
 224                                          <&clk_s_d0_quadfs 3>,
 225                                          <&clk_sysin>;
 226
 227                                 clock-output-names = "clk-pcm-0",
 228                                                      "clk-pcm-1",
 229                                                      "clk-pcm-2",
 230                                                      "clk-spdiff";
 231                         };
 232                 };
 233
 234                 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
 235                         #clock-cells = <1>;
 236                         compatible = "st,stih407-quadfs660-D", "st,quadfs";
 237                         reg = <0x9106000 0x1000>;
 238
 239                         clocks = <&clk_sysin>;
 240
 241                         clock-output-names = "clk-s-d2-fs0-ch0",
 242                                              "clk-s-d2-fs0-ch1",
 243                                              "clk-s-d2-fs0-ch2",
 244                                              "clk-s-d2-fs0-ch3";
 245                 };
 246
 247                 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
 248                         #clock-cells = <0>;
 249                         compatible = "fixed-clock";
 250                         clock-frequency = <0>;
 251                 };
 252
 253                 clockgen-d2@x9106000 {
 254                         compatible = "st,clkgen-c32";
 255                         reg = <0x9106000 0x1000>;
 256
 257                         clk_s_d2_flexgen: clk-s-d2-flexgen {
 258                                 #clock-cells = <1>;
 259                                 compatible = "st,flexgen";
 260
 261                                 clocks = <&clk_s_d2_quadfs 0>,
 262                                          <&clk_s_d2_quadfs 1>,
 263                                          <&clk_s_d2_quadfs 2>,
 264                                          <&clk_s_d2_quadfs 3>,
 265                                          <&clk_sysin>,
 266                                          <&clk_sysin>,
 267                                          <&clk_tmdsout_hdmi>;
 268
 269                                 clock-output-names = "clk-pix-main-disp",
 270                                                      "clk-pix-pip",
 271                                                      "clk-pix-gdp1",
 272                                                      "clk-pix-gdp2",
 273                                                      "clk-pix-gdp3",
 274                                                      "clk-pix-gdp4",
 275                                                      "clk-pix-aux-disp",
 276                                                      "clk-denc",
 277                                                      "clk-pix-hddac",
 278                                                      "clk-hddac",
 279                                                      "clk-sddac",
 280                                                      "clk-pix-dvo",
 281                                                      "clk-dvo",
 282                                                      "clk-pix-hdmi",
 283                                                      "clk-tmds-hdmi",
 284                                                      "clk-ref-hdmiphy";
 285                                                      };
 286                 };
 287
 288                 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
 289                         #clock-cells = <1>;
 290                         compatible = "st,stih407-quadfs660-D", "st,quadfs";
 291                         reg = <0x9107000 0x1000>;
 292
 293                         clocks = <&clk_sysin>;
 294
 295                         clock-output-names = "clk-s-d3-fs0-ch0",
 296                                              "clk-s-d3-fs0-ch1",
 297                                              "clk-s-d3-fs0-ch2",
 298                                              "clk-s-d3-fs0-ch3";
 299                 };
 300
 301                 clockgen-d3@9107000 {
 302                         compatible = "st,clkgen-c32";
 303                         reg = <0x9107000 0x1000>;
 304
 305                         clk_s_d3_flexgen: clk-s-d3-flexgen {
 306                                 #clock-cells = <1>;
 307                                 compatible = "st,flexgen";
 308
 309                                 clocks = <&clk_s_d3_quadfs 0>,
 310                                          <&clk_s_d3_quadfs 1>,
 311                                          <&clk_s_d3_quadfs 2>,
 312                                          <&clk_s_d3_quadfs 3>,
 313                                          <&clk_sysin>;
 314
 315                                 clock-output-names = "clk-stfe-frc1",
 316                                                      "clk-tsout-0",
 317                                                      "clk-tsout-1",
 318                                                      "clk-mchi",
 319                                                      "clk-vsens-compo",
 320                                                      "clk-frc1-remote",
 321                                                      "clk-lpc-0",
 322                                                      "clk-lpc-1";
 323                         };
 324                 };
 325         };
 326 };