| blob | 5b4fb838cddb61a71c747cfc05789a80f2f48c27 |
1 /*
2 * Copyright (C) 2013 STMicroelectronics R&D Limited
3 * <stlinux-devel@stlinux.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
10 #include <dt-bindings/clock/stih416-clks.h>
12 / {
13 clocks {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
18 /*
19 * Fixed 30MHz oscillator inputs to SoC
20 */
21 clk_sysin: clk-sysin {
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
24 clock-frequency = <30000000>;
25 };
27 /*
28 * ClockGenAs on SASG2
29 */
30 clockgen-a@fee62000 {
31 reg = <0xfee62000 0xb48>;
33 clk_s_a0_pll: clk-s-a0-pll {
34 #clock-cells = <1>;
35 compatible = "st,clkgena-plls-c65";
37 clocks = <&clk_sysin>;
39 clock-output-names = "clk-s-a0-pll0-hs",
40 "clk-s-a0-pll0-ls",
41 "clk-s-a0-pll1";
42 };
44 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
45 #clock-cells = <0>;
46 compatible = "st,clkgena-prediv-c65",
47 "st,clkgena-prediv";
49 clocks = <&clk_sysin>;
51 clock-output-names = "clk-s-a0-osc-prediv";
52 };
54 clk_s_a0_hs: clk-s-a0-hs {
55 #clock-cells = <1>;
56 compatible = "st,clkgena-divmux-c65-hs",
57 "st,clkgena-divmux";
59 clocks = <&clk_s_a0_osc_prediv>,
60 <&clk_s_a0_pll 0>, /* PLL0 HS */
61 <&clk_s_a0_pll 2>; /* PLL1 */
63 clock-output-names = "clk-s-fdma-0",
64 "clk-s-fdma-1",
65 ""; /* clk-s-jit-sense */
66 /* Fourth output unused */
67 };
69 clk_s_a0_ls: clk-s-a0-ls {
70 #clock-cells = <1>;
71 compatible = "st,clkgena-divmux-c65-ls",
72 "st,clkgena-divmux";
74 clocks = <&clk_s_a0_osc_prediv>,
75 <&clk_s_a0_pll 1>, /* PLL0 LS */
76 <&clk_s_a0_pll 2>; /* PLL1 */
78 clock-output-names = "clk-s-icn-reg-0",
79 "clk-s-icn-if-0",
80 "clk-s-icn-reg-lp-0",
81 "clk-s-emiss",
82 "clk-s-eth1-phy",
83 "clk-s-mii-ref-out";
84 /* Remaining outputs unused */
85 };
86 };
88 clockgen-a@fee81000 {
89 reg = <0xfee81000 0xb48>;
91 clk_s_a1_pll: clk-s-a1-pll {
92 #clock-cells = <1>;
93 compatible = "st,clkgena-plls-c65";
95 clocks = <&clk_sysin>;
97 clock-output-names = "clk-s-a1-pll0-hs",
98 "clk-s-a1-pll0-ls",
99 "clk-s-a1-pll1";
100 };
102 clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
103 #clock-cells = <0>;
104 compatible = "st,clkgena-prediv-c65",
105 "st,clkgena-prediv";
107 clocks = <&clk_sysin>;
109 clock-output-names = "clk-s-a1-osc-prediv";
110 };
112 clk_s_a1_hs: clk-s-a1-hs {
113 #clock-cells = <1>;
114 compatible = "st,clkgena-divmux-c65-hs",
115 "st,clkgena-divmux";
117 clocks = <&clk_s_a1_osc_prediv>,
118 <&clk_s_a1_pll 0>, /* PLL0 HS */
119 <&clk_s_a1_pll 2>; /* PLL1 */
121 clock-output-names = "", /* Reserved */
122 "", /* Reserved */
123 "clk-s-stac-phy",
124 "clk-s-vtac-tx-phy";
125 };
127 clk_s_a1_ls: clk-s-a1-ls {
128 #clock-cells = <1>;
129 compatible = "st,clkgena-divmux-c65-ls",
130 "st,clkgena-divmux";
132 clocks = <&clk_s_a1_osc_prediv>,
133 <&clk_s_a1_pll 1>, /* PLL0 LS */
134 <&clk_s_a1_pll 2>; /* PLL1 */
136 clock-output-names = "clk-s-icn-if-2",
137 "clk-s-card-mmc-0",
138 "clk-s-icn-if-1",
139 "clk-s-gmac0-phy",
140 "clk-s-nand-ctrl",
141 "", /* Reserved */
142 "clk-s-mii0-ref-out",
143 "clk-s-stac-sys",
144 "clk-s-card-mmc-1";
145 /* Remaining outputs unused */
146 };
147 };
149 /*
150 * ClockGenAs on MPE42
151 */
152 clockgen-a@fde12000 {
153 reg = <0xfde12000 0xb50>;
155 clk_m_a0_pll0: clk-m-a0-pll0 {
156 #clock-cells = <1>;
157 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
159 clocks = <&clk_sysin>;
161 clock-output-names = "clk-m-a0-pll0-phi0",
162 "clk-m-a0-pll0-phi1",
163 "clk-m-a0-pll0-phi2",
164 "clk-m-a0-pll0-phi3";
165 };
167 clk_m_a0_pll1: clk-m-a0-pll1 {
168 #clock-cells = <1>;
169 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
171 clocks = <&clk_sysin>;
173 clock-output-names = "clk-m-a0-pll1-phi0",
174 "clk-m-a0-pll1-phi1",
175 "clk-m-a0-pll1-phi2",
176 "clk-m-a0-pll1-phi3";
177 };
179 clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
180 #clock-cells = <0>;
181 compatible = "st,clkgena-prediv-c32",
182 "st,clkgena-prediv";
184 clocks = <&clk_sysin>;
186 clock-output-names = "clk-m-a0-osc-prediv";
187 };
189 clk_m_a0_div0: clk-m-a0-div0 {
190 #clock-cells = <1>;
191 compatible = "st,clkgena-divmux-c32-odf0",
192 "st,clkgena-divmux";
194 clocks = <&clk_m_a0_osc_prediv>,
195 <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
196 <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
198 clock-output-names = "", /* Unused */
199 "", /* Unused */
200 "clk-m-fdma-12",
201 "", /* Unused */
202 "clk-m-pp-dmu-0",
203 "clk-m-pp-dmu-1",
204 "clk-m-icm-lmi",
205 "clk-m-vid-dmu-0";
206 };
208 clk_m_a0_div1: clk-m-a0-div1 {
209 #clock-cells = <1>;
210 compatible = "st,clkgena-divmux-c32-odf1",
211 "st,clkgena-divmux";
213 clocks = <&clk_m_a0_osc_prediv>,
214 <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
215 <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
217 clock-output-names = "clk-m-vid-dmu-1",
218 "", /* Unused */
219 "clk-m-a9-ext2f",
220 "clk-m-st40rt",
221 "clk-m-st231-dmu-0",
222 "clk-m-st231-dmu-1",
223 "clk-m-st231-aud",
224 "clk-m-st231-gp-0";
225 };
227 clk_m_a0_div2: clk-m-a0-div2 {
228 #clock-cells = <1>;
229 compatible = "st,clkgena-divmux-c32-odf2",
230 "st,clkgena-divmux";
232 clocks = <&clk_m_a0_osc_prediv>,
233 <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
234 <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
236 clock-output-names = "clk-m-st231-gp-1",
237 "clk-m-icn-cpu",
238 "clk-m-icn-stac",
239 "clk-m-tx-icn-dmu-0",
240 "clk-m-tx-icn-dmu-1",
241 "clk-m-tx-icn-ts",
242 "clk-m-icn-vdp-0",
243 "clk-m-icn-vdp-1";
244 };
246 clk_m_a0_div3: clk-m-a0-div3 {
247 #clock-cells = <1>;
248 compatible = "st,clkgena-divmux-c32-odf3",
249 "st,clkgena-divmux";
251 clocks = <&clk_m_a0_osc_prediv>,
252 <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
253 <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
255 clock-output-names = "", /* Unused */
256 "", /* Unused */
257 "", /* Unused */
258 "", /* Unused */
259 "clk-m-icn-vp8",
260 "", /* Unused */
261 "clk-m-icn-reg-11",
262 "clk-m-a9-trace";
263 };
264 };
266 clockgen-a@fd6db000 {
267 reg = <0xfd6db000 0xb50>;
269 clk_m_a1_pll0: clk-m-a1-pll0 {
270 #clock-cells = <1>;
271 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
273 clocks = <&clk_sysin>;
275 clock-output-names = "clk-m-a1-pll0-phi0",
276 "clk-m-a1-pll0-phi1",
277 "clk-m-a1-pll0-phi2",
278 "clk-m-a1-pll0-phi3";
279 };
281 clk_m_a1_pll1: clk-m-a1-pll1 {
282 #clock-cells = <1>;
283 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
285 clocks = <&clk_sysin>;
287 clock-output-names = "clk-m-a1-pll1-phi0",
288 "clk-m-a1-pll1-phi1",
289 "clk-m-a1-pll1-phi2",
290 "clk-m-a1-pll1-phi3";
291 };
293 clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
294 #clock-cells = <0>;
295 compatible = "st,clkgena-prediv-c32",
296 "st,clkgena-prediv";
298 clocks = <&clk_sysin>;
300 clock-output-names = "clk-m-a1-osc-prediv";
301 };
303 clk_m_a1_div0: clk-m-a1-div0 {
304 #clock-cells = <1>;
305 compatible = "st,clkgena-divmux-c32-odf0",
306 "st,clkgena-divmux";
308 clocks = <&clk_m_a1_osc_prediv>,
309 <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
310 <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
312 clock-output-names = "", /* Unused */
313 "clk-m-fdma-10",
314 "clk-m-fdma-11",
315 "clk-m-hva-alt",
316 "clk-m-proc-sc",
317 "clk-m-tp",
318 "clk-m-rx-icn-dmu-0",
319 "clk-m-rx-icn-dmu-1";
320 };
322 clk_m_a1_div1: clk-m-a1-div1 {
323 #clock-cells = <1>;
324 compatible = "st,clkgena-divmux-c32-odf1",
325 "st,clkgena-divmux";
327 clocks = <&clk_m_a1_osc_prediv>,
328 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
329 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
331 clock-output-names = "clk-m-rx-icn-ts",
332 "clk-m-rx-icn-vdp-0",
333 "", /* Unused */
334 "clk-m-prv-t1-bus",
335 "clk-m-icn-reg-12",
336 "clk-m-icn-reg-10",
337 "", /* Unused */
338 "clk-m-icn-st231";
339 };
341 clk_m_a1_div2: clk-m-a1-div2 {
342 #clock-cells = <1>;
343 compatible = "st,clkgena-divmux-c32-odf2",
344 "st,clkgena-divmux";
346 clocks = <&clk_m_a1_osc_prediv>,
347 <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
348 <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
350 clock-output-names = "clk-m-fvdp-proc-alt",
351 "clk-m-icn-reg-13",
352 "clk-m-tx-icn-gpu",
353 "clk-m-rx-icn-gpu",
354 "", /* Unused */
355 "", /* Unused */
356 "", /* clk-m-apb-pm-12 */
357 ""; /* Unused */
358 };
360 clk_m_a1_div3: clk-m-a1-div3 {
361 #clock-cells = <1>;
362 compatible = "st,clkgena-divmux-c32-odf3",
363 "st,clkgena-divmux";
365 clocks = <&clk_m_a1_osc_prediv>,
366 <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
367 <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
369 clock-output-names = "", /* Unused */
370 "", /* Unused */
371 "", /* Unused */
372 "", /* Unused */
373 "", /* Unused */
374 "", /* Unused */
375 "", /* Unused */
376 ""; /* clk-m-gpu-alt */
377 };
378 };
380 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
381 #clock-cells = <0>;
382 compatible = "fixed-factor-clock";
383 clocks = <&clk_m_a0_div1 2>;
384 clock-div = <2>;
385 clock-mult = <1>;
386 };
388 clockgen-a@fd345000 {
389 reg = <0xfd345000 0xb50>;
391 clk_m_a2_pll0: clk-m-a2-pll0 {
392 #clock-cells = <1>;
393 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
395 clocks = <&clk_sysin>;
397 clock-output-names = "clk-m-a2-pll0-phi0",
398 "clk-m-a2-pll0-phi1",
399 "clk-m-a2-pll0-phi2",
400 "clk-m-a2-pll0-phi3";
401 };
403 clk_m_a2_pll1: clk-m-a2-pll1 {
404 #clock-cells = <1>;
405 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
407 clocks = <&clk_sysin>;
409 clock-output-names = "clk-m-a2-pll1-phi0",
410 "clk-m-a2-pll1-phi1",
411 "clk-m-a2-pll1-phi2",
412 "clk-m-a2-pll1-phi3";
413 };
415 clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
416 #clock-cells = <0>;
417 compatible = "st,clkgena-prediv-c32",
418 "st,clkgena-prediv";
420 clocks = <&clk_sysin>;
422 clock-output-names = "clk-m-a2-osc-prediv";
423 };
425 clk_m_a2_div0: clk-m-a2-div0 {
426 #clock-cells = <1>;
427 compatible = "st,clkgena-divmux-c32-odf0",
428 "st,clkgena-divmux";
430 clocks = <&clk_m_a2_osc_prediv>,
431 <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
432 <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
434 clock-output-names = "clk-m-vtac-main-phy",
435 "clk-m-vtac-aux-phy",
436 "clk-m-stac-phy",
437 "clk-m-stac-sys",
438 "", /* clk-m-mpestac-pg */
439 "", /* clk-m-mpestac-wc */
440 "", /* clk-m-mpevtacaux-pg*/
441 ""; /* clk-m-mpevtacmain-pg*/
442 };
444 clk_m_a2_div1: clk-m-a2-div1 {
445 #clock-cells = <1>;
446 compatible = "st,clkgena-divmux-c32-odf1",
447 "st,clkgena-divmux";
449 clocks = <&clk_m_a2_osc_prediv>,
450 <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
451 <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
453 clock-output-names = "", /* clk-m-mpevtacrx0-wc */
454 "", /* clk-m-mpevtacrx1-wc */
455 "clk-m-compo-main",
456 "clk-m-compo-aux",
457 "clk-m-bdisp-0",
458 "clk-m-bdisp-1",
459 "clk-m-icn-bdisp",
460 "clk-m-icn-compo";
461 };
463 clk_m_a2_div2: clk-m-a2-div2 {
464 #clock-cells = <1>;
465 compatible = "st,clkgena-divmux-c32-odf2",
466 "st,clkgena-divmux";
468 clocks = <&clk_m_a2_osc_prediv>,
469 <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
470 <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
472 clock-output-names = "clk-m-icn-vdp-2",
473 "", /* Unused */
474 "clk-m-icn-reg-14",
475 "clk-m-mdtp",
476 "clk-m-jpegdec",
477 "", /* Unused */
478 "clk-m-dcephy-impctrl",
479 ""; /* Unused */
480 };
482 clk_m_a2_div3: clk-m-a2-div3 {
483 #clock-cells = <1>;
484 compatible = "st,clkgena-divmux-c32-odf3",
485 "st,clkgena-divmux";
487 clocks = <&clk_m_a2_osc_prediv>,
488 <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
489 <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
491 clock-output-names = "", /* Unused */
492 ""; /* clk-m-apb-pm-11 */
493 /* Remaining outputs unused */
494 };
495 };
497 /*
498 * A9 PLL
499 */
500 clockgen-a9@fdde08b0 {
501 reg = <0xfdde08b0 0x70>;
503 clockgen_a9_pll: clockgen-a9-pll {
504 #clock-cells = <1>;
505 compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32";
507 clocks = <&clk_sysin>;
508 clock-output-names = "clockgen-a9-pll-odf";
509 };
510 };
512 /*
513 * ARM CPU related clocks
514 */
515 clk_m_a9: clk-m-a9@fdde08ac {
516 #clock-cells = <0>;
517 compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux";
518 reg = <0xfdde08ac 0x4>;
519 clocks = <&clockgen_a9_pll 0>,
520 <&clockgen_a9_pll 0>,
521 <&clk_m_a0_div1 2>,
522 <&clk_m_a9_ext2f_div2>;
523 };
525 /*
526 * ARM Peripheral clock for timers
527 */
528 arm_periph_clk: clk-m-a9-periphs {
529 #clock-cells = <0>;
530 compatible = "fixed-factor-clock";
531 clocks = <&clk_m_a9>;
532 clock-div = <2>;
533 clock-mult = <1>;
534 };
536 /*
537 * Frequency synthesizers on the SASG2
538 */
539 clockgen_b0: clockgen-b0@fee108b4 {
540 #clock-cells = <1>;
541 compatible = "st,stih416-quadfs216", "st,quadfs";
542 reg = <0xfee108b4 0x44>;
544 clocks = <&clk_sysin>;
545 clock-output-names = "clk-s-usb48",
546 "clk-s-dss",
547 "clk-s-stfe-frc-2",
548 "clk-s-thsens-scard";
549 };
551 clockgen_b1: clockgen-b1@fe8308c4 {
552 #clock-cells = <1>;
553 compatible = "st,stih416-quadfs216", "st,quadfs";
554 reg = <0xfe8308c4 0x44>;
556 clocks = <&clk_sysin>;
557 clock-output-names = "clk-s-pcm-0",
558 "clk-s-pcm-1",
559 "clk-s-pcm-2",
560 "clk-s-pcm-3";
561 };
563 clockgen_c: clockgen-c@fe8307d0 {
564 #clock-cells = <1>;
565 compatible = "st,stih416-quadfs432", "st,quadfs";
566 reg = <0xfe8307d0 0x44>;
568 clocks = <&clk_sysin>;
569 clock-output-names = "clk-s-c-fs0-ch0",
570 "clk-s-c-vcc-sd",
571 "clk-s-c-fs0-ch2";
572 };
574 clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 {
575 #clock-cells = <0>;
576 compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux";
577 reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */
579 clocks = <&clk_sysin>,
580 <&clockgen_c 0>;
581 };
583 /*
584 * Add a dummy clock for the HDMI PHY for the VCC input mux
585 */
586 clk_s_tmds_fromphy: clk-s-tmds-fromphy {
587 #clock-cells = <0>;
588 compatible = "fixed-clock";
589 clock-frequency = <0>;
590 };
592 clockgen_c_vcc: clockgen-c-vcc@fe8308ac {
593 #clock-cells = <1>;
594 compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
595 reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */
597 clocks = <&clk_s_vcc_hd>,
598 <&clockgen_c 1>,
599 <&clk_s_tmds_fromphy>,
600 <&clockgen_c 2>;
602 clock-output-names = "clk-s-pix-hdmi",
603 "clk-s-pix-dvo",
604 "clk-s-out-dvo",
605 "clk-s-pix-hd",
606 "clk-s-hddac",
607 "clk-s-denc",
608 "clk-s-sddac",
609 "clk-s-pix-main",
610 "clk-s-pix-aux",
611 "clk-s-stfe-frc-0",
612 "clk-s-ref-mcru",
613 "clk-s-slave-mcru",
614 "clk-s-tmds-hdmi",
615 "clk-s-hdmi-reject-pll",
616 "clk-s-thsens";
617 };
619 clockgen_d: clockgen-d@fee107e0 {
620 #clock-cells = <1>;
621 compatible = "st,stih416-quadfs216", "st,quadfs";
622 reg = <0xfee107e0 0x44>;
624 clocks = <&clk_sysin>;
625 clock-output-names = "clk-s-ccsc",
626 "clk-s-stfe-frc-1",
627 "clk-s-tsout-1",
628 "clk-s-mchi";
629 };
631 /*
632 * Frequency synthesizers on the MPE42
633 */
634 clockgen_e: clockgen-e@fd3208bc {
635 #clock-cells = <1>;
636 compatible = "st,stih416-quadfs660-E", "st,quadfs";
637 reg = <0xfd3208bc 0xb0>;
639 clocks = <&clk_sysin>;
640 clock-output-names = "clk-m-pix-mdtp-0",
641 "clk-m-pix-mdtp-1",
642 "clk-m-pix-mdtp-2",
643 "clk-m-mpelpc";
644 };
646 clockgen_f: clockgen-f@fd320878 {
647 #clock-cells = <1>;
648 compatible = "st,stih416-quadfs660-F", "st,quadfs";
649 reg = <0xfd320878 0xf0>;
651 clocks = <&clk_sysin>;
652 clock-output-names = "clk-m-main-vidfs",
653 "clk-m-hva-fs",
654 "clk-m-fvdp-vcpu",
655 "clk-m-fvdp-proc-fs";
656 };
658 clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 {
659 #clock-cells = <0>;
660 compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux";
661 reg = <0xfd320910 0x4>; /* SYSCFG8580 */
663 clocks = <&clk_m_a1_div2 0>,
664 <&clockgen_f 3>;
665 };
667 clk_m_hva: clk-m-hva@fd690868 {
668 #clock-cells = <0>;
669 compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
670 reg = <0xfd690868 0x4>; /* SYSCFG9538 */
672 clocks = <&clockgen_f 1>,
673 <&clk_m_a1_div0 3>;
674 };
676 clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c {
677 #clock-cells = <0>;
678 compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux";
679 reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
681 clocks = <&clockgen_c_vcc 7>,
682 <&clockgen_f 0>;
683 };
685 clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c {
686 #clock-cells = <0>;
687 compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux";
688 reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
690 clocks = <&clockgen_c_vcc 8>,
691 <&clockgen_f 1>;
692 };
694 /*
695 * Add a dummy clock for the HDMIRx external signal clock
696 */
697 clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas {
698 #clock-cells = <0>;
699 compatible = "fixed-clock";
700 clock-frequency = <0>;
701 };
703 clockgen_f_vcc: clockgen-f-vcc@fd32086c {
704 #clock-cells = <1>;
705 compatible = "st,stih416-clkgenf", "st,clkgen-vcc";
706 reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */
708 clocks = <&clk_m_f_vcc_hd>,
709 <&clk_m_f_vcc_sd>,
710 <&clockgen_f 0>,
711 <&clk_m_pix_hdmirx_sas>;
713 clock-output-names = "clk-m-pix-main-pipe",
714 "clk-m-pix-aux-pipe",
715 "clk-m-pix-main-cru",
716 "clk-m-pix-aux-cru",
717 "clk-m-xfer-be-compo",
718 "clk-m-xfer-pip-compo",
719 "clk-m-xfer-aux-compo",
720 "clk-m-vsens",
721 "clk-m-pix-hdmirx-0",
722 "clk-m-pix-hdmirx-1";
723 };
725 /*
726 * DDR PLL
727 */
728 clockgen-ddr@0xfdde07d8 {
729 reg = <0xfdde07d8 0x110>;
731 clockgen_ddr_pll: clockgen-ddr-pll {
732 #clock-cells = <1>;
733 compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32";
735 clocks = <&clk_sysin>;
736 clock-output-names = "clockgen-ddr0",
737 "clockgen-ddr1";
738 };
739 };
741 /*
742 * GPU PLL
743 */
744 clockgen-gpu@fd68ff00 {
745 reg = <0xfd68ff00 0x910>;
747 clockgen_gpu_pll: clockgen-gpu-pll {
748 #clock-cells = <1>;
749 compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32";
751 clocks = <&clk_sysin>;
752 clock-output-names = "clockgen-gpu-pll";
753 };
754 };
755 };
756 };