| blob | 9e3170ccd18c628f54d5896558c1646283c535da |
1 /*
2 * Copyright (C) 2012 STMicroelectronics Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9 #include "stih41x.dtsi"
10 #include "stih416-clock.dtsi"
11 #include "stih416-pinctrl.dtsi"
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/reset/stih416-resets.h>
16 #include <dt-bindings/interrupt-controller/irq-st.h>
17 / {
18 L2: cache-controller {
19 compatible = "arm,pl310-cache";
20 reg = <0xfffe2000 0x1000>;
21 arm,data-latency = <3 3 3>;
22 arm,tag-latency = <2 2 2>;
23 cache-unified;
24 cache-level = <2>;
25 };
27 arm-pmu {
28 compatible = "arm,cortex-a9-pmu";
29 interrupt-parent = <&intc>;
30 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
31 };
33 soc {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-parent = <&intc>;
37 ranges;
38 compatible = "simple-bus";
40 restart {
41 compatible = "st,stih416-restart";
42 st,syscfg = <&syscfg_sbc>;
43 status = "okay";
44 };
46 powerdown: powerdown-controller {
47 #reset-cells = <1>;
48 compatible = "st,stih416-powerdown";
49 };
51 softreset: softreset-controller {
52 #reset-cells = <1>;
53 compatible = "st,stih416-softreset";
54 };
56 syscfg_sbc:sbc-syscfg@fe600000{
57 compatible = "st,stih416-sbc-syscfg", "syscon";
58 reg = <0xfe600000 0x1000>;
59 };
61 syscfg_front:front-syscfg@fee10000{
62 compatible = "st,stih416-front-syscfg", "syscon";
63 reg = <0xfee10000 0x1000>;
64 };
66 syscfg_rear:rear-syscfg@fe830000{
67 compatible = "st,stih416-rear-syscfg", "syscon";
68 reg = <0xfe830000 0x1000>;
69 };
71 /* MPE */
72 syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
73 compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
74 reg = <0xfddf0000 0x1000>;
75 };
77 syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
78 compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
79 reg = <0xfd6a0000 0x1000>;
80 };
82 syscfg_cpu:cpu-syscfg@fdde0000{
83 compatible = "st,stih416-cpu-syscfg", "syscon";
84 reg = <0xfdde0000 0x1000>;
85 };
87 syscfg_compo:compo-syscfg@fd320000{
88 compatible = "st,stih416-compo-syscfg", "syscon";
89 reg = <0xfd320000 0x1000>;
90 };
92 syscfg_transport:transport-syscfg@fd690000{
93 compatible = "st,stih416-transport-syscfg", "syscon";
94 reg = <0xfd690000 0x1000>;
95 };
97 syscfg_lpm:lpm-syscfg@fe4b5100{
98 compatible = "st,stih416-lpm-syscfg", "syscon";
99 reg = <0xfe4b5100 0x8>;
100 };
102 irq-syscfg {
103 compatible = "st,stih416-irq-syscfg";
104 st,syscfg = <&syscfg_cpu>;
105 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
106 <ST_IRQ_SYSCFG_PMU_1>;
107 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
108 <ST_IRQ_SYSCFG_DISABLED>;
109 };
111 serial2: serial@fed32000{
112 compatible = "st,asc";
113 status = "disabled";
114 reg = <0xfed32000 0x2c>;
115 interrupts = <0 197 0>;
116 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
119 };
121 /* SBC_UART1 */
122 sbc_serial1: serial@fe531000 {
123 compatible = "st,asc";
124 status = "disabled";
125 reg = <0xfe531000 0x2c>;
126 interrupts = <0 210 0>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_sbc_serial1>;
129 clocks = <&clk_sysin>;
130 };
132 i2c@fed40000 {
133 compatible = "st,comms-ssc4-i2c";
134 reg = <0xfed40000 0x110>;
135 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
137 clock-names = "ssc";
138 clock-frequency = <400000>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c0_default>;
142 status = "disabled";
143 };
145 i2c@fed41000 {
146 compatible = "st,comms-ssc4-i2c";
147 reg = <0xfed41000 0x110>;
148 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
149 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
150 clock-names = "ssc";
151 clock-frequency = <400000>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c1_default>;
155 status = "disabled";
156 };
158 i2c@fe540000 {
159 compatible = "st,comms-ssc4-i2c";
160 reg = <0xfe540000 0x110>;
161 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&clk_sysin>;
163 clock-names = "ssc";
164 clock-frequency = <400000>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
168 status = "disabled";
169 };
171 i2c@fe541000 {
172 compatible = "st,comms-ssc4-i2c";
173 reg = <0xfe541000 0x110>;
174 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&clk_sysin>;
176 clock-names = "ssc";
177 clock-frequency = <400000>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
181 status = "disabled";
182 };
184 ethernet0: dwmac@fe810000 {
185 device_type = "network";
186 compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
187 status = "disabled";
188 reg = <0xfe810000 0x8000>;
189 reg-names = "stmmaceth";
191 interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
192 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
194 snps,pbl = <32>;
195 snps,mixed-burst;
197 st,syscon = <&syscfg_rear 0x8bc>;
198 resets = <&softreset STIH416_ETH0_SOFTRESET>;
199 reset-names = "stmmaceth";
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_mii0>;
202 clock-names = "stmmaceth", "sti-ethclk";
203 clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
204 };
206 ethernet1: dwmac@fef08000 {
207 device_type = "network";
208 compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
209 status = "disabled";
210 reg = <0xfef08000 0x8000>;
211 reg-names = "stmmaceth";
212 interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
213 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
215 snps,pbl = <32>;
216 snps,mixed-burst;
218 st,syscon = <&syscfg_sbc 0x7f0>;
220 resets = <&softreset STIH416_ETH1_SOFTRESET>;
221 reset-names = "stmmaceth";
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_mii1>;
224 clock-names = "stmmaceth", "sti-ethclk";
225 clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
226 };
228 rc: rc@fe518000 {
229 compatible = "st,comms-irb";
230 reg = <0xfe518000 0x234>;
231 interrupts = <0 203 0>;
232 rx-mode = "infrared";
233 clocks = <&clk_sysin>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_ir>;
236 resets = <&softreset STIH416_IRB_SOFTRESET>;
237 };
239 /* FSM */
240 spifsm: spifsm@fe902000 {
241 compatible = "st,spi-fsm";
242 reg = <0xfe902000 0x1000>;
243 pinctrl-0 = <&pinctrl_fsm>;
245 st,syscfg = <&syscfg_rear>;
246 st,boot-device-reg = <0x958>;
247 st,boot-device-spi = <0x1a>;
249 status = "disabled";
250 };
252 keyscan: keyscan@fe4b0000 {
253 compatible = "st,sti-keyscan";
254 status = "disabled";
255 reg = <0xfe4b0000 0x2000>;
256 interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
257 clocks = <&clk_sysin>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_keyscan>;
260 resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
261 <&softreset STIH416_KEYSCAN_SOFTRESET>;
262 };
264 temp0 {
265 compatible = "st,stih416-sas-thermal";
266 clock-names = "thermal";
267 clocks = <&clockgen_c_vcc 14>;
269 status = "okay";
270 };
272 temp1@fdfe8000 {
273 compatible = "st,stih416-mpe-thermal";
274 reg = <0xfdfe8000 0x10>;
275 clocks = <&clockgen_e 3>;
276 clock-names = "thermal";
277 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
279 status = "okay";
280 };
282 mmc0: sdhci@fe81e000 {
283 compatible = "st,sdhci";
284 status = "disabled";
285 reg = <0xfe81e000 0x1000>;
286 interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
287 interrupt-names = "mmcirq";
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_mmc0>;
290 clock-names = "mmc";
291 clocks = <&clk_s_a1_ls 1>;
292 };
294 mmc1: sdhci@fe81f000 {
295 compatible = "st,sdhci";
296 status = "disabled";
297 reg = <0xfe81f000 0x1000>;
298 interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
299 interrupt-names = "mmcirq";
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_mmc1>;
302 clock-names = "mmc";
303 clocks = <&clk_s_a1_ls 8>;
304 };
306 miphy365x_phy: phy@fe382000 {
307 compatible = "st,miphy365x-phy";
308 st,syscfg = <&syscfg_rear 0x824 0x828>;
309 #address-cells = <1>;
310 #size-cells = <1>;
311 ranges;
313 phy_port0: port@fe382000 {
314 #phy-cells = <1>;
315 reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
316 reg-names = "sata", "pcie";
317 };
319 phy_port1: port@fe38a000 {
320 #phy-cells = <1>;
321 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
322 reg-names = "sata", "pcie";
323 };
324 };
326 sata0: sata@fe380000 {
327 compatible = "st,sti-ahci";
328 reg = <0xfe380000 0x1000>;
329 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
330 interrupt-names = "hostc";
331 phys = <&phy_port0 PHY_TYPE_SATA>;
332 phy-names = "sata-phy";
333 resets = <&powerdown STIH416_SATA0_POWERDOWN>,
334 <&softreset STIH416_SATA0_SOFTRESET>;
335 reset-names = "pwr-dwn", "sw-rst";
336 clock-names = "ahci_clk";
337 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
339 status = "disabled";
340 };
342 usb2_phy: phy@0 {
343 compatible = "st,stih416-usb-phy";
344 #phy-cells = <0>;
345 st,syscfg = <&syscfg_rear>;
346 clocks = <&clk_sysin>;
347 clock-names = "osc_phy";
348 };
350 ehci0: usb@fe1ffe00 {
351 compatible = "st,st-ehci-300x";
352 reg = <0xfe1ffe00 0x100>;
353 interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_usb0>;
356 clocks = <&clk_s_a1_ls 0>,
357 <&clockgen_b0 0>;
358 clock-names = "ic", "clk48";
359 phys = <&usb2_phy>;
360 phy-names = "usb";
361 resets = <&powerdown STIH416_USB0_POWERDOWN>,
362 <&softreset STIH416_USB0_SOFTRESET>;
363 reset-names = "power", "softreset";
364 };
366 ohci0: usb@fe1ffc00 {
367 compatible = "st,st-ohci-300x";
368 reg = <0xfe1ffc00 0x100>;
369 interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
370 clocks = <&clk_s_a1_ls 0>,
371 <&clockgen_b0 0>;
372 clock-names = "ic", "clk48";
373 phys = <&usb2_phy>;
374 phy-names = "usb";
375 status = "okay";
376 resets = <&powerdown STIH416_USB0_POWERDOWN>,
377 <&softreset STIH416_USB0_SOFTRESET>;
378 reset-names = "power", "softreset";
379 };
381 ehci1: usb@fe203e00 {
382 compatible = "st,st-ehci-300x";
383 reg = <0xfe203e00 0x100>;
384 interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_usb1>;
387 clocks = <&clk_s_a1_ls 0>,
388 <&clockgen_b0 0>;
389 clock-names = "ic", "clk48";
390 phys = <&usb2_phy>;
391 phy-names = "usb";
392 resets = <&powerdown STIH416_USB1_POWERDOWN>,
393 <&softreset STIH416_USB1_SOFTRESET>;
394 reset-names = "power", "softreset";
395 };
397 ohci1: usb@fe203c00 {
398 compatible = "st,st-ohci-300x";
399 reg = <0xfe203c00 0x100>;
400 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
401 clocks = <&clk_s_a1_ls 0>,
402 <&clockgen_b0 0>;
403 clock-names = "ic", "clk48";
404 phys = <&usb2_phy>;
405 phy-names = "usb";
406 resets = <&powerdown STIH416_USB1_POWERDOWN>,
407 <&softreset STIH416_USB1_SOFTRESET>;
408 reset-names = "power", "softreset";
409 };
411 ehci2: usb@fe303e00 {
412 compatible = "st,st-ehci-300x";
413 reg = <0xfe303e00 0x100>;
414 interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_usb2>;
417 clocks = <&clk_s_a1_ls 0>,
418 <&clockgen_b0 0>;
419 clock-names = "ic", "clk48";
420 phys = <&usb2_phy>;
421 phy-names = "usb";
422 resets = <&powerdown STIH416_USB2_POWERDOWN>,
423 <&softreset STIH416_USB2_SOFTRESET>;
424 reset-names = "power", "softreset";
425 };
427 ohci2: usb@fe303c00 {
428 compatible = "st,st-ohci-300x";
429 reg = <0xfe303c00 0x100>;
430 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
431 clocks = <&clk_s_a1_ls 0>,
432 <&clockgen_b0 0>;
433 clock-names = "ic", "clk48";
434 phys = <&usb2_phy>;
435 phy-names = "usb";
436 resets = <&powerdown STIH416_USB2_POWERDOWN>,
437 <&softreset STIH416_USB2_SOFTRESET>;
438 reset-names = "power", "softreset";
439 };
441 ehci3: usb@fe343e00 {
442 compatible = "st,st-ehci-300x";
443 reg = <0xfe343e00 0x100>;
444 interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_usb3>;
447 clocks = <&clk_s_a1_ls 0>,
448 <&clockgen_b0 0>;
449 clock-names = "ic", "clk48";
450 phys = <&usb2_phy>;
451 phy-names = "usb";
452 resets = <&powerdown STIH416_USB3_POWERDOWN>,
453 <&softreset STIH416_USB3_SOFTRESET>;
454 reset-names = "power", "softreset";
455 };
457 ohci3: usb@fe343c00 {
458 compatible = "st,st-ohci-300x";
459 reg = <0xfe343c00 0x100>;
460 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
461 clocks = <&clk_s_a1_ls 0>,
462 <&clockgen_b0 0>;
463 clock-names = "ic", "clk48";
464 phys = <&usb2_phy>;
465 phy-names = "usb";
466 resets = <&powerdown STIH416_USB3_POWERDOWN>,
467 <&softreset STIH416_USB3_SOFTRESET>;
468 reset-names = "power", "softreset";
469 };
471 /* SAS PWM Module */
472 pwm0: pwm@fed10000 {
473 compatible = "st,sti-pwm";
474 status = "disabled";
475 #pwm-cells = <2>;
476 reg = <0xfed10000 0x68>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_pwm0_chan0_default
480 &pinctrl_pwm0_chan1_default
481 &pinctrl_pwm0_chan2_default
482 &pinctrl_pwm0_chan3_default>;
484 clock-names = "pwm";
485 clocks = <&clk_sysin>;
486 st,pwm-num-chan = <4>;
487 };
489 /* SBC PWM Module */
490 pwm1: pwm@fe510000 {
491 compatible = "st,sti-pwm";
492 status = "disabled";
493 #pwm-cells = <2>;
494 reg = <0xfe510000 0x68>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_pwm1_chan0_default
498 /*
499 * Shared with SBC_OBS_NOTRST. Don't
500 * enable unless you really know what
501 * you're doing.
502 *
503 * &pinctrl_pwm1_chan1_default
504 */
505 &pinctrl_pwm1_chan2_default
506 &pinctrl_pwm1_chan3_default>;
508 clock-names = "pwm";
509 clocks = <&clk_sysin>;
510 st,pwm-num-chan = <3>;
511 };
512 };
513 };