arch/arm/boot/dts/uniphier-ph1-sld8.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD8 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /include/ "skeleton.dtsi"
  46
  47 / {
  48         compatible = "socionext,ph1-sld8";
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 cpu@0 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a9";
  57                         reg = <0>;
  58                         next-level-cache = <&l2>;
  59                 };
  60         };
  61
  62         clocks {
  63                 arm_timer_clk: arm_timer_clk {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <50000000>;
  67                 };
  68
  69                 uart_clk: uart_clk {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <80000000>;
  73                 };
  74
  75                 iobus_clk: iobus_clk {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <100000000>;
  79                 };
  80         };
  81
  82         soc {
  83                 compatible = "simple-bus";
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 ranges;
  87                 interrupt-parent = <&intc>;
  88
  89                 extbus: extbus {
  90                         compatible = "simple-bus";
  91                         #address-cells = <2>;
  92                         #size-cells = <1>;
  93                 };
  94
  95                 l2: l2-cache@500c0000 {
  96                         compatible = "socionext,uniphier-system-cache";
  97                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  98                               <0x506c0000 0x400>;
  99                         interrupts = <0 174 4>, <0 175 4>;
 100                         cache-unified;
 101                         cache-size = <(256 * 1024)>;
 102                         cache-sets = <256>;
 103                         cache-line-size = <128>;
 104                         cache-level = <2>;
 105                 };
 106
 107                 serial0: serial@54006800 {
 108                         compatible = "socionext,uniphier-uart";
 109                         status = "disabled";
 110                         reg = <0x54006800 0x40>;
 111                         pinctrl-names = "default";
 112                         pinctrl-0 = <&pinctrl_uart0>;
 113                         interrupts = <0 33 4>;
 114                         clocks = <&uart_clk>;
 115                         fifo-size = <64>;
 116                 };
 117
 118                 serial1: serial@54006900 {
 119                         compatible = "socionext,uniphier-uart";
 120                         status = "disabled";
 121                         reg = <0x54006900 0x40>;
 122                         pinctrl-names = "default";
 123                         pinctrl-0 = <&pinctrl_uart1>;
 124                         interrupts = <0 35 4>;
 125                         clocks = <&uart_clk>;
 126                         fifo-size = <64>;
 127                 };
 128
 129                 serial2: serial@54006a00 {
 130                         compatible = "socionext,uniphier-uart";
 131                         status = "disabled";
 132                         reg = <0x54006a00 0x40>;
 133                         pinctrl-names = "default";
 134                         pinctrl-0 = <&pinctrl_uart2>;
 135                         interrupts = <0 37 4>;
 136                         clocks = <&uart_clk>;
 137                         fifo-size = <64>;
 138                 };
 139
 140                 serial3: serial@54006b00 {
 141                         compatible = "socionext,uniphier-uart";
 142                         status = "disabled";
 143                         reg = <0x54006b00 0x40>;
 144                         pinctrl-names = "default";
 145                         pinctrl-0 = <&pinctrl_uart3>;
 146                         interrupts = <0 29 4>;
 147                         clocks = <&uart_clk>;
 148                         fifo-size = <64>;
 149                 };
 150
 151                 i2c0: i2c@58400000 {
 152                         compatible = "socionext,uniphier-i2c";
 153                         status = "disabled";
 154                         reg = <0x58400000 0x40>;
 155                         #address-cells = <1>;
 156                         #size-cells = <0>;
 157                         pinctrl-names = "default";
 158                         pinctrl-0 = <&pinctrl_i2c0>;
 159                         interrupts = <0 41 1>;
 160                         clocks = <&iobus_clk>;
 161                         clock-frequency = <100000>;
 162                 };
 163
 164                 i2c1: i2c@58480000 {
 165                         compatible = "socionext,uniphier-i2c";
 166                         status = "disabled";
 167                         reg = <0x58480000 0x40>;
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         pinctrl-names = "default";
 171                         pinctrl-0 = <&pinctrl_i2c1>;
 172                         interrupts = <0 42 1>;
 173                         clocks = <&iobus_clk>;
 174                         clock-frequency = <100000>;
 175                 };
 176
 177                 /* chip-internal connection for DMD */
 178                 i2c2: i2c@58500000 {
 179                         compatible = "socionext,uniphier-i2c";
 180                         reg = <0x58500000 0x40>;
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_i2c2>;
 185                         interrupts = <0 43 1>;
 186                         clocks = <&iobus_clk>;
 187                         clock-frequency = <400000>;
 188                 };
 189
 190                 i2c3: i2c@58580000 {
 191                         compatible = "socionext,uniphier-i2c";
 192                         status = "disabled";
 193                         reg = <0x58580000 0x40>;
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&pinctrl_i2c3>;
 198                         interrupts = <0 44 1>;
 199                         clocks = <&iobus_clk>;
 200                         clock-frequency = <100000>;
 201                 };
 202
 203                 system-bus-controller@58c00000 {
 204                         compatible = "socionext,uniphier-system-bus-controller";
 205                         reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
 206                 };
 207
 208                 usb0: usb@5a800100 {
 209                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 210                         status = "disabled";
 211                         reg = <0x5a800100 0x100>;
 212                         pinctrl-names = "default";
 213                         pinctrl-0 = <&pinctrl_usb0>;
 214                         interrupts = <0 80 4>;
 215                 };
 216
 217                 usb1: usb@5a810100 {
 218                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 219                         status = "disabled";
 220                         reg = <0x5a810100 0x100>;
 221                         pinctrl-names = "default";
 222                         pinctrl-0 = <&pinctrl_usb1>;
 223                         interrupts = <0 81 4>;
 224                 };
 225
 226                 usb2: usb@5a820100 {
 227                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 228                         status = "disabled";
 229                         reg = <0x5a820100 0x100>;
 230                         pinctrl-names = "default";
 231                         pinctrl-0 = <&pinctrl_usb2>;
 232                         interrupts = <0 82 4>;
 233                 };
 234
 235                 pinctrl: pinctrl@5f801000 {
 236                         compatible = "socionext,ph1-sld8-pinctrl",
 237                                      "syscon";
 238                         reg = <0x5f801000 0xe00>;
 239                 };
 240
 241                 timer@60000200 {
 242                         compatible = "arm,cortex-a9-global-timer";
 243                         reg = <0x60000200 0x20>;
 244                         interrupts = <1 11 0x104>;
 245                         clocks = <&arm_timer_clk>;
 246                 };
 247
 248                 timer@60000600 {
 249                         compatible = "arm,cortex-a9-twd-timer";
 250                         reg = <0x60000600 0x20>;
 251                         interrupts = <1 13 0x104>;
 252                         clocks = <&arm_timer_clk>;
 253                 };
 254
 255                 intc: interrupt-controller@60001000 {
 256                         compatible = "arm,cortex-a9-gic";
 257                         #interrupt-cells = <3>;
 258                         interrupt-controller;
 259                         reg = <0x60001000 0x1000>,
 260                               <0x60000100 0x100>;
 261                 };
 262         };
 263 };
 264
 265 /include/ "uniphier-pinctrl.dtsi"