arch/arm/boot/dts/zynq-parallella.dts

   1 /*
   2  * Copyright (c) 2014 SUSE LINUX Products GmbH
   3  *
   4  * Derived from zynq-zed.dts:
   5  *
   6  *  Copyright (C) 2011 Xilinx
   7  *  Copyright (C) 2012 National Instruments Corp.
   8  *  Copyright (C) 2013 Xilinx
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19 /dts-v1/;
  20 /include/ "zynq-7000.dtsi"
  21
  22 / {
  23         model = "Adapteva Parallella Board";
  24         compatible = "adapteva,parallella", "xlnx,zynq-7000";
  25
  26         aliases {
  27                 ethernet0 = &gem0;
  28                 serial0 = &uart1;
  29         };
  30
  31         memory {
  32                 device_type = "memory";
  33                 reg = <0x0 0x40000000>;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40 };
  41
  42 &clkc {
  43         fclk-enable = <0xf>;
  44         ps-clk-frequency = <33333333>;
  45 };
  46
  47 &gem0 {
  48         status = "okay";
  49         phy-mode = "rgmii-id";
  50         phy-handle = <&ethernet_phy>;
  51
  52         ethernet_phy: ethernet-phy@0 {
  53                 /* Marvell 88E1318 */
  54                 compatible = "ethernet-phy-id0141.0e90",
  55                              "ethernet-phy-ieee802.3-c22";
  56                 reg = <0>;
  57                 marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
  58                                    <0x3 0x11 0xfff0 0xa>;
  59         };
  60 };
  61
  62 &i2c0 {
  63         status = "okay";
  64
  65         isl9305: isl9305@68 {
  66                 compatible = "isil,isl9305";
  67                 reg = <0x68>;
  68
  69                 regulators {
  70                         dcd1 {
  71                                 regulator-name = "VDD_DSP";
  72                                 regulator-always-on;
  73                         };
  74                         dcd2 {
  75                                 regulator-name = "1P35V";
  76                                 regulator-always-on;
  77                         };
  78                         ldo1 {
  79                                 regulator-name = "VDD_ADJ";
  80                         };
  81                         ldo2 {
  82                                 regulator-name = "VDD_GPIO";
  83                                 regulator-always-on;
  84                         };
  85                 };
  86         };
  87 };
  88
  89 &sdhci1 {
  90         status = "okay";
  91 };
  92
  93 &uart1 {
  94         status = "okay";
  95 };