mm: hugetlb: fix hugepage memory leak caused by wrong reserve count
[linux/fpc-iii.git] / arch / arm / boot / dts / zynq-zc706.dts
blobabf5d238ae04aa6224d5da7e0d83f67f640ec6df
1 /*
2  *  Copyright (C) 2011 - 2014 Xilinx
3  *  Copyright (C) 2012 National Instruments Corp.
4  *
5  * This software is licensed under the terms of the GNU General Public
6  * License version 2, as published by the Free Software Foundation, and
7  * may be copied, distributed, and modified under those terms.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 /dts-v1/;
15 /include/ "zynq-7000.dtsi"
17 / {
18         model = "Zynq ZC706 Development Board";
19         compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
21         aliases {
22                 ethernet0 = &gem0;
23                 i2c0 = &i2c0;
24                 serial0 = &uart1;
25         };
27         memory {
28                 device_type = "memory";
29                 reg = <0x0 0x40000000>;
30         };
32         chosen {
33                 bootargs = "earlyprintk";
34                 stdout-path = "serial0:115200n8";
35         };
37         usb_phy0: phy0 {
38                 compatible = "usb-nop-xceiv";
39                 #phy-cells = <0>;
40         };
43 &clkc {
44         ps-clk-frequency = <33333333>;
47 &gem0 {
48         status = "okay";
49         phy-mode = "rgmii-id";
50         phy-handle = <&ethernet_phy>;
51         pinctrl-names = "default";
52         pinctrl-0 = <&pinctrl_gem0_default>;
54         ethernet_phy: ethernet-phy@7 {
55                 reg = <7>;
56         };
59 &gpio0 {
60         pinctrl-names = "default";
61         pinctrl-0 = <&pinctrl_gpio0_default>;
64 &i2c0 {
65         status = "okay";
66         clock-frequency = <400000>;
67         pinctrl-names = "default";
68         pinctrl-0 = <&pinctrl_i2c0_default>;
70         i2cswitch@74 {
71                 compatible = "nxp,pca9548";
72                 #address-cells = <1>;
73                 #size-cells = <0>;
74                 reg = <0x74>;
76                 i2c@0 {
77                         #address-cells = <1>;
78                         #size-cells = <0>;
79                         reg = <0>;
80                         si570: clock-generator@5d {
81                                 #clock-cells = <0>;
82                                 compatible = "silabs,si570";
83                                 temperature-stability = <50>;
84                                 reg = <0x5d>;
85                                 factory-fout = <156250000>;
86                                 clock-frequency = <148500000>;
87                         };
88                 };
90                 i2c@2 {
91                         #address-cells = <1>;
92                         #size-cells = <0>;
93                         reg = <2>;
94                         eeprom@54 {
95                                 compatible = "at,24c08";
96                                 reg = <0x54>;
97                         };
98                 };
100                 i2c@3 {
101                         #address-cells = <1>;
102                         #size-cells = <0>;
103                         reg = <3>;
104                         gpio@21 {
105                                 compatible = "ti,tca6416";
106                                 reg = <0x21>;
107                                 gpio-controller;
108                                 #gpio-cells = <2>;
109                         };
110                 };
112                 i2c@4 {
113                         #address-cells = <1>;
114                         #size-cells = <0>;
115                         reg = <4>;
116                         rtc@51 {
117                                 compatible = "nxp,pcf8563";
118                                 reg = <0x51>;
119                         };
120                 };
122                 i2c@7 {
123                         #address-cells = <1>;
124                         #size-cells = <0>;
125                         reg = <7>;
126                         ucd90120@65 {
127                                 compatible = "ti,ucd90120";
128                                 reg = <0x65>;
129                         };
130                 };
131         };
134 &pinctrl0 {
135         pinctrl_gem0_default: gem0-default {
136                 mux {
137                         function = "ethernet0";
138                         groups = "ethernet0_0_grp";
139                 };
141                 conf {
142                         groups = "ethernet0_0_grp";
143                         slew-rate = <0>;
144                         io-standard = <4>;
145                 };
147                 conf-rx {
148                         pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
149                         bias-high-impedance;
150                         low-power-disable;
151                 };
153                 conf-tx {
154                         pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
155                         low-power-enable;
156                         bias-disable;
157                 };
159                 mux-mdio {
160                         function = "mdio0";
161                         groups = "mdio0_0_grp";
162                 };
164                 conf-mdio {
165                         groups = "mdio0_0_grp";
166                         slew-rate = <0>;
167                         io-standard = <1>;
168                         bias-disable;
169                 };
170         };
172         pinctrl_gpio0_default: gpio0-default {
173                 mux {
174                         function = "gpio0";
175                         groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
176                 };
178                 conf {
179                         groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
180                         slew-rate = <0>;
181                         io-standard = <1>;
182                 };
184                 conf-pull-up {
185                         pins = "MIO46", "MIO47";
186                         bias-pull-up;
187                 };
189                 conf-pull-none {
190                         pins = "MIO7";
191                         bias-disable;
192                 };
193         };
195         pinctrl_i2c0_default: i2c0-default {
196                 mux {
197                         groups = "i2c0_10_grp";
198                         function = "i2c0";
199                 };
201                 conf {
202                         groups = "i2c0_10_grp";
203                         bias-pull-up;
204                         slew-rate = <0>;
205                         io-standard = <1>;
206                 };
207         };
209         pinctrl_sdhci0_default: sdhci0-default {
210                 mux {
211                         groups = "sdio0_2_grp";
212                         function = "sdio0";
213                 };
215                 conf {
216                         groups = "sdio0_2_grp";
217                         slew-rate = <0>;
218                         io-standard = <1>;
219                         bias-disable;
220                 };
222                 mux-cd {
223                         groups = "gpio0_14_grp";
224                         function = "sdio0_cd";
225                 };
227                 conf-cd {
228                         groups = "gpio0_14_grp";
229                         bias-high-impedance;
230                         bias-pull-up;
231                         slew-rate = <0>;
232                         io-standard = <1>;
233                 };
235                 mux-wp {
236                         groups = "gpio0_15_grp";
237                         function = "sdio0_wp";
238                 };
240                 conf-wp {
241                         groups = "gpio0_15_grp";
242                         bias-high-impedance;
243                         bias-pull-up;
244                         slew-rate = <0>;
245                         io-standard = <1>;
246                 };
247         };
249         pinctrl_uart1_default: uart1-default {
250                 mux {
251                         groups = "uart1_10_grp";
252                         function = "uart1";
253                 };
255                 conf {
256                         groups = "uart1_10_grp";
257                         slew-rate = <0>;
258                         io-standard = <1>;
259                 };
261                 conf-rx {
262                         pins = "MIO49";
263                         bias-high-impedance;
264                 };
266                 conf-tx {
267                         pins = "MIO48";
268                         bias-disable;
269                 };
270         };
272         pinctrl_usb0_default: usb0-default {
273                 mux {
274                         groups = "usb0_0_grp";
275                         function = "usb0";
276                 };
278                 conf {
279                         groups = "usb0_0_grp";
280                         slew-rate = <0>;
281                         io-standard = <1>;
282                 };
284                 conf-rx {
285                         pins = "MIO29", "MIO31", "MIO36";
286                         bias-high-impedance;
287                 };
289                 conf-tx {
290                         pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
291                                "MIO35", "MIO37", "MIO38", "MIO39";
292                         bias-disable;
293                 };
294         };
297 &sdhci0 {
298         status = "okay";
299         pinctrl-names = "default";
300         pinctrl-0 = <&pinctrl_sdhci0_default>;
303 &uart1 {
304         status = "okay";
305         pinctrl-names = "default";
306         pinctrl-0 = <&pinctrl_uart1_default>;
309 &usb0 {
310         status = "okay";
311         dr_mode = "host";
312         usb-phy = <&usb_phy0>;
313         pinctrl-names = "default";
314         pinctrl-0 = <&pinctrl_usb0_default>;