?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mm: hugetlb: fix hugepage memory leak caused by wrong reserve count
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
blobee4e04434a943ea573210fb2468ba29a36232f07
1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
25
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
30
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "i2c.h"
37 #include "wd_timer.h"
38 #include "soc.h"
39
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
42
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
45
46
47 /*
48 * IP blocks
49 */
50
51 /*
52 * 'dmm' class
53 * instance(s): dmm
54 */
55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
56 .name = "dmm",
57 };
58
59 /* dmm */
60 static struct omap_hwmod dra7xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70 };
71
72 /*
73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2
75 */
76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
77 .name = "l3",
78 };
79
80 /* l3_instr */
81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92 };
93
94 /* l3_main_1 */
95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105 };
106
107 /* l3_main_2 */
108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
117 },
118 },
119 };
120
121 /*
122 * 'l4' class
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
124 */
125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
126 .name = "l4",
127 };
128
129 /* l4_cfg */
130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
131 .name = "l4_cfg",
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
138 },
139 },
140 };
141
142 /* l4_per1 */
143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
144 .name = "l4_per1",
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153 };
154
155 /* l4_per2 */
156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
157 .name = "l4_per2",
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 },
165 },
166 };
167
168 /* l4_per3 */
169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
170 .name = "l4_per3",
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
177 },
178 },
179 };
180
181 /* l4_wkup */
182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192 };
193
194 /*
195 * 'atl' class
196 *
197 */
198
199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
200 .name = "atl",
201 };
202
203 /* atl */
204 static struct omap_hwmod dra7xx_atl_hwmod = {
205 .name = "atl",
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216 };
217
218 /*
219 * 'bb2d' class
220 *
221 */
222
223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
224 .name = "bb2d",
225 };
226
227 /* bb2d */
228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
229 .name = "bb2d",
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
238 },
239 },
240 };
241
242 /*
243 * 'counter' class
244 *
245 */
246
247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
248 .rev_offs = 0x0000,
249 .sysc_offs = 0x0010,
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 SIDLE_SMART_WKUP),
253 .sysc_fields = &omap_hwmod_sysc_type1,
254 };
255
256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
257 .name = "counter",
258 .sysc = &dra7xx_counter_sysc,
259 };
260
261 /* counter_32k */
262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
272 },
273 },
274 };
275
276 /*
277 * 'ctrl_module' class
278 *
279 */
280
281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
283 };
284
285 /* ctrl_module_wkup */
286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
290 .prcm = {
291 .omap4 = {
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
293 },
294 },
295 };
296
297 /*
298 * 'gmac' class
299 * cpsw/gmac sub system
300 */
301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
302 .rev_offs = 0x0,
303 .sysc_offs = 0x8,
304 .syss_offs = 0x4,
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
308 MSTANDBY_NO),
309 .sysc_fields = &omap_hwmod_sysc_type3,
310 };
311
312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
313 .name = "gmac",
314 .sysc = &dra7xx_gmac_sysc,
315 };
316
317 static struct omap_hwmod dra7xx_gmac_hwmod = {
318 .name = "gmac",
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
323 .mpu_rt_idx = 1,
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
329 },
330 },
331 };
332
333 /*
334 * 'mdio' class
335 */
336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
338 };
339
340 static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
345 };
346
347 /*
348 * 'dcan' class
349 *
350 */
351
352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
353 .name = "dcan",
354 };
355
356 /* dcan1 */
357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
358 .name = "dcan1",
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
362 .prcm = {
363 .omap4 = {
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
367 },
368 },
369 };
370
371 /* dcan2 */
372 static struct omap_hwmod dra7xx_dcan2_hwmod = {
373 .name = "dcan2",
374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1",
377 .prcm = {
378 .omap4 = {
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL,
382 },
383 },
384 };
385
386 /*
387 * 'dma' class
388 *
389 */
390
391 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
392 .rev_offs = 0x0000,
393 .sysc_offs = 0x002c,
394 .syss_offs = 0x0028,
395 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
396 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
397 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
398 SYSS_HAS_RESET_STATUS),
399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
400 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
401 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
402 .sysc_fields = &omap_hwmod_sysc_type1,
403 };
404
405 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
406 .name = "dma",
407 .sysc = &dra7xx_dma_sysc,
408 };
409
410 /* dma dev_attr */
411 static struct omap_dma_dev_attr dma_dev_attr = {
412 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
413 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
414 .lch_count = 32,
415 };
416
417 /* dma_system */
418 static struct omap_hwmod dra7xx_dma_system_hwmod = {
419 .name = "dma_system",
420 .class = &dra7xx_dma_hwmod_class,
421 .clkdm_name = "dma_clkdm",
422 .main_clk = "l3_iclk_div",
423 .prcm = {
424 .omap4 = {
425 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
427 },
428 },
429 .dev_attr = &dma_dev_attr,
430 };
431
432 /*
433 * 'dss' class
434 *
435 */
436
437 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
438 .rev_offs = 0x0000,
439 .syss_offs = 0x0014,
440 .sysc_flags = SYSS_HAS_RESET_STATUS,
441 };
442
443 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
444 .name = "dss",
445 .sysc = &dra7xx_dss_sysc,
446 .reset = omap_dss_reset,
447 };
448
449 /* dss */
450 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
451 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
452 { .dma_req = -1 }
453 };
454
455 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
456 { .role = "dss_clk", .clk = "dss_dss_clk" },
457 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
458 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
459 { .role = "video2_clk", .clk = "dss_video2_clk" },
460 { .role = "video1_clk", .clk = "dss_video1_clk" },
461 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
462 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
463 };
464
465 static struct omap_hwmod dra7xx_dss_hwmod = {
466 .name = "dss_core",
467 .class = &dra7xx_dss_hwmod_class,
468 .clkdm_name = "dss_clkdm",
469 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
470 .sdma_reqs = dra7xx_dss_sdma_reqs,
471 .main_clk = "dss_dss_clk",
472 .prcm = {
473 .omap4 = {
474 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
475 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
476 .modulemode = MODULEMODE_SWCTRL,
477 },
478 },
479 .opt_clks = dss_opt_clks,
480 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
481 };
482
483 /*
484 * 'dispc' class
485 * display controller
486 */
487
488 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
489 .rev_offs = 0x0000,
490 .sysc_offs = 0x0010,
491 .syss_offs = 0x0014,
492 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
493 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
494 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
495 SYSS_HAS_RESET_STATUS),
496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
497 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
498 .sysc_fields = &omap_hwmod_sysc_type1,
499 };
500
501 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
502 .name = "dispc",
503 .sysc = &dra7xx_dispc_sysc,
504 };
505
506 /* dss_dispc */
507 /* dss_dispc dev_attr */
508 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
509 .has_framedonetv_irq = 1,
510 .manager_count = 4,
511 };
512
513 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
514 .name = "dss_dispc",
515 .class = &dra7xx_dispc_hwmod_class,
516 .clkdm_name = "dss_clkdm",
517 .main_clk = "dss_dss_clk",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
521 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
522 },
523 },
524 .dev_attr = &dss_dispc_dev_attr,
525 .parent_hwmod = &dra7xx_dss_hwmod,
526 };
527
528 /*
529 * 'hdmi' class
530 * hdmi controller
531 */
532
533 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
534 .rev_offs = 0x0000,
535 .sysc_offs = 0x0010,
536 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
537 SYSC_HAS_SOFTRESET),
538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
539 SIDLE_SMART_WKUP),
540 .sysc_fields = &omap_hwmod_sysc_type2,
541 };
542
543 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
544 .name = "hdmi",
545 .sysc = &dra7xx_hdmi_sysc,
546 };
547
548 /* dss_hdmi */
549
550 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
551 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
552 };
553
554 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
555 .name = "dss_hdmi",
556 .class = &dra7xx_hdmi_hwmod_class,
557 .clkdm_name = "dss_clkdm",
558 .main_clk = "dss_48mhz_clk",
559 .prcm = {
560 .omap4 = {
561 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
562 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
563 },
564 },
565 .opt_clks = dss_hdmi_opt_clks,
566 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
567 .parent_hwmod = &dra7xx_dss_hwmod,
568 };
569
570 /*
571 * 'elm' class
572 *
573 */
574
575 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
576 .rev_offs = 0x0000,
577 .sysc_offs = 0x0010,
578 .syss_offs = 0x0014,
579 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
580 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
581 SYSS_HAS_RESET_STATUS),
582 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
583 SIDLE_SMART_WKUP),
584 .sysc_fields = &omap_hwmod_sysc_type1,
585 };
586
587 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
588 .name = "elm",
589 .sysc = &dra7xx_elm_sysc,
590 };
591
592 /* elm */
593
594 static struct omap_hwmod dra7xx_elm_hwmod = {
595 .name = "elm",
596 .class = &dra7xx_elm_hwmod_class,
597 .clkdm_name = "l4per_clkdm",
598 .main_clk = "l3_iclk_div",
599 .prcm = {
600 .omap4 = {
601 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
602 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
603 },
604 },
605 };
606
607 /*
608 * 'gpio' class
609 *
610 */
611
612 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
613 .rev_offs = 0x0000,
614 .sysc_offs = 0x0010,
615 .syss_offs = 0x0114,
616 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
617 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
618 SYSS_HAS_RESET_STATUS),
619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
620 SIDLE_SMART_WKUP),
621 .sysc_fields = &omap_hwmod_sysc_type1,
622 };
623
624 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
625 .name = "gpio",
626 .sysc = &dra7xx_gpio_sysc,
627 .rev = 2,
628 };
629
630 /* gpio dev_attr */
631 static struct omap_gpio_dev_attr gpio_dev_attr = {
632 .bank_width = 32,
633 .dbck_flag = true,
634 };
635
636 /* gpio1 */
637 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
638 { .role = "dbclk", .clk = "gpio1_dbclk" },
639 };
640
641 static struct omap_hwmod dra7xx_gpio1_hwmod = {
642 .name = "gpio1",
643 .class = &dra7xx_gpio_hwmod_class,
644 .clkdm_name = "wkupaon_clkdm",
645 .main_clk = "wkupaon_iclk_mux",
646 .prcm = {
647 .omap4 = {
648 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
649 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
650 .modulemode = MODULEMODE_HWCTRL,
651 },
652 },
653 .opt_clks = gpio1_opt_clks,
654 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
655 .dev_attr = &gpio_dev_attr,
656 };
657
658 /* gpio2 */
659 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
660 { .role = "dbclk", .clk = "gpio2_dbclk" },
661 };
662
663 static struct omap_hwmod dra7xx_gpio2_hwmod = {
664 .name = "gpio2",
665 .class = &dra7xx_gpio_hwmod_class,
666 .clkdm_name = "l4per_clkdm",
667 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
668 .main_clk = "l3_iclk_div",
669 .prcm = {
670 .omap4 = {
671 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
672 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
673 .modulemode = MODULEMODE_HWCTRL,
674 },
675 },
676 .opt_clks = gpio2_opt_clks,
677 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
678 .dev_attr = &gpio_dev_attr,
679 };
680
681 /* gpio3 */
682 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
683 { .role = "dbclk", .clk = "gpio3_dbclk" },
684 };
685
686 static struct omap_hwmod dra7xx_gpio3_hwmod = {
687 .name = "gpio3",
688 .class = &dra7xx_gpio_hwmod_class,
689 .clkdm_name = "l4per_clkdm",
690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 .main_clk = "l3_iclk_div",
692 .prcm = {
693 .omap4 = {
694 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
695 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
696 .modulemode = MODULEMODE_HWCTRL,
697 },
698 },
699 .opt_clks = gpio3_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
701 .dev_attr = &gpio_dev_attr,
702 };
703
704 /* gpio4 */
705 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
706 { .role = "dbclk", .clk = "gpio4_dbclk" },
707 };
708
709 static struct omap_hwmod dra7xx_gpio4_hwmod = {
710 .name = "gpio4",
711 .class = &dra7xx_gpio_hwmod_class,
712 .clkdm_name = "l4per_clkdm",
713 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
714 .main_clk = "l3_iclk_div",
715 .prcm = {
716 .omap4 = {
717 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
718 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
719 .modulemode = MODULEMODE_HWCTRL,
720 },
721 },
722 .opt_clks = gpio4_opt_clks,
723 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
724 .dev_attr = &gpio_dev_attr,
725 };
726
727 /* gpio5 */
728 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
729 { .role = "dbclk", .clk = "gpio5_dbclk" },
730 };
731
732 static struct omap_hwmod dra7xx_gpio5_hwmod = {
733 .name = "gpio5",
734 .class = &dra7xx_gpio_hwmod_class,
735 .clkdm_name = "l4per_clkdm",
736 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
737 .main_clk = "l3_iclk_div",
738 .prcm = {
739 .omap4 = {
740 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
741 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
742 .modulemode = MODULEMODE_HWCTRL,
743 },
744 },
745 .opt_clks = gpio5_opt_clks,
746 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
747 .dev_attr = &gpio_dev_attr,
748 };
749
750 /* gpio6 */
751 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
752 { .role = "dbclk", .clk = "gpio6_dbclk" },
753 };
754
755 static struct omap_hwmod dra7xx_gpio6_hwmod = {
756 .name = "gpio6",
757 .class = &dra7xx_gpio_hwmod_class,
758 .clkdm_name = "l4per_clkdm",
759 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
760 .main_clk = "l3_iclk_div",
761 .prcm = {
762 .omap4 = {
763 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
764 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
765 .modulemode = MODULEMODE_HWCTRL,
766 },
767 },
768 .opt_clks = gpio6_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
770 .dev_attr = &gpio_dev_attr,
771 };
772
773 /* gpio7 */
774 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
775 { .role = "dbclk", .clk = "gpio7_dbclk" },
776 };
777
778 static struct omap_hwmod dra7xx_gpio7_hwmod = {
779 .name = "gpio7",
780 .class = &dra7xx_gpio_hwmod_class,
781 .clkdm_name = "l4per_clkdm",
782 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
783 .main_clk = "l3_iclk_div",
784 .prcm = {
785 .omap4 = {
786 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
787 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
788 .modulemode = MODULEMODE_HWCTRL,
789 },
790 },
791 .opt_clks = gpio7_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
793 .dev_attr = &gpio_dev_attr,
794 };
795
796 /* gpio8 */
797 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
798 { .role = "dbclk", .clk = "gpio8_dbclk" },
799 };
800
801 static struct omap_hwmod dra7xx_gpio8_hwmod = {
802 .name = "gpio8",
803 .class = &dra7xx_gpio_hwmod_class,
804 .clkdm_name = "l4per_clkdm",
805 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
806 .main_clk = "l3_iclk_div",
807 .prcm = {
808 .omap4 = {
809 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
810 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
811 .modulemode = MODULEMODE_HWCTRL,
812 },
813 },
814 .opt_clks = gpio8_opt_clks,
815 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
816 .dev_attr = &gpio_dev_attr,
817 };
818
819 /*
820 * 'gpmc' class
821 *
822 */
823
824 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
825 .rev_offs = 0x0000,
826 .sysc_offs = 0x0010,
827 .syss_offs = 0x0014,
828 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
829 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
830 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
831 .sysc_fields = &omap_hwmod_sysc_type1,
832 };
833
834 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
835 .name = "gpmc",
836 .sysc = &dra7xx_gpmc_sysc,
837 };
838
839 /* gpmc */
840
841 static struct omap_hwmod dra7xx_gpmc_hwmod = {
842 .name = "gpmc",
843 .class = &dra7xx_gpmc_hwmod_class,
844 .clkdm_name = "l3main1_clkdm",
845 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
846 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
847 .main_clk = "l3_iclk_div",
848 .prcm = {
849 .omap4 = {
850 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
851 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
852 .modulemode = MODULEMODE_HWCTRL,
853 },
854 },
855 };
856
857 /*
858 * 'hdq1w' class
859 *
860 */
861
862 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
863 .rev_offs = 0x0000,
864 .sysc_offs = 0x0014,
865 .syss_offs = 0x0018,
866 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
867 SYSS_HAS_RESET_STATUS),
868 .sysc_fields = &omap_hwmod_sysc_type1,
869 };
870
871 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
872 .name = "hdq1w",
873 .sysc = &dra7xx_hdq1w_sysc,
874 };
875
876 /* hdq1w */
877
878 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
879 .name = "hdq1w",
880 .class = &dra7xx_hdq1w_hwmod_class,
881 .clkdm_name = "l4per_clkdm",
882 .flags = HWMOD_INIT_NO_RESET,
883 .main_clk = "func_12m_fclk",
884 .prcm = {
885 .omap4 = {
886 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
887 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
888 .modulemode = MODULEMODE_SWCTRL,
889 },
890 },
891 };
892
893 /*
894 * 'i2c' class
895 *
896 */
897
898 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
899 .sysc_offs = 0x0010,
900 .syss_offs = 0x0090,
901 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
902 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
903 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
904 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
905 SIDLE_SMART_WKUP),
906 .clockact = CLOCKACT_TEST_ICLK,
907 .sysc_fields = &omap_hwmod_sysc_type1,
908 };
909
910 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
911 .name = "i2c",
912 .sysc = &dra7xx_i2c_sysc,
913 .reset = &omap_i2c_reset,
914 .rev = OMAP_I2C_IP_VERSION_2,
915 };
916
917 /* i2c dev_attr */
918 static struct omap_i2c_dev_attr i2c_dev_attr = {
919 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
920 };
921
922 /* i2c1 */
923 static struct omap_hwmod dra7xx_i2c1_hwmod = {
924 .name = "i2c1",
925 .class = &dra7xx_i2c_hwmod_class,
926 .clkdm_name = "l4per_clkdm",
927 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
928 .main_clk = "func_96m_fclk",
929 .prcm = {
930 .omap4 = {
931 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
932 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
933 .modulemode = MODULEMODE_SWCTRL,
934 },
935 },
936 .dev_attr = &i2c_dev_attr,
937 };
938
939 /* i2c2 */
940 static struct omap_hwmod dra7xx_i2c2_hwmod = {
941 .name = "i2c2",
942 .class = &dra7xx_i2c_hwmod_class,
943 .clkdm_name = "l4per_clkdm",
944 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
945 .main_clk = "func_96m_fclk",
946 .prcm = {
947 .omap4 = {
948 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
949 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
950 .modulemode = MODULEMODE_SWCTRL,
951 },
952 },
953 .dev_attr = &i2c_dev_attr,
954 };
955
956 /* i2c3 */
957 static struct omap_hwmod dra7xx_i2c3_hwmod = {
958 .name = "i2c3",
959 .class = &dra7xx_i2c_hwmod_class,
960 .clkdm_name = "l4per_clkdm",
961 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
962 .main_clk = "func_96m_fclk",
963 .prcm = {
964 .omap4 = {
965 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
966 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
967 .modulemode = MODULEMODE_SWCTRL,
968 },
969 },
970 .dev_attr = &i2c_dev_attr,
971 };
972
973 /* i2c4 */
974 static struct omap_hwmod dra7xx_i2c4_hwmod = {
975 .name = "i2c4",
976 .class = &dra7xx_i2c_hwmod_class,
977 .clkdm_name = "l4per_clkdm",
978 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
979 .main_clk = "func_96m_fclk",
980 .prcm = {
981 .omap4 = {
982 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
983 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
984 .modulemode = MODULEMODE_SWCTRL,
985 },
986 },
987 .dev_attr = &i2c_dev_attr,
988 };
989
990 /* i2c5 */
991 static struct omap_hwmod dra7xx_i2c5_hwmod = {
992 .name = "i2c5",
993 .class = &dra7xx_i2c_hwmod_class,
994 .clkdm_name = "ipu_clkdm",
995 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
996 .main_clk = "func_96m_fclk",
997 .prcm = {
998 .omap4 = {
999 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1000 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1001 .modulemode = MODULEMODE_SWCTRL,
1002 },
1003 },
1004 .dev_attr = &i2c_dev_attr,
1005 };
1006
1007 /*
1008 * 'mailbox' class
1009 *
1010 */
1011
1012 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1013 .rev_offs = 0x0000,
1014 .sysc_offs = 0x0010,
1015 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1016 SYSC_HAS_SOFTRESET),
1017 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1018 .sysc_fields = &omap_hwmod_sysc_type2,
1019 };
1020
1021 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1022 .name = "mailbox",
1023 .sysc = &dra7xx_mailbox_sysc,
1024 };
1025
1026 /* mailbox1 */
1027 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1028 .name = "mailbox1",
1029 .class = &dra7xx_mailbox_hwmod_class,
1030 .clkdm_name = "l4cfg_clkdm",
1031 .prcm = {
1032 .omap4 = {
1033 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1034 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1035 },
1036 },
1037 };
1038
1039 /* mailbox2 */
1040 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1041 .name = "mailbox2",
1042 .class = &dra7xx_mailbox_hwmod_class,
1043 .clkdm_name = "l4cfg_clkdm",
1044 .prcm = {
1045 .omap4 = {
1046 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1047 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1048 },
1049 },
1050 };
1051
1052 /* mailbox3 */
1053 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1054 .name = "mailbox3",
1055 .class = &dra7xx_mailbox_hwmod_class,
1056 .clkdm_name = "l4cfg_clkdm",
1057 .prcm = {
1058 .omap4 = {
1059 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1060 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1061 },
1062 },
1063 };
1064
1065 /* mailbox4 */
1066 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1067 .name = "mailbox4",
1068 .class = &dra7xx_mailbox_hwmod_class,
1069 .clkdm_name = "l4cfg_clkdm",
1070 .prcm = {
1071 .omap4 = {
1072 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1073 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1074 },
1075 },
1076 };
1077
1078 /* mailbox5 */
1079 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1080 .name = "mailbox5",
1081 .class = &dra7xx_mailbox_hwmod_class,
1082 .clkdm_name = "l4cfg_clkdm",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1087 },
1088 },
1089 };
1090
1091 /* mailbox6 */
1092 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1093 .name = "mailbox6",
1094 .class = &dra7xx_mailbox_hwmod_class,
1095 .clkdm_name = "l4cfg_clkdm",
1096 .prcm = {
1097 .omap4 = {
1098 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1099 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1100 },
1101 },
1102 };
1103
1104 /* mailbox7 */
1105 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1106 .name = "mailbox7",
1107 .class = &dra7xx_mailbox_hwmod_class,
1108 .clkdm_name = "l4cfg_clkdm",
1109 .prcm = {
1110 .omap4 = {
1111 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1112 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1113 },
1114 },
1115 };
1116
1117 /* mailbox8 */
1118 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1119 .name = "mailbox8",
1120 .class = &dra7xx_mailbox_hwmod_class,
1121 .clkdm_name = "l4cfg_clkdm",
1122 .prcm = {
1123 .omap4 = {
1124 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1125 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1126 },
1127 },
1128 };
1129
1130 /* mailbox9 */
1131 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1132 .name = "mailbox9",
1133 .class = &dra7xx_mailbox_hwmod_class,
1134 .clkdm_name = "l4cfg_clkdm",
1135 .prcm = {
1136 .omap4 = {
1137 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1138 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1139 },
1140 },
1141 };
1142
1143 /* mailbox10 */
1144 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1145 .name = "mailbox10",
1146 .class = &dra7xx_mailbox_hwmod_class,
1147 .clkdm_name = "l4cfg_clkdm",
1148 .prcm = {
1149 .omap4 = {
1150 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1151 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1152 },
1153 },
1154 };
1155
1156 /* mailbox11 */
1157 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1158 .name = "mailbox11",
1159 .class = &dra7xx_mailbox_hwmod_class,
1160 .clkdm_name = "l4cfg_clkdm",
1161 .prcm = {
1162 .omap4 = {
1163 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1164 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1165 },
1166 },
1167 };
1168
1169 /* mailbox12 */
1170 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1171 .name = "mailbox12",
1172 .class = &dra7xx_mailbox_hwmod_class,
1173 .clkdm_name = "l4cfg_clkdm",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1178 },
1179 },
1180 };
1181
1182 /* mailbox13 */
1183 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1184 .name = "mailbox13",
1185 .class = &dra7xx_mailbox_hwmod_class,
1186 .clkdm_name = "l4cfg_clkdm",
1187 .prcm = {
1188 .omap4 = {
1189 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1190 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1191 },
1192 },
1193 };
1194
1195 /*
1196 * 'mcspi' class
1197 *
1198 */
1199
1200 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1201 .rev_offs = 0x0000,
1202 .sysc_offs = 0x0010,
1203 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1204 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1205 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1206 SIDLE_SMART_WKUP),
1207 .sysc_fields = &omap_hwmod_sysc_type2,
1208 };
1209
1210 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1211 .name = "mcspi",
1212 .sysc = &dra7xx_mcspi_sysc,
1213 .rev = OMAP4_MCSPI_REV,
1214 };
1215
1216 /* mcspi1 */
1217 /* mcspi1 dev_attr */
1218 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1219 .num_chipselect = 4,
1220 };
1221
1222 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1223 .name = "mcspi1",
1224 .class = &dra7xx_mcspi_hwmod_class,
1225 .clkdm_name = "l4per_clkdm",
1226 .main_clk = "func_48m_fclk",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1230 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_SWCTRL,
1232 },
1233 },
1234 .dev_attr = &mcspi1_dev_attr,
1235 };
1236
1237 /* mcspi2 */
1238 /* mcspi2 dev_attr */
1239 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1240 .num_chipselect = 2,
1241 };
1242
1243 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1244 .name = "mcspi2",
1245 .class = &dra7xx_mcspi_hwmod_class,
1246 .clkdm_name = "l4per_clkdm",
1247 .main_clk = "func_48m_fclk",
1248 .prcm = {
1249 .omap4 = {
1250 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1251 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1252 .modulemode = MODULEMODE_SWCTRL,
1253 },
1254 },
1255 .dev_attr = &mcspi2_dev_attr,
1256 };
1257
1258 /* mcspi3 */
1259 /* mcspi3 dev_attr */
1260 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1261 .num_chipselect = 2,
1262 };
1263
1264 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1265 .name = "mcspi3",
1266 .class = &dra7xx_mcspi_hwmod_class,
1267 .clkdm_name = "l4per_clkdm",
1268 .main_clk = "func_48m_fclk",
1269 .prcm = {
1270 .omap4 = {
1271 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1272 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1273 .modulemode = MODULEMODE_SWCTRL,
1274 },
1275 },
1276 .dev_attr = &mcspi3_dev_attr,
1277 };
1278
1279 /* mcspi4 */
1280 /* mcspi4 dev_attr */
1281 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1282 .num_chipselect = 1,
1283 };
1284
1285 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1286 .name = "mcspi4",
1287 .class = &dra7xx_mcspi_hwmod_class,
1288 .clkdm_name = "l4per_clkdm",
1289 .main_clk = "func_48m_fclk",
1290 .prcm = {
1291 .omap4 = {
1292 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1293 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1294 .modulemode = MODULEMODE_SWCTRL,
1295 },
1296 },
1297 .dev_attr = &mcspi4_dev_attr,
1298 };
1299
1300 /*
1301 * 'mcasp' class
1302 *
1303 */
1304 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1305 .sysc_offs = 0x0004,
1306 .sysc_flags = SYSC_HAS_SIDLEMODE,
1307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1308 .sysc_fields = &omap_hwmod_sysc_type3,
1309 };
1310
1311 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1312 .name = "mcasp",
1313 .sysc = &dra7xx_mcasp_sysc,
1314 };
1315
1316 /* mcasp3 */
1317 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1318 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1319 };
1320
1321 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1322 .name = "mcasp3",
1323 .class = &dra7xx_mcasp_hwmod_class,
1324 .clkdm_name = "l4per2_clkdm",
1325 .main_clk = "mcasp3_aux_gfclk_mux",
1326 .flags = HWMOD_OPT_CLKS_NEEDED,
1327 .prcm = {
1328 .omap4 = {
1329 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1330 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1331 .modulemode = MODULEMODE_SWCTRL,
1332 },
1333 },
1334 .opt_clks = mcasp3_opt_clks,
1335 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1336 };
1337
1338 /*
1339 * 'mmc' class
1340 *
1341 */
1342
1343 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1344 .rev_offs = 0x0000,
1345 .sysc_offs = 0x0010,
1346 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1347 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1348 SYSC_HAS_SOFTRESET),
1349 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1350 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1351 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1352 .sysc_fields = &omap_hwmod_sysc_type2,
1353 };
1354
1355 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1356 .name = "mmc",
1357 .sysc = &dra7xx_mmc_sysc,
1358 };
1359
1360 /* mmc1 */
1361 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1362 { .role = "clk32k", .clk = "mmc1_clk32k" },
1363 };
1364
1365 /* mmc1 dev_attr */
1366 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1367 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1368 };
1369
1370 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1371 .name = "mmc1",
1372 .class = &dra7xx_mmc_hwmod_class,
1373 .clkdm_name = "l3init_clkdm",
1374 .main_clk = "mmc1_fclk_div",
1375 .prcm = {
1376 .omap4 = {
1377 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1378 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1379 .modulemode = MODULEMODE_SWCTRL,
1380 },
1381 },
1382 .opt_clks = mmc1_opt_clks,
1383 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1384 .dev_attr = &mmc1_dev_attr,
1385 };
1386
1387 /* mmc2 */
1388 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1389 { .role = "clk32k", .clk = "mmc2_clk32k" },
1390 };
1391
1392 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1393 .name = "mmc2",
1394 .class = &dra7xx_mmc_hwmod_class,
1395 .clkdm_name = "l3init_clkdm",
1396 .main_clk = "mmc2_fclk_div",
1397 .prcm = {
1398 .omap4 = {
1399 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1400 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1401 .modulemode = MODULEMODE_SWCTRL,
1402 },
1403 },
1404 .opt_clks = mmc2_opt_clks,
1405 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1406 };
1407
1408 /* mmc3 */
1409 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1410 { .role = "clk32k", .clk = "mmc3_clk32k" },
1411 };
1412
1413 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1414 .name = "mmc3",
1415 .class = &dra7xx_mmc_hwmod_class,
1416 .clkdm_name = "l4per_clkdm",
1417 .main_clk = "mmc3_gfclk_div",
1418 .prcm = {
1419 .omap4 = {
1420 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1421 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1422 .modulemode = MODULEMODE_SWCTRL,
1423 },
1424 },
1425 .opt_clks = mmc3_opt_clks,
1426 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1427 };
1428
1429 /* mmc4 */
1430 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1431 { .role = "clk32k", .clk = "mmc4_clk32k" },
1432 };
1433
1434 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1435 .name = "mmc4",
1436 .class = &dra7xx_mmc_hwmod_class,
1437 .clkdm_name = "l4per_clkdm",
1438 .main_clk = "mmc4_gfclk_div",
1439 .prcm = {
1440 .omap4 = {
1441 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1442 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1443 .modulemode = MODULEMODE_SWCTRL,
1444 },
1445 },
1446 .opt_clks = mmc4_opt_clks,
1447 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1448 };
1449
1450 /*
1451 * 'mpu' class
1452 *
1453 */
1454
1455 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1456 .name = "mpu",
1457 };
1458
1459 /* mpu */
1460 static struct omap_hwmod dra7xx_mpu_hwmod = {
1461 .name = "mpu",
1462 .class = &dra7xx_mpu_hwmod_class,
1463 .clkdm_name = "mpu_clkdm",
1464 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1465 .main_clk = "dpll_mpu_m2_ck",
1466 .prcm = {
1467 .omap4 = {
1468 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1469 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1470 },
1471 },
1472 };
1473
1474 /*
1475 * 'ocp2scp' class
1476 *
1477 */
1478
1479 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1480 .rev_offs = 0x0000,
1481 .sysc_offs = 0x0010,
1482 .syss_offs = 0x0014,
1483 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1484 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1485 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1486 SIDLE_SMART_WKUP),
1487 .sysc_fields = &omap_hwmod_sysc_type1,
1488 };
1489
1490 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1491 .name = "ocp2scp",
1492 .sysc = &dra7xx_ocp2scp_sysc,
1493 };
1494
1495 /* ocp2scp1 */
1496 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1497 .name = "ocp2scp1",
1498 .class = &dra7xx_ocp2scp_hwmod_class,
1499 .clkdm_name = "l3init_clkdm",
1500 .main_clk = "l4_root_clk_div",
1501 .prcm = {
1502 .omap4 = {
1503 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1504 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1505 .modulemode = MODULEMODE_HWCTRL,
1506 },
1507 },
1508 };
1509
1510 /* ocp2scp3 */
1511 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1512 .name = "ocp2scp3",
1513 .class = &dra7xx_ocp2scp_hwmod_class,
1514 .clkdm_name = "l3init_clkdm",
1515 .main_clk = "l4_root_clk_div",
1516 .prcm = {
1517 .omap4 = {
1518 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1519 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1520 .modulemode = MODULEMODE_HWCTRL,
1521 },
1522 },
1523 };
1524
1525 /*
1526 * 'PCIE' class
1527 *
1528 */
1529
1530 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1531 .name = "pcie",
1532 };
1533
1534 /* pcie1 */
1535 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1536 .name = "pcie1",
1537 .class = &dra7xx_pciess_hwmod_class,
1538 .clkdm_name = "pcie_clkdm",
1539 .main_clk = "l4_root_clk_div",
1540 .prcm = {
1541 .omap4 = {
1542 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1543 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1544 .modulemode = MODULEMODE_SWCTRL,
1545 },
1546 },
1547 };
1548
1549 /* pcie2 */
1550 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1551 .name = "pcie2",
1552 .class = &dra7xx_pciess_hwmod_class,
1553 .clkdm_name = "pcie_clkdm",
1554 .main_clk = "l4_root_clk_div",
1555 .prcm = {
1556 .omap4 = {
1557 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1558 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1559 .modulemode = MODULEMODE_SWCTRL,
1560 },
1561 },
1562 };
1563
1564 /*
1565 * 'qspi' class
1566 *
1567 */
1568
1569 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1570 .sysc_offs = 0x0010,
1571 .sysc_flags = SYSC_HAS_SIDLEMODE,
1572 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1573 SIDLE_SMART_WKUP),
1574 .sysc_fields = &omap_hwmod_sysc_type2,
1575 };
1576
1577 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1578 .name = "qspi",
1579 .sysc = &dra7xx_qspi_sysc,
1580 };
1581
1582 /* qspi */
1583 static struct omap_hwmod dra7xx_qspi_hwmod = {
1584 .name = "qspi",
1585 .class = &dra7xx_qspi_hwmod_class,
1586 .clkdm_name = "l4per2_clkdm",
1587 .main_clk = "qspi_gfclk_div",
1588 .prcm = {
1589 .omap4 = {
1590 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1591 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1592 .modulemode = MODULEMODE_SWCTRL,
1593 },
1594 },
1595 };
1596
1597 /*
1598 * 'rtcss' class
1599 *
1600 */
1601 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1602 .sysc_offs = 0x0078,
1603 .sysc_flags = SYSC_HAS_SIDLEMODE,
1604 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1605 SIDLE_SMART_WKUP),
1606 .sysc_fields = &omap_hwmod_sysc_type3,
1607 };
1608
1609 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1610 .name = "rtcss",
1611 .sysc = &dra7xx_rtcss_sysc,
1612 };
1613
1614 /* rtcss */
1615 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1616 .name = "rtcss",
1617 .class = &dra7xx_rtcss_hwmod_class,
1618 .clkdm_name = "rtc_clkdm",
1619 .main_clk = "sys_32k_ck",
1620 .prcm = {
1621 .omap4 = {
1622 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1623 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1624 .modulemode = MODULEMODE_SWCTRL,
1625 },
1626 },
1627 };
1628
1629 /*
1630 * 'sata' class
1631 *
1632 */
1633
1634 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1635 .sysc_offs = 0x0000,
1636 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1637 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1638 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1639 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1640 .sysc_fields = &omap_hwmod_sysc_type2,
1641 };
1642
1643 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1644 .name = "sata",
1645 .sysc = &dra7xx_sata_sysc,
1646 };
1647
1648 /* sata */
1649
1650 static struct omap_hwmod dra7xx_sata_hwmod = {
1651 .name = "sata",
1652 .class = &dra7xx_sata_hwmod_class,
1653 .clkdm_name = "l3init_clkdm",
1654 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1655 .main_clk = "func_48m_fclk",
1656 .mpu_rt_idx = 1,
1657 .prcm = {
1658 .omap4 = {
1659 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1660 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1661 .modulemode = MODULEMODE_SWCTRL,
1662 },
1663 },
1664 };
1665
1666 /*
1667 * 'smartreflex' class
1668 *
1669 */
1670
1671 /* The IP is not compliant to type1 / type2 scheme */
1672 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1673 .sidle_shift = 24,
1674 .enwkup_shift = 26,
1675 };
1676
1677 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1678 .sysc_offs = 0x0038,
1679 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1680 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1681 SIDLE_SMART_WKUP),
1682 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1683 };
1684
1685 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1686 .name = "smartreflex",
1687 .sysc = &dra7xx_smartreflex_sysc,
1688 .rev = 2,
1689 };
1690
1691 /* smartreflex_core */
1692 /* smartreflex_core dev_attr */
1693 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1694 .sensor_voltdm_name = "core",
1695 };
1696
1697 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1698 .name = "smartreflex_core",
1699 .class = &dra7xx_smartreflex_hwmod_class,
1700 .clkdm_name = "coreaon_clkdm",
1701 .main_clk = "wkupaon_iclk_mux",
1702 .prcm = {
1703 .omap4 = {
1704 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1705 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1706 .modulemode = MODULEMODE_SWCTRL,
1707 },
1708 },
1709 .dev_attr = &smartreflex_core_dev_attr,
1710 };
1711
1712 /* smartreflex_mpu */
1713 /* smartreflex_mpu dev_attr */
1714 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1715 .sensor_voltdm_name = "mpu",
1716 };
1717
1718 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1719 .name = "smartreflex_mpu",
1720 .class = &dra7xx_smartreflex_hwmod_class,
1721 .clkdm_name = "coreaon_clkdm",
1722 .main_clk = "wkupaon_iclk_mux",
1723 .prcm = {
1724 .omap4 = {
1725 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1726 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1727 .modulemode = MODULEMODE_SWCTRL,
1728 },
1729 },
1730 .dev_attr = &smartreflex_mpu_dev_attr,
1731 };
1732
1733 /*
1734 * 'spinlock' class
1735 *
1736 */
1737
1738 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1739 .rev_offs = 0x0000,
1740 .sysc_offs = 0x0010,
1741 .syss_offs = 0x0014,
1742 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1743 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1744 SYSS_HAS_RESET_STATUS),
1745 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1746 .sysc_fields = &omap_hwmod_sysc_type1,
1747 };
1748
1749 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1750 .name = "spinlock",
1751 .sysc = &dra7xx_spinlock_sysc,
1752 };
1753
1754 /* spinlock */
1755 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1756 .name = "spinlock",
1757 .class = &dra7xx_spinlock_hwmod_class,
1758 .clkdm_name = "l4cfg_clkdm",
1759 .main_clk = "l3_iclk_div",
1760 .prcm = {
1761 .omap4 = {
1762 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1763 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1764 },
1765 },
1766 };
1767
1768 /*
1769 * 'timer' class
1770 *
1771 * This class contains several variants: ['timer_1ms', 'timer_secure',
1772 * 'timer']
1773 */
1774
1775 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1776 .rev_offs = 0x0000,
1777 .sysc_offs = 0x0010,
1778 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1779 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1780 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1781 SIDLE_SMART_WKUP),
1782 .sysc_fields = &omap_hwmod_sysc_type2,
1783 };
1784
1785 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1786 .name = "timer",
1787 .sysc = &dra7xx_timer_1ms_sysc,
1788 };
1789
1790 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1791 .rev_offs = 0x0000,
1792 .sysc_offs = 0x0010,
1793 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1794 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1795 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1796 SIDLE_SMART_WKUP),
1797 .sysc_fields = &omap_hwmod_sysc_type2,
1798 };
1799
1800 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1801 .name = "timer",
1802 .sysc = &dra7xx_timer_sysc,
1803 };
1804
1805 /* timer1 */
1806 static struct omap_hwmod dra7xx_timer1_hwmod = {
1807 .name = "timer1",
1808 .class = &dra7xx_timer_1ms_hwmod_class,
1809 .clkdm_name = "wkupaon_clkdm",
1810 .main_clk = "timer1_gfclk_mux",
1811 .prcm = {
1812 .omap4 = {
1813 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1814 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1815 .modulemode = MODULEMODE_SWCTRL,
1816 },
1817 },
1818 };
1819
1820 /* timer2 */
1821 static struct omap_hwmod dra7xx_timer2_hwmod = {
1822 .name = "timer2",
1823 .class = &dra7xx_timer_1ms_hwmod_class,
1824 .clkdm_name = "l4per_clkdm",
1825 .main_clk = "timer2_gfclk_mux",
1826 .prcm = {
1827 .omap4 = {
1828 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1829 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1830 .modulemode = MODULEMODE_SWCTRL,
1831 },
1832 },
1833 };
1834
1835 /* timer3 */
1836 static struct omap_hwmod dra7xx_timer3_hwmod = {
1837 .name = "timer3",
1838 .class = &dra7xx_timer_hwmod_class,
1839 .clkdm_name = "l4per_clkdm",
1840 .main_clk = "timer3_gfclk_mux",
1841 .prcm = {
1842 .omap4 = {
1843 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1844 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1845 .modulemode = MODULEMODE_SWCTRL,
1846 },
1847 },
1848 };
1849
1850 /* timer4 */
1851 static struct omap_hwmod dra7xx_timer4_hwmod = {
1852 .name = "timer4",
1853 .class = &dra7xx_timer_hwmod_class,
1854 .clkdm_name = "l4per_clkdm",
1855 .main_clk = "timer4_gfclk_mux",
1856 .prcm = {
1857 .omap4 = {
1858 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1859 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1860 .modulemode = MODULEMODE_SWCTRL,
1861 },
1862 },
1863 };
1864
1865 /* timer5 */
1866 static struct omap_hwmod dra7xx_timer5_hwmod = {
1867 .name = "timer5",
1868 .class = &dra7xx_timer_hwmod_class,
1869 .clkdm_name = "ipu_clkdm",
1870 .main_clk = "timer5_gfclk_mux",
1871 .prcm = {
1872 .omap4 = {
1873 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1874 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1875 .modulemode = MODULEMODE_SWCTRL,
1876 },
1877 },
1878 };
1879
1880 /* timer6 */
1881 static struct omap_hwmod dra7xx_timer6_hwmod = {
1882 .name = "timer6",
1883 .class = &dra7xx_timer_hwmod_class,
1884 .clkdm_name = "ipu_clkdm",
1885 .main_clk = "timer6_gfclk_mux",
1886 .prcm = {
1887 .omap4 = {
1888 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1889 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1890 .modulemode = MODULEMODE_SWCTRL,
1891 },
1892 },
1893 };
1894
1895 /* timer7 */
1896 static struct omap_hwmod dra7xx_timer7_hwmod = {
1897 .name = "timer7",
1898 .class = &dra7xx_timer_hwmod_class,
1899 .clkdm_name = "ipu_clkdm",
1900 .main_clk = "timer7_gfclk_mux",
1901 .prcm = {
1902 .omap4 = {
1903 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1904 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1905 .modulemode = MODULEMODE_SWCTRL,
1906 },
1907 },
1908 };
1909
1910 /* timer8 */
1911 static struct omap_hwmod dra7xx_timer8_hwmod = {
1912 .name = "timer8",
1913 .class = &dra7xx_timer_hwmod_class,
1914 .clkdm_name = "ipu_clkdm",
1915 .main_clk = "timer8_gfclk_mux",
1916 .prcm = {
1917 .omap4 = {
1918 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1919 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1920 .modulemode = MODULEMODE_SWCTRL,
1921 },
1922 },
1923 };
1924
1925 /* timer9 */
1926 static struct omap_hwmod dra7xx_timer9_hwmod = {
1927 .name = "timer9",
1928 .class = &dra7xx_timer_hwmod_class,
1929 .clkdm_name = "l4per_clkdm",
1930 .main_clk = "timer9_gfclk_mux",
1931 .prcm = {
1932 .omap4 = {
1933 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1934 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1935 .modulemode = MODULEMODE_SWCTRL,
1936 },
1937 },
1938 };
1939
1940 /* timer10 */
1941 static struct omap_hwmod dra7xx_timer10_hwmod = {
1942 .name = "timer10",
1943 .class = &dra7xx_timer_1ms_hwmod_class,
1944 .clkdm_name = "l4per_clkdm",
1945 .main_clk = "timer10_gfclk_mux",
1946 .prcm = {
1947 .omap4 = {
1948 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1949 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1950 .modulemode = MODULEMODE_SWCTRL,
1951 },
1952 },
1953 };
1954
1955 /* timer11 */
1956 static struct omap_hwmod dra7xx_timer11_hwmod = {
1957 .name = "timer11",
1958 .class = &dra7xx_timer_hwmod_class,
1959 .clkdm_name = "l4per_clkdm",
1960 .main_clk = "timer11_gfclk_mux",
1961 .prcm = {
1962 .omap4 = {
1963 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1964 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1965 .modulemode = MODULEMODE_SWCTRL,
1966 },
1967 },
1968 };
1969
1970 /* timer13 */
1971 static struct omap_hwmod dra7xx_timer13_hwmod = {
1972 .name = "timer13",
1973 .class = &dra7xx_timer_hwmod_class,
1974 .clkdm_name = "l4per3_clkdm",
1975 .main_clk = "timer13_gfclk_mux",
1976 .prcm = {
1977 .omap4 = {
1978 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1979 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1980 .modulemode = MODULEMODE_SWCTRL,
1981 },
1982 },
1983 };
1984
1985 /* timer14 */
1986 static struct omap_hwmod dra7xx_timer14_hwmod = {
1987 .name = "timer14",
1988 .class = &dra7xx_timer_hwmod_class,
1989 .clkdm_name = "l4per3_clkdm",
1990 .main_clk = "timer14_gfclk_mux",
1991 .prcm = {
1992 .omap4 = {
1993 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1994 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1995 .modulemode = MODULEMODE_SWCTRL,
1996 },
1997 },
1998 };
1999
2000 /* timer15 */
2001 static struct omap_hwmod dra7xx_timer15_hwmod = {
2002 .name = "timer15",
2003 .class = &dra7xx_timer_hwmod_class,
2004 .clkdm_name = "l4per3_clkdm",
2005 .main_clk = "timer15_gfclk_mux",
2006 .prcm = {
2007 .omap4 = {
2008 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2009 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2010 .modulemode = MODULEMODE_SWCTRL,
2011 },
2012 },
2013 };
2014
2015 /* timer16 */
2016 static struct omap_hwmod dra7xx_timer16_hwmod = {
2017 .name = "timer16",
2018 .class = &dra7xx_timer_hwmod_class,
2019 .clkdm_name = "l4per3_clkdm",
2020 .main_clk = "timer16_gfclk_mux",
2021 .prcm = {
2022 .omap4 = {
2023 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2024 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2025 .modulemode = MODULEMODE_SWCTRL,
2026 },
2027 },
2028 };
2029
2030 /*
2031 * 'uart' class
2032 *
2033 */
2034
2035 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2036 .rev_offs = 0x0050,
2037 .sysc_offs = 0x0054,
2038 .syss_offs = 0x0058,
2039 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2040 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2041 SYSS_HAS_RESET_STATUS),
2042 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2043 SIDLE_SMART_WKUP),
2044 .sysc_fields = &omap_hwmod_sysc_type1,
2045 };
2046
2047 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2048 .name = "uart",
2049 .sysc = &dra7xx_uart_sysc,
2050 };
2051
2052 /* uart1 */
2053 static struct omap_hwmod dra7xx_uart1_hwmod = {
2054 .name = "uart1",
2055 .class = &dra7xx_uart_hwmod_class,
2056 .clkdm_name = "l4per_clkdm",
2057 .main_clk = "uart1_gfclk_mux",
2058 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2059 .prcm = {
2060 .omap4 = {
2061 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2062 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2063 .modulemode = MODULEMODE_SWCTRL,
2064 },
2065 },
2066 };
2067
2068 /* uart2 */
2069 static struct omap_hwmod dra7xx_uart2_hwmod = {
2070 .name = "uart2",
2071 .class = &dra7xx_uart_hwmod_class,
2072 .clkdm_name = "l4per_clkdm",
2073 .main_clk = "uart2_gfclk_mux",
2074 .flags = HWMOD_SWSUP_SIDLE_ACT,
2075 .prcm = {
2076 .omap4 = {
2077 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2078 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2079 .modulemode = MODULEMODE_SWCTRL,
2080 },
2081 },
2082 };
2083
2084 /* uart3 */
2085 static struct omap_hwmod dra7xx_uart3_hwmod = {
2086 .name = "uart3",
2087 .class = &dra7xx_uart_hwmod_class,
2088 .clkdm_name = "l4per_clkdm",
2089 .main_clk = "uart3_gfclk_mux",
2090 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2091 .prcm = {
2092 .omap4 = {
2093 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2094 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2095 .modulemode = MODULEMODE_SWCTRL,
2096 },
2097 },
2098 };
2099
2100 /* uart4 */
2101 static struct omap_hwmod dra7xx_uart4_hwmod = {
2102 .name = "uart4",
2103 .class = &dra7xx_uart_hwmod_class,
2104 .clkdm_name = "l4per_clkdm",
2105 .main_clk = "uart4_gfclk_mux",
2106 .flags = HWMOD_SWSUP_SIDLE_ACT,
2107 .prcm = {
2108 .omap4 = {
2109 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2110 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2111 .modulemode = MODULEMODE_SWCTRL,
2112 },
2113 },
2114 };
2115
2116 /* uart5 */
2117 static struct omap_hwmod dra7xx_uart5_hwmod = {
2118 .name = "uart5",
2119 .class = &dra7xx_uart_hwmod_class,
2120 .clkdm_name = "l4per_clkdm",
2121 .main_clk = "uart5_gfclk_mux",
2122 .flags = HWMOD_SWSUP_SIDLE_ACT,
2123 .prcm = {
2124 .omap4 = {
2125 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2126 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2127 .modulemode = MODULEMODE_SWCTRL,
2128 },
2129 },
2130 };
2131
2132 /* uart6 */
2133 static struct omap_hwmod dra7xx_uart6_hwmod = {
2134 .name = "uart6",
2135 .class = &dra7xx_uart_hwmod_class,
2136 .clkdm_name = "ipu_clkdm",
2137 .main_clk = "uart6_gfclk_mux",
2138 .flags = HWMOD_SWSUP_SIDLE_ACT,
2139 .prcm = {
2140 .omap4 = {
2141 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2142 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2143 .modulemode = MODULEMODE_SWCTRL,
2144 },
2145 },
2146 };
2147
2148 /* uart7 */
2149 static struct omap_hwmod dra7xx_uart7_hwmod = {
2150 .name = "uart7",
2151 .class = &dra7xx_uart_hwmod_class,
2152 .clkdm_name = "l4per2_clkdm",
2153 .main_clk = "uart7_gfclk_mux",
2154 .flags = HWMOD_SWSUP_SIDLE_ACT,
2155 .prcm = {
2156 .omap4 = {
2157 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2158 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2159 .modulemode = MODULEMODE_SWCTRL,
2160 },
2161 },
2162 };
2163
2164 /* uart8 */
2165 static struct omap_hwmod dra7xx_uart8_hwmod = {
2166 .name = "uart8",
2167 .class = &dra7xx_uart_hwmod_class,
2168 .clkdm_name = "l4per2_clkdm",
2169 .main_clk = "uart8_gfclk_mux",
2170 .flags = HWMOD_SWSUP_SIDLE_ACT,
2171 .prcm = {
2172 .omap4 = {
2173 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2174 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2175 .modulemode = MODULEMODE_SWCTRL,
2176 },
2177 },
2178 };
2179
2180 /* uart9 */
2181 static struct omap_hwmod dra7xx_uart9_hwmod = {
2182 .name = "uart9",
2183 .class = &dra7xx_uart_hwmod_class,
2184 .clkdm_name = "l4per2_clkdm",
2185 .main_clk = "uart9_gfclk_mux",
2186 .flags = HWMOD_SWSUP_SIDLE_ACT,
2187 .prcm = {
2188 .omap4 = {
2189 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2190 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2191 .modulemode = MODULEMODE_SWCTRL,
2192 },
2193 },
2194 };
2195
2196 /* uart10 */
2197 static struct omap_hwmod dra7xx_uart10_hwmod = {
2198 .name = "uart10",
2199 .class = &dra7xx_uart_hwmod_class,
2200 .clkdm_name = "wkupaon_clkdm",
2201 .main_clk = "uart10_gfclk_mux",
2202 .flags = HWMOD_SWSUP_SIDLE_ACT,
2203 .prcm = {
2204 .omap4 = {
2205 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2206 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2207 .modulemode = MODULEMODE_SWCTRL,
2208 },
2209 },
2210 };
2211
2212 /*
2213 * 'usb_otg_ss' class
2214 *
2215 */
2216
2217 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2218 .rev_offs = 0x0000,
2219 .sysc_offs = 0x0010,
2220 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2221 SYSC_HAS_SIDLEMODE),
2222 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2223 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2224 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2225 .sysc_fields = &omap_hwmod_sysc_type2,
2226 };
2227
2228 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2229 .name = "usb_otg_ss",
2230 .sysc = &dra7xx_usb_otg_ss_sysc,
2231 };
2232
2233 /* usb_otg_ss1 */
2234 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2235 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2236 };
2237
2238 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2239 .name = "usb_otg_ss1",
2240 .class = &dra7xx_usb_otg_ss_hwmod_class,
2241 .clkdm_name = "l3init_clkdm",
2242 .main_clk = "dpll_core_h13x2_ck",
2243 .prcm = {
2244 .omap4 = {
2245 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2246 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2247 .modulemode = MODULEMODE_HWCTRL,
2248 },
2249 },
2250 .opt_clks = usb_otg_ss1_opt_clks,
2251 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2252 };
2253
2254 /* usb_otg_ss2 */
2255 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2256 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2257 };
2258
2259 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2260 .name = "usb_otg_ss2",
2261 .class = &dra7xx_usb_otg_ss_hwmod_class,
2262 .clkdm_name = "l3init_clkdm",
2263 .main_clk = "dpll_core_h13x2_ck",
2264 .prcm = {
2265 .omap4 = {
2266 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2267 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2268 .modulemode = MODULEMODE_HWCTRL,
2269 },
2270 },
2271 .opt_clks = usb_otg_ss2_opt_clks,
2272 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2273 };
2274
2275 /* usb_otg_ss3 */
2276 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2277 .name = "usb_otg_ss3",
2278 .class = &dra7xx_usb_otg_ss_hwmod_class,
2279 .clkdm_name = "l3init_clkdm",
2280 .main_clk = "dpll_core_h13x2_ck",
2281 .prcm = {
2282 .omap4 = {
2283 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2284 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2285 .modulemode = MODULEMODE_HWCTRL,
2286 },
2287 },
2288 };
2289
2290 /* usb_otg_ss4 */
2291 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2292 .name = "usb_otg_ss4",
2293 .class = &dra7xx_usb_otg_ss_hwmod_class,
2294 .clkdm_name = "l3init_clkdm",
2295 .main_clk = "dpll_core_h13x2_ck",
2296 .prcm = {
2297 .omap4 = {
2298 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2299 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2300 .modulemode = MODULEMODE_HWCTRL,
2301 },
2302 },
2303 };
2304
2305 /*
2306 * 'vcp' class
2307 *
2308 */
2309
2310 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2311 .name = "vcp",
2312 };
2313
2314 /* vcp1 */
2315 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2316 .name = "vcp1",
2317 .class = &dra7xx_vcp_hwmod_class,
2318 .clkdm_name = "l3main1_clkdm",
2319 .main_clk = "l3_iclk_div",
2320 .prcm = {
2321 .omap4 = {
2322 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2323 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2324 },
2325 },
2326 };
2327
2328 /* vcp2 */
2329 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2330 .name = "vcp2",
2331 .class = &dra7xx_vcp_hwmod_class,
2332 .clkdm_name = "l3main1_clkdm",
2333 .main_clk = "l3_iclk_div",
2334 .prcm = {
2335 .omap4 = {
2336 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2337 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2338 },
2339 },
2340 };
2341
2342 /*
2343 * 'wd_timer' class
2344 *
2345 */
2346
2347 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2348 .rev_offs = 0x0000,
2349 .sysc_offs = 0x0010,
2350 .syss_offs = 0x0014,
2351 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2352 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2353 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2354 SIDLE_SMART_WKUP),
2355 .sysc_fields = &omap_hwmod_sysc_type1,
2356 };
2357
2358 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2359 .name = "wd_timer",
2360 .sysc = &dra7xx_wd_timer_sysc,
2361 .pre_shutdown = &omap2_wd_timer_disable,
2362 .reset = &omap2_wd_timer_reset,
2363 };
2364
2365 /* wd_timer2 */
2366 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2367 .name = "wd_timer2",
2368 .class = &dra7xx_wd_timer_hwmod_class,
2369 .clkdm_name = "wkupaon_clkdm",
2370 .main_clk = "sys_32k_ck",
2371 .prcm = {
2372 .omap4 = {
2373 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2374 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2375 .modulemode = MODULEMODE_SWCTRL,
2376 },
2377 },
2378 };
2379
2380
2381 /*
2382 * Interfaces
2383 */
2384
2385 /* l3_main_1 -> dmm */
2386 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2387 .master = &dra7xx_l3_main_1_hwmod,
2388 .slave = &dra7xx_dmm_hwmod,
2389 .clk = "l3_iclk_div",
2390 .user = OCP_USER_SDMA,
2391 };
2392
2393 /* l3_main_2 -> l3_instr */
2394 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2395 .master = &dra7xx_l3_main_2_hwmod,
2396 .slave = &dra7xx_l3_instr_hwmod,
2397 .clk = "l3_iclk_div",
2398 .user = OCP_USER_MPU | OCP_USER_SDMA,
2399 };
2400
2401 /* l4_cfg -> l3_main_1 */
2402 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2403 .master = &dra7xx_l4_cfg_hwmod,
2404 .slave = &dra7xx_l3_main_1_hwmod,
2405 .clk = "l3_iclk_div",
2406 .user = OCP_USER_MPU | OCP_USER_SDMA,
2407 };
2408
2409 /* mpu -> l3_main_1 */
2410 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2411 .master = &dra7xx_mpu_hwmod,
2412 .slave = &dra7xx_l3_main_1_hwmod,
2413 .clk = "l3_iclk_div",
2414 .user = OCP_USER_MPU,
2415 };
2416
2417 /* l3_main_1 -> l3_main_2 */
2418 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2419 .master = &dra7xx_l3_main_1_hwmod,
2420 .slave = &dra7xx_l3_main_2_hwmod,
2421 .clk = "l3_iclk_div",
2422 .user = OCP_USER_MPU,
2423 };
2424
2425 /* l4_cfg -> l3_main_2 */
2426 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2427 .master = &dra7xx_l4_cfg_hwmod,
2428 .slave = &dra7xx_l3_main_2_hwmod,
2429 .clk = "l3_iclk_div",
2430 .user = OCP_USER_MPU | OCP_USER_SDMA,
2431 };
2432
2433 /* l3_main_1 -> l4_cfg */
2434 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2435 .master = &dra7xx_l3_main_1_hwmod,
2436 .slave = &dra7xx_l4_cfg_hwmod,
2437 .clk = "l3_iclk_div",
2438 .user = OCP_USER_MPU | OCP_USER_SDMA,
2439 };
2440
2441 /* l3_main_1 -> l4_per1 */
2442 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2443 .master = &dra7xx_l3_main_1_hwmod,
2444 .slave = &dra7xx_l4_per1_hwmod,
2445 .clk = "l3_iclk_div",
2446 .user = OCP_USER_MPU | OCP_USER_SDMA,
2447 };
2448
2449 /* l3_main_1 -> l4_per2 */
2450 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2451 .master = &dra7xx_l3_main_1_hwmod,
2452 .slave = &dra7xx_l4_per2_hwmod,
2453 .clk = "l3_iclk_div",
2454 .user = OCP_USER_MPU | OCP_USER_SDMA,
2455 };
2456
2457 /* l3_main_1 -> l4_per3 */
2458 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2459 .master = &dra7xx_l3_main_1_hwmod,
2460 .slave = &dra7xx_l4_per3_hwmod,
2461 .clk = "l3_iclk_div",
2462 .user = OCP_USER_MPU | OCP_USER_SDMA,
2463 };
2464
2465 /* l3_main_1 -> l4_wkup */
2466 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2467 .master = &dra7xx_l3_main_1_hwmod,
2468 .slave = &dra7xx_l4_wkup_hwmod,
2469 .clk = "wkupaon_iclk_mux",
2470 .user = OCP_USER_MPU | OCP_USER_SDMA,
2471 };
2472
2473 /* l4_per2 -> atl */
2474 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2475 .master = &dra7xx_l4_per2_hwmod,
2476 .slave = &dra7xx_atl_hwmod,
2477 .clk = "l3_iclk_div",
2478 .user = OCP_USER_MPU | OCP_USER_SDMA,
2479 };
2480
2481 /* l3_main_1 -> bb2d */
2482 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2483 .master = &dra7xx_l3_main_1_hwmod,
2484 .slave = &dra7xx_bb2d_hwmod,
2485 .clk = "l3_iclk_div",
2486 .user = OCP_USER_MPU | OCP_USER_SDMA,
2487 };
2488
2489 /* l4_wkup -> counter_32k */
2490 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2491 .master = &dra7xx_l4_wkup_hwmod,
2492 .slave = &dra7xx_counter_32k_hwmod,
2493 .clk = "wkupaon_iclk_mux",
2494 .user = OCP_USER_MPU | OCP_USER_SDMA,
2495 };
2496
2497 /* l4_wkup -> ctrl_module_wkup */
2498 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2499 .master = &dra7xx_l4_wkup_hwmod,
2500 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2501 .clk = "wkupaon_iclk_mux",
2502 .user = OCP_USER_MPU | OCP_USER_SDMA,
2503 };
2504
2505 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2506 .master = &dra7xx_l4_per2_hwmod,
2507 .slave = &dra7xx_gmac_hwmod,
2508 .clk = "dpll_gmac_ck",
2509 .user = OCP_USER_MPU,
2510 };
2511
2512 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2513 .master = &dra7xx_gmac_hwmod,
2514 .slave = &dra7xx_mdio_hwmod,
2515 .user = OCP_USER_MPU,
2516 };
2517
2518 /* l4_wkup -> dcan1 */
2519 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2520 .master = &dra7xx_l4_wkup_hwmod,
2521 .slave = &dra7xx_dcan1_hwmod,
2522 .clk = "wkupaon_iclk_mux",
2523 .user = OCP_USER_MPU | OCP_USER_SDMA,
2524 };
2525
2526 /* l4_per2 -> dcan2 */
2527 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2528 .master = &dra7xx_l4_per2_hwmod,
2529 .slave = &dra7xx_dcan2_hwmod,
2530 .clk = "l3_iclk_div",
2531 .user = OCP_USER_MPU | OCP_USER_SDMA,
2532 };
2533
2534 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2535 {
2536 .pa_start = 0x4a056000,
2537 .pa_end = 0x4a056fff,
2538 .flags = ADDR_TYPE_RT
2539 },
2540 { }
2541 };
2542
2543 /* l4_cfg -> dma_system */
2544 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2545 .master = &dra7xx_l4_cfg_hwmod,
2546 .slave = &dra7xx_dma_system_hwmod,
2547 .clk = "l3_iclk_div",
2548 .addr = dra7xx_dma_system_addrs,
2549 .user = OCP_USER_MPU | OCP_USER_SDMA,
2550 };
2551
2552 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2553 {
2554 .name = "family",
2555 .pa_start = 0x58000000,
2556 .pa_end = 0x5800007f,
2557 .flags = ADDR_TYPE_RT
2558 },
2559 };
2560
2561 /* l3_main_1 -> dss */
2562 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2563 .master = &dra7xx_l3_main_1_hwmod,
2564 .slave = &dra7xx_dss_hwmod,
2565 .clk = "l3_iclk_div",
2566 .addr = dra7xx_dss_addrs,
2567 .user = OCP_USER_MPU | OCP_USER_SDMA,
2568 };
2569
2570 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2571 {
2572 .name = "dispc",
2573 .pa_start = 0x58001000,
2574 .pa_end = 0x58001fff,
2575 .flags = ADDR_TYPE_RT
2576 },
2577 };
2578
2579 /* l3_main_1 -> dispc */
2580 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2581 .master = &dra7xx_l3_main_1_hwmod,
2582 .slave = &dra7xx_dss_dispc_hwmod,
2583 .clk = "l3_iclk_div",
2584 .addr = dra7xx_dss_dispc_addrs,
2585 .user = OCP_USER_MPU | OCP_USER_SDMA,
2586 };
2587
2588 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2589 {
2590 .name = "hdmi_wp",
2591 .pa_start = 0x58040000,
2592 .pa_end = 0x580400ff,
2593 .flags = ADDR_TYPE_RT
2594 },
2595 { }
2596 };
2597
2598 /* l3_main_1 -> dispc */
2599 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2600 .master = &dra7xx_l3_main_1_hwmod,
2601 .slave = &dra7xx_dss_hdmi_hwmod,
2602 .clk = "l3_iclk_div",
2603 .addr = dra7xx_dss_hdmi_addrs,
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2605 };
2606
2607 /* l4_per2 -> mcasp3 */
2608 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2609 .master = &dra7xx_l4_per2_hwmod,
2610 .slave = &dra7xx_mcasp3_hwmod,
2611 .clk = "l4_root_clk_div",
2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613 };
2614
2615 /* l3_main_1 -> mcasp3 */
2616 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
2617 .master = &dra7xx_l3_main_1_hwmod,
2618 .slave = &dra7xx_mcasp3_hwmod,
2619 .clk = "l3_iclk_div",
2620 .user = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 /* l4_per1 -> elm */
2624 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2625 .master = &dra7xx_l4_per1_hwmod,
2626 .slave = &dra7xx_elm_hwmod,
2627 .clk = "l3_iclk_div",
2628 .user = OCP_USER_MPU | OCP_USER_SDMA,
2629 };
2630
2631 /* l4_wkup -> gpio1 */
2632 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2633 .master = &dra7xx_l4_wkup_hwmod,
2634 .slave = &dra7xx_gpio1_hwmod,
2635 .clk = "wkupaon_iclk_mux",
2636 .user = OCP_USER_MPU | OCP_USER_SDMA,
2637 };
2638
2639 /* l4_per1 -> gpio2 */
2640 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2641 .master = &dra7xx_l4_per1_hwmod,
2642 .slave = &dra7xx_gpio2_hwmod,
2643 .clk = "l3_iclk_div",
2644 .user = OCP_USER_MPU | OCP_USER_SDMA,
2645 };
2646
2647 /* l4_per1 -> gpio3 */
2648 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2649 .master = &dra7xx_l4_per1_hwmod,
2650 .slave = &dra7xx_gpio3_hwmod,
2651 .clk = "l3_iclk_div",
2652 .user = OCP_USER_MPU | OCP_USER_SDMA,
2653 };
2654
2655 /* l4_per1 -> gpio4 */
2656 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2657 .master = &dra7xx_l4_per1_hwmod,
2658 .slave = &dra7xx_gpio4_hwmod,
2659 .clk = "l3_iclk_div",
2660 .user = OCP_USER_MPU | OCP_USER_SDMA,
2661 };
2662
2663 /* l4_per1 -> gpio5 */
2664 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2665 .master = &dra7xx_l4_per1_hwmod,
2666 .slave = &dra7xx_gpio5_hwmod,
2667 .clk = "l3_iclk_div",
2668 .user = OCP_USER_MPU | OCP_USER_SDMA,
2669 };
2670
2671 /* l4_per1 -> gpio6 */
2672 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2673 .master = &dra7xx_l4_per1_hwmod,
2674 .slave = &dra7xx_gpio6_hwmod,
2675 .clk = "l3_iclk_div",
2676 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677 };
2678
2679 /* l4_per1 -> gpio7 */
2680 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2681 .master = &dra7xx_l4_per1_hwmod,
2682 .slave = &dra7xx_gpio7_hwmod,
2683 .clk = "l3_iclk_div",
2684 .user = OCP_USER_MPU | OCP_USER_SDMA,
2685 };
2686
2687 /* l4_per1 -> gpio8 */
2688 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2689 .master = &dra7xx_l4_per1_hwmod,
2690 .slave = &dra7xx_gpio8_hwmod,
2691 .clk = "l3_iclk_div",
2692 .user = OCP_USER_MPU | OCP_USER_SDMA,
2693 };
2694
2695 /* l3_main_1 -> gpmc */
2696 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2697 .master = &dra7xx_l3_main_1_hwmod,
2698 .slave = &dra7xx_gpmc_hwmod,
2699 .clk = "l3_iclk_div",
2700 .user = OCP_USER_MPU | OCP_USER_SDMA,
2701 };
2702
2703 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2704 {
2705 .pa_start = 0x480b2000,
2706 .pa_end = 0x480b201f,
2707 .flags = ADDR_TYPE_RT
2708 },
2709 { }
2710 };
2711
2712 /* l4_per1 -> hdq1w */
2713 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2714 .master = &dra7xx_l4_per1_hwmod,
2715 .slave = &dra7xx_hdq1w_hwmod,
2716 .clk = "l3_iclk_div",
2717 .addr = dra7xx_hdq1w_addrs,
2718 .user = OCP_USER_MPU | OCP_USER_SDMA,
2719 };
2720
2721 /* l4_per1 -> i2c1 */
2722 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2723 .master = &dra7xx_l4_per1_hwmod,
2724 .slave = &dra7xx_i2c1_hwmod,
2725 .clk = "l3_iclk_div",
2726 .user = OCP_USER_MPU | OCP_USER_SDMA,
2727 };
2728
2729 /* l4_per1 -> i2c2 */
2730 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2731 .master = &dra7xx_l4_per1_hwmod,
2732 .slave = &dra7xx_i2c2_hwmod,
2733 .clk = "l3_iclk_div",
2734 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735 };
2736
2737 /* l4_per1 -> i2c3 */
2738 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2739 .master = &dra7xx_l4_per1_hwmod,
2740 .slave = &dra7xx_i2c3_hwmod,
2741 .clk = "l3_iclk_div",
2742 .user = OCP_USER_MPU | OCP_USER_SDMA,
2743 };
2744
2745 /* l4_per1 -> i2c4 */
2746 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2747 .master = &dra7xx_l4_per1_hwmod,
2748 .slave = &dra7xx_i2c4_hwmod,
2749 .clk = "l3_iclk_div",
2750 .user = OCP_USER_MPU | OCP_USER_SDMA,
2751 };
2752
2753 /* l4_per1 -> i2c5 */
2754 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2755 .master = &dra7xx_l4_per1_hwmod,
2756 .slave = &dra7xx_i2c5_hwmod,
2757 .clk = "l3_iclk_div",
2758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2759 };
2760
2761 /* l4_cfg -> mailbox1 */
2762 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2763 .master = &dra7xx_l4_cfg_hwmod,
2764 .slave = &dra7xx_mailbox1_hwmod,
2765 .clk = "l3_iclk_div",
2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767 };
2768
2769 /* l4_per3 -> mailbox2 */
2770 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2771 .master = &dra7xx_l4_per3_hwmod,
2772 .slave = &dra7xx_mailbox2_hwmod,
2773 .clk = "l3_iclk_div",
2774 .user = OCP_USER_MPU | OCP_USER_SDMA,
2775 };
2776
2777 /* l4_per3 -> mailbox3 */
2778 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2779 .master = &dra7xx_l4_per3_hwmod,
2780 .slave = &dra7xx_mailbox3_hwmod,
2781 .clk = "l3_iclk_div",
2782 .user = OCP_USER_MPU | OCP_USER_SDMA,
2783 };
2784
2785 /* l4_per3 -> mailbox4 */
2786 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2787 .master = &dra7xx_l4_per3_hwmod,
2788 .slave = &dra7xx_mailbox4_hwmod,
2789 .clk = "l3_iclk_div",
2790 .user = OCP_USER_MPU | OCP_USER_SDMA,
2791 };
2792
2793 /* l4_per3 -> mailbox5 */
2794 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2795 .master = &dra7xx_l4_per3_hwmod,
2796 .slave = &dra7xx_mailbox5_hwmod,
2797 .clk = "l3_iclk_div",
2798 .user = OCP_USER_MPU | OCP_USER_SDMA,
2799 };
2800
2801 /* l4_per3 -> mailbox6 */
2802 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2803 .master = &dra7xx_l4_per3_hwmod,
2804 .slave = &dra7xx_mailbox6_hwmod,
2805 .clk = "l3_iclk_div",
2806 .user = OCP_USER_MPU | OCP_USER_SDMA,
2807 };
2808
2809 /* l4_per3 -> mailbox7 */
2810 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2811 .master = &dra7xx_l4_per3_hwmod,
2812 .slave = &dra7xx_mailbox7_hwmod,
2813 .clk = "l3_iclk_div",
2814 .user = OCP_USER_MPU | OCP_USER_SDMA,
2815 };
2816
2817 /* l4_per3 -> mailbox8 */
2818 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2819 .master = &dra7xx_l4_per3_hwmod,
2820 .slave = &dra7xx_mailbox8_hwmod,
2821 .clk = "l3_iclk_div",
2822 .user = OCP_USER_MPU | OCP_USER_SDMA,
2823 };
2824
2825 /* l4_per3 -> mailbox9 */
2826 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2827 .master = &dra7xx_l4_per3_hwmod,
2828 .slave = &dra7xx_mailbox9_hwmod,
2829 .clk = "l3_iclk_div",
2830 .user = OCP_USER_MPU | OCP_USER_SDMA,
2831 };
2832
2833 /* l4_per3 -> mailbox10 */
2834 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2835 .master = &dra7xx_l4_per3_hwmod,
2836 .slave = &dra7xx_mailbox10_hwmod,
2837 .clk = "l3_iclk_div",
2838 .user = OCP_USER_MPU | OCP_USER_SDMA,
2839 };
2840
2841 /* l4_per3 -> mailbox11 */
2842 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2843 .master = &dra7xx_l4_per3_hwmod,
2844 .slave = &dra7xx_mailbox11_hwmod,
2845 .clk = "l3_iclk_div",
2846 .user = OCP_USER_MPU | OCP_USER_SDMA,
2847 };
2848
2849 /* l4_per3 -> mailbox12 */
2850 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2851 .master = &dra7xx_l4_per3_hwmod,
2852 .slave = &dra7xx_mailbox12_hwmod,
2853 .clk = "l3_iclk_div",
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855 };
2856
2857 /* l4_per3 -> mailbox13 */
2858 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2859 .master = &dra7xx_l4_per3_hwmod,
2860 .slave = &dra7xx_mailbox13_hwmod,
2861 .clk = "l3_iclk_div",
2862 .user = OCP_USER_MPU | OCP_USER_SDMA,
2863 };
2864
2865 /* l4_per1 -> mcspi1 */
2866 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2867 .master = &dra7xx_l4_per1_hwmod,
2868 .slave = &dra7xx_mcspi1_hwmod,
2869 .clk = "l3_iclk_div",
2870 .user = OCP_USER_MPU | OCP_USER_SDMA,
2871 };
2872
2873 /* l4_per1 -> mcspi2 */
2874 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2875 .master = &dra7xx_l4_per1_hwmod,
2876 .slave = &dra7xx_mcspi2_hwmod,
2877 .clk = "l3_iclk_div",
2878 .user = OCP_USER_MPU | OCP_USER_SDMA,
2879 };
2880
2881 /* l4_per1 -> mcspi3 */
2882 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2883 .master = &dra7xx_l4_per1_hwmod,
2884 .slave = &dra7xx_mcspi3_hwmod,
2885 .clk = "l3_iclk_div",
2886 .user = OCP_USER_MPU | OCP_USER_SDMA,
2887 };
2888
2889 /* l4_per1 -> mcspi4 */
2890 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2891 .master = &dra7xx_l4_per1_hwmod,
2892 .slave = &dra7xx_mcspi4_hwmod,
2893 .clk = "l3_iclk_div",
2894 .user = OCP_USER_MPU | OCP_USER_SDMA,
2895 };
2896
2897 /* l4_per1 -> mmc1 */
2898 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2899 .master = &dra7xx_l4_per1_hwmod,
2900 .slave = &dra7xx_mmc1_hwmod,
2901 .clk = "l3_iclk_div",
2902 .user = OCP_USER_MPU | OCP_USER_SDMA,
2903 };
2904
2905 /* l4_per1 -> mmc2 */
2906 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2907 .master = &dra7xx_l4_per1_hwmod,
2908 .slave = &dra7xx_mmc2_hwmod,
2909 .clk = "l3_iclk_div",
2910 .user = OCP_USER_MPU | OCP_USER_SDMA,
2911 };
2912
2913 /* l4_per1 -> mmc3 */
2914 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2915 .master = &dra7xx_l4_per1_hwmod,
2916 .slave = &dra7xx_mmc3_hwmod,
2917 .clk = "l3_iclk_div",
2918 .user = OCP_USER_MPU | OCP_USER_SDMA,
2919 };
2920
2921 /* l4_per1 -> mmc4 */
2922 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2923 .master = &dra7xx_l4_per1_hwmod,
2924 .slave = &dra7xx_mmc4_hwmod,
2925 .clk = "l3_iclk_div",
2926 .user = OCP_USER_MPU | OCP_USER_SDMA,
2927 };
2928
2929 /* l4_cfg -> mpu */
2930 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2931 .master = &dra7xx_l4_cfg_hwmod,
2932 .slave = &dra7xx_mpu_hwmod,
2933 .clk = "l3_iclk_div",
2934 .user = OCP_USER_MPU | OCP_USER_SDMA,
2935 };
2936
2937 /* l4_cfg -> ocp2scp1 */
2938 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2939 .master = &dra7xx_l4_cfg_hwmod,
2940 .slave = &dra7xx_ocp2scp1_hwmod,
2941 .clk = "l4_root_clk_div",
2942 .user = OCP_USER_MPU | OCP_USER_SDMA,
2943 };
2944
2945 /* l4_cfg -> ocp2scp3 */
2946 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2947 .master = &dra7xx_l4_cfg_hwmod,
2948 .slave = &dra7xx_ocp2scp3_hwmod,
2949 .clk = "l4_root_clk_div",
2950 .user = OCP_USER_MPU | OCP_USER_SDMA,
2951 };
2952
2953 /* l3_main_1 -> pciess1 */
2954 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2955 .master = &dra7xx_l3_main_1_hwmod,
2956 .slave = &dra7xx_pciess1_hwmod,
2957 .clk = "l3_iclk_div",
2958 .user = OCP_USER_MPU | OCP_USER_SDMA,
2959 };
2960
2961 /* l4_cfg -> pciess1 */
2962 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2963 .master = &dra7xx_l4_cfg_hwmod,
2964 .slave = &dra7xx_pciess1_hwmod,
2965 .clk = "l4_root_clk_div",
2966 .user = OCP_USER_MPU | OCP_USER_SDMA,
2967 };
2968
2969 /* l3_main_1 -> pciess2 */
2970 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2971 .master = &dra7xx_l3_main_1_hwmod,
2972 .slave = &dra7xx_pciess2_hwmod,
2973 .clk = "l3_iclk_div",
2974 .user = OCP_USER_MPU | OCP_USER_SDMA,
2975 };
2976
2977 /* l4_cfg -> pciess2 */
2978 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2979 .master = &dra7xx_l4_cfg_hwmod,
2980 .slave = &dra7xx_pciess2_hwmod,
2981 .clk = "l4_root_clk_div",
2982 .user = OCP_USER_MPU | OCP_USER_SDMA,
2983 };
2984
2985 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2986 {
2987 .pa_start = 0x4b300000,
2988 .pa_end = 0x4b30007f,
2989 .flags = ADDR_TYPE_RT
2990 },
2991 { }
2992 };
2993
2994 /* l3_main_1 -> qspi */
2995 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2996 .master = &dra7xx_l3_main_1_hwmod,
2997 .slave = &dra7xx_qspi_hwmod,
2998 .clk = "l3_iclk_div",
2999 .addr = dra7xx_qspi_addrs,
3000 .user = OCP_USER_MPU | OCP_USER_SDMA,
3001 };
3002
3003 /* l4_per3 -> rtcss */
3004 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3005 .master = &dra7xx_l4_per3_hwmod,
3006 .slave = &dra7xx_rtcss_hwmod,
3007 .clk = "l4_root_clk_div",
3008 .user = OCP_USER_MPU | OCP_USER_SDMA,
3009 };
3010
3011 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3012 {
3013 .name = "sysc",
3014 .pa_start = 0x4a141100,
3015 .pa_end = 0x4a141107,
3016 .flags = ADDR_TYPE_RT
3017 },
3018 { }
3019 };
3020
3021 /* l4_cfg -> sata */
3022 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3023 .master = &dra7xx_l4_cfg_hwmod,
3024 .slave = &dra7xx_sata_hwmod,
3025 .clk = "l3_iclk_div",
3026 .addr = dra7xx_sata_addrs,
3027 .user = OCP_USER_MPU | OCP_USER_SDMA,
3028 };
3029
3030 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3031 {
3032 .pa_start = 0x4a0dd000,
3033 .pa_end = 0x4a0dd07f,
3034 .flags = ADDR_TYPE_RT
3035 },
3036 { }
3037 };
3038
3039 /* l4_cfg -> smartreflex_core */
3040 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3041 .master = &dra7xx_l4_cfg_hwmod,
3042 .slave = &dra7xx_smartreflex_core_hwmod,
3043 .clk = "l4_root_clk_div",
3044 .addr = dra7xx_smartreflex_core_addrs,
3045 .user = OCP_USER_MPU | OCP_USER_SDMA,
3046 };
3047
3048 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3049 {
3050 .pa_start = 0x4a0d9000,
3051 .pa_end = 0x4a0d907f,
3052 .flags = ADDR_TYPE_RT
3053 },
3054 { }
3055 };
3056
3057 /* l4_cfg -> smartreflex_mpu */
3058 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3059 .master = &dra7xx_l4_cfg_hwmod,
3060 .slave = &dra7xx_smartreflex_mpu_hwmod,
3061 .clk = "l4_root_clk_div",
3062 .addr = dra7xx_smartreflex_mpu_addrs,
3063 .user = OCP_USER_MPU | OCP_USER_SDMA,
3064 };
3065
3066 /* l4_cfg -> spinlock */
3067 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3068 .master = &dra7xx_l4_cfg_hwmod,
3069 .slave = &dra7xx_spinlock_hwmod,
3070 .clk = "l3_iclk_div",
3071 .user = OCP_USER_MPU | OCP_USER_SDMA,
3072 };
3073
3074 /* l4_wkup -> timer1 */
3075 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3076 .master = &dra7xx_l4_wkup_hwmod,
3077 .slave = &dra7xx_timer1_hwmod,
3078 .clk = "wkupaon_iclk_mux",
3079 .user = OCP_USER_MPU | OCP_USER_SDMA,
3080 };
3081
3082 /* l4_per1 -> timer2 */
3083 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3084 .master = &dra7xx_l4_per1_hwmod,
3085 .slave = &dra7xx_timer2_hwmod,
3086 .clk = "l3_iclk_div",
3087 .user = OCP_USER_MPU | OCP_USER_SDMA,
3088 };
3089
3090 /* l4_per1 -> timer3 */
3091 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3092 .master = &dra7xx_l4_per1_hwmod,
3093 .slave = &dra7xx_timer3_hwmod,
3094 .clk = "l3_iclk_div",
3095 .user = OCP_USER_MPU | OCP_USER_SDMA,
3096 };
3097
3098 /* l4_per1 -> timer4 */
3099 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3100 .master = &dra7xx_l4_per1_hwmod,
3101 .slave = &dra7xx_timer4_hwmod,
3102 .clk = "l3_iclk_div",
3103 .user = OCP_USER_MPU | OCP_USER_SDMA,
3104 };
3105
3106 /* l4_per3 -> timer5 */
3107 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3108 .master = &dra7xx_l4_per3_hwmod,
3109 .slave = &dra7xx_timer5_hwmod,
3110 .clk = "l3_iclk_div",
3111 .user = OCP_USER_MPU | OCP_USER_SDMA,
3112 };
3113
3114 /* l4_per3 -> timer6 */
3115 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3116 .master = &dra7xx_l4_per3_hwmod,
3117 .slave = &dra7xx_timer6_hwmod,
3118 .clk = "l3_iclk_div",
3119 .user = OCP_USER_MPU | OCP_USER_SDMA,
3120 };
3121
3122 /* l4_per3 -> timer7 */
3123 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3124 .master = &dra7xx_l4_per3_hwmod,
3125 .slave = &dra7xx_timer7_hwmod,
3126 .clk = "l3_iclk_div",
3127 .user = OCP_USER_MPU | OCP_USER_SDMA,
3128 };
3129
3130 /* l4_per3 -> timer8 */
3131 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3132 .master = &dra7xx_l4_per3_hwmod,
3133 .slave = &dra7xx_timer8_hwmod,
3134 .clk = "l3_iclk_div",
3135 .user = OCP_USER_MPU | OCP_USER_SDMA,
3136 };
3137
3138 /* l4_per1 -> timer9 */
3139 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3140 .master = &dra7xx_l4_per1_hwmod,
3141 .slave = &dra7xx_timer9_hwmod,
3142 .clk = "l3_iclk_div",
3143 .user = OCP_USER_MPU | OCP_USER_SDMA,
3144 };
3145
3146 /* l4_per1 -> timer10 */
3147 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3148 .master = &dra7xx_l4_per1_hwmod,
3149 .slave = &dra7xx_timer10_hwmod,
3150 .clk = "l3_iclk_div",
3151 .user = OCP_USER_MPU | OCP_USER_SDMA,
3152 };
3153
3154 /* l4_per1 -> timer11 */
3155 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3156 .master = &dra7xx_l4_per1_hwmod,
3157 .slave = &dra7xx_timer11_hwmod,
3158 .clk = "l3_iclk_div",
3159 .user = OCP_USER_MPU | OCP_USER_SDMA,
3160 };
3161
3162 /* l4_per3 -> timer13 */
3163 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3164 .master = &dra7xx_l4_per3_hwmod,
3165 .slave = &dra7xx_timer13_hwmod,
3166 .clk = "l3_iclk_div",
3167 .user = OCP_USER_MPU | OCP_USER_SDMA,
3168 };
3169
3170 /* l4_per3 -> timer14 */
3171 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3172 .master = &dra7xx_l4_per3_hwmod,
3173 .slave = &dra7xx_timer14_hwmod,
3174 .clk = "l3_iclk_div",
3175 .user = OCP_USER_MPU | OCP_USER_SDMA,
3176 };
3177
3178 /* l4_per3 -> timer15 */
3179 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3180 .master = &dra7xx_l4_per3_hwmod,
3181 .slave = &dra7xx_timer15_hwmod,
3182 .clk = "l3_iclk_div",
3183 .user = OCP_USER_MPU | OCP_USER_SDMA,
3184 };
3185
3186 /* l4_per3 -> timer16 */
3187 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3188 .master = &dra7xx_l4_per3_hwmod,
3189 .slave = &dra7xx_timer16_hwmod,
3190 .clk = "l3_iclk_div",
3191 .user = OCP_USER_MPU | OCP_USER_SDMA,
3192 };
3193
3194 /* l4_per1 -> uart1 */
3195 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3196 .master = &dra7xx_l4_per1_hwmod,
3197 .slave = &dra7xx_uart1_hwmod,
3198 .clk = "l3_iclk_div",
3199 .user = OCP_USER_MPU | OCP_USER_SDMA,
3200 };
3201
3202 /* l4_per1 -> uart2 */
3203 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3204 .master = &dra7xx_l4_per1_hwmod,
3205 .slave = &dra7xx_uart2_hwmod,
3206 .clk = "l3_iclk_div",
3207 .user = OCP_USER_MPU | OCP_USER_SDMA,
3208 };
3209
3210 /* l4_per1 -> uart3 */
3211 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3212 .master = &dra7xx_l4_per1_hwmod,
3213 .slave = &dra7xx_uart3_hwmod,
3214 .clk = "l3_iclk_div",
3215 .user = OCP_USER_MPU | OCP_USER_SDMA,
3216 };
3217
3218 /* l4_per1 -> uart4 */
3219 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3220 .master = &dra7xx_l4_per1_hwmod,
3221 .slave = &dra7xx_uart4_hwmod,
3222 .clk = "l3_iclk_div",
3223 .user = OCP_USER_MPU | OCP_USER_SDMA,
3224 };
3225
3226 /* l4_per1 -> uart5 */
3227 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3228 .master = &dra7xx_l4_per1_hwmod,
3229 .slave = &dra7xx_uart5_hwmod,
3230 .clk = "l3_iclk_div",
3231 .user = OCP_USER_MPU | OCP_USER_SDMA,
3232 };
3233
3234 /* l4_per1 -> uart6 */
3235 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3236 .master = &dra7xx_l4_per1_hwmod,
3237 .slave = &dra7xx_uart6_hwmod,
3238 .clk = "l3_iclk_div",
3239 .user = OCP_USER_MPU | OCP_USER_SDMA,
3240 };
3241
3242 /* l4_per2 -> uart7 */
3243 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3244 .master = &dra7xx_l4_per2_hwmod,
3245 .slave = &dra7xx_uart7_hwmod,
3246 .clk = "l3_iclk_div",
3247 .user = OCP_USER_MPU | OCP_USER_SDMA,
3248 };
3249
3250 /* l4_per2 -> uart8 */
3251 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3252 .master = &dra7xx_l4_per2_hwmod,
3253 .slave = &dra7xx_uart8_hwmod,
3254 .clk = "l3_iclk_div",
3255 .user = OCP_USER_MPU | OCP_USER_SDMA,
3256 };
3257
3258 /* l4_per2 -> uart9 */
3259 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3260 .master = &dra7xx_l4_per2_hwmod,
3261 .slave = &dra7xx_uart9_hwmod,
3262 .clk = "l3_iclk_div",
3263 .user = OCP_USER_MPU | OCP_USER_SDMA,
3264 };
3265
3266 /* l4_wkup -> uart10 */
3267 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3268 .master = &dra7xx_l4_wkup_hwmod,
3269 .slave = &dra7xx_uart10_hwmod,
3270 .clk = "wkupaon_iclk_mux",
3271 .user = OCP_USER_MPU | OCP_USER_SDMA,
3272 };
3273
3274 /* l4_per3 -> usb_otg_ss1 */
3275 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3276 .master = &dra7xx_l4_per3_hwmod,
3277 .slave = &dra7xx_usb_otg_ss1_hwmod,
3278 .clk = "dpll_core_h13x2_ck",
3279 .user = OCP_USER_MPU | OCP_USER_SDMA,
3280 };
3281
3282 /* l4_per3 -> usb_otg_ss2 */
3283 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3284 .master = &dra7xx_l4_per3_hwmod,
3285 .slave = &dra7xx_usb_otg_ss2_hwmod,
3286 .clk = "dpll_core_h13x2_ck",
3287 .user = OCP_USER_MPU | OCP_USER_SDMA,
3288 };
3289
3290 /* l4_per3 -> usb_otg_ss3 */
3291 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3292 .master = &dra7xx_l4_per3_hwmod,
3293 .slave = &dra7xx_usb_otg_ss3_hwmod,
3294 .clk = "dpll_core_h13x2_ck",
3295 .user = OCP_USER_MPU | OCP_USER_SDMA,
3296 };
3297
3298 /* l4_per3 -> usb_otg_ss4 */
3299 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3300 .master = &dra7xx_l4_per3_hwmod,
3301 .slave = &dra7xx_usb_otg_ss4_hwmod,
3302 .clk = "dpll_core_h13x2_ck",
3303 .user = OCP_USER_MPU | OCP_USER_SDMA,
3304 };
3305
3306 /* l3_main_1 -> vcp1 */
3307 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3308 .master = &dra7xx_l3_main_1_hwmod,
3309 .slave = &dra7xx_vcp1_hwmod,
3310 .clk = "l3_iclk_div",
3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3313
3314 /* l4_per2 -> vcp1 */
3315 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3316 .master = &dra7xx_l4_per2_hwmod,
3317 .slave = &dra7xx_vcp1_hwmod,
3318 .clk = "l3_iclk_div",
3319 .user = OCP_USER_MPU | OCP_USER_SDMA,
3320 };
3321
3322 /* l3_main_1 -> vcp2 */
3323 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3324 .master = &dra7xx_l3_main_1_hwmod,
3325 .slave = &dra7xx_vcp2_hwmod,
3326 .clk = "l3_iclk_div",
3327 .user = OCP_USER_MPU | OCP_USER_SDMA,
3328 };
3329
3330 /* l4_per2 -> vcp2 */
3331 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3332 .master = &dra7xx_l4_per2_hwmod,
3333 .slave = &dra7xx_vcp2_hwmod,
3334 .clk = "l3_iclk_div",
3335 .user = OCP_USER_MPU | OCP_USER_SDMA,
3336 };
3337
3338 /* l4_wkup -> wd_timer2 */
3339 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3340 .master = &dra7xx_l4_wkup_hwmod,
3341 .slave = &dra7xx_wd_timer2_hwmod,
3342 .clk = "wkupaon_iclk_mux",
3343 .user = OCP_USER_MPU | OCP_USER_SDMA,
3344 };
3345
3346 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3347 &dra7xx_l3_main_1__dmm,
3348 &dra7xx_l3_main_2__l3_instr,
3349 &dra7xx_l4_cfg__l3_main_1,
3350 &dra7xx_mpu__l3_main_1,
3351 &dra7xx_l3_main_1__l3_main_2,
3352 &dra7xx_l4_cfg__l3_main_2,
3353 &dra7xx_l3_main_1__l4_cfg,
3354 &dra7xx_l3_main_1__l4_per1,
3355 &dra7xx_l3_main_1__l4_per2,
3356 &dra7xx_l3_main_1__l4_per3,
3357 &dra7xx_l3_main_1__l4_wkup,
3358 &dra7xx_l4_per2__atl,
3359 &dra7xx_l3_main_1__bb2d,
3360 &dra7xx_l4_wkup__counter_32k,
3361 &dra7xx_l4_wkup__ctrl_module_wkup,
3362 &dra7xx_l4_wkup__dcan1,
3363 &dra7xx_l4_per2__dcan2,
3364 &dra7xx_l4_per2__cpgmac0,
3365 &dra7xx_l4_per2__mcasp3,
3366 &dra7xx_l3_main_1__mcasp3,
3367 &dra7xx_gmac__mdio,
3368 &dra7xx_l4_cfg__dma_system,
3369 &dra7xx_l3_main_1__dss,
3370 &dra7xx_l3_main_1__dispc,
3371 &dra7xx_l3_main_1__hdmi,
3372 &dra7xx_l4_per1__elm,
3373 &dra7xx_l4_wkup__gpio1,
3374 &dra7xx_l4_per1__gpio2,
3375 &dra7xx_l4_per1__gpio3,
3376 &dra7xx_l4_per1__gpio4,
3377 &dra7xx_l4_per1__gpio5,
3378 &dra7xx_l4_per1__gpio6,
3379 &dra7xx_l4_per1__gpio7,
3380 &dra7xx_l4_per1__gpio8,
3381 &dra7xx_l3_main_1__gpmc,
3382 &dra7xx_l4_per1__hdq1w,
3383 &dra7xx_l4_per1__i2c1,
3384 &dra7xx_l4_per1__i2c2,
3385 &dra7xx_l4_per1__i2c3,
3386 &dra7xx_l4_per1__i2c4,
3387 &dra7xx_l4_per1__i2c5,
3388 &dra7xx_l4_cfg__mailbox1,
3389 &dra7xx_l4_per3__mailbox2,
3390 &dra7xx_l4_per3__mailbox3,
3391 &dra7xx_l4_per3__mailbox4,
3392 &dra7xx_l4_per3__mailbox5,
3393 &dra7xx_l4_per3__mailbox6,
3394 &dra7xx_l4_per3__mailbox7,
3395 &dra7xx_l4_per3__mailbox8,
3396 &dra7xx_l4_per3__mailbox9,
3397 &dra7xx_l4_per3__mailbox10,
3398 &dra7xx_l4_per3__mailbox11,
3399 &dra7xx_l4_per3__mailbox12,
3400 &dra7xx_l4_per3__mailbox13,
3401 &dra7xx_l4_per1__mcspi1,
3402 &dra7xx_l4_per1__mcspi2,
3403 &dra7xx_l4_per1__mcspi3,
3404 &dra7xx_l4_per1__mcspi4,
3405 &dra7xx_l4_per1__mmc1,
3406 &dra7xx_l4_per1__mmc2,
3407 &dra7xx_l4_per1__mmc3,
3408 &dra7xx_l4_per1__mmc4,
3409 &dra7xx_l4_cfg__mpu,
3410 &dra7xx_l4_cfg__ocp2scp1,
3411 &dra7xx_l4_cfg__ocp2scp3,
3412 &dra7xx_l3_main_1__pciess1,
3413 &dra7xx_l4_cfg__pciess1,
3414 &dra7xx_l3_main_1__pciess2,
3415 &dra7xx_l4_cfg__pciess2,
3416 &dra7xx_l3_main_1__qspi,
3417 &dra7xx_l4_per3__rtcss,
3418 &dra7xx_l4_cfg__sata,
3419 &dra7xx_l4_cfg__smartreflex_core,
3420 &dra7xx_l4_cfg__smartreflex_mpu,
3421 &dra7xx_l4_cfg__spinlock,
3422 &dra7xx_l4_wkup__timer1,
3423 &dra7xx_l4_per1__timer2,
3424 &dra7xx_l4_per1__timer3,
3425 &dra7xx_l4_per1__timer4,
3426 &dra7xx_l4_per3__timer5,
3427 &dra7xx_l4_per3__timer6,
3428 &dra7xx_l4_per3__timer7,
3429 &dra7xx_l4_per3__timer8,
3430 &dra7xx_l4_per1__timer9,
3431 &dra7xx_l4_per1__timer10,
3432 &dra7xx_l4_per1__timer11,
3433 &dra7xx_l4_per3__timer13,
3434 &dra7xx_l4_per3__timer14,
3435 &dra7xx_l4_per3__timer15,
3436 &dra7xx_l4_per3__timer16,
3437 &dra7xx_l4_per1__uart1,
3438 &dra7xx_l4_per1__uart2,
3439 &dra7xx_l4_per1__uart3,
3440 &dra7xx_l4_per1__uart4,
3441 &dra7xx_l4_per1__uart5,
3442 &dra7xx_l4_per1__uart6,
3443 &dra7xx_l4_per2__uart7,
3444 &dra7xx_l4_per2__uart8,
3445 &dra7xx_l4_per2__uart9,
3446 &dra7xx_l4_wkup__uart10,
3447 &dra7xx_l4_per3__usb_otg_ss1,
3448 &dra7xx_l4_per3__usb_otg_ss2,
3449 &dra7xx_l4_per3__usb_otg_ss3,
3450 &dra7xx_l3_main_1__vcp1,
3451 &dra7xx_l4_per2__vcp1,
3452 &dra7xx_l3_main_1__vcp2,
3453 &dra7xx_l4_per2__vcp2,
3454 &dra7xx_l4_wkup__wd_timer2,
3455 NULL,
3456 };
3457
3458 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3459 &dra7xx_l4_per3__usb_otg_ss4,
3460 NULL,
3461 };
3462
3463 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3464 NULL,
3465 };
3466
3467 int __init dra7xx_hwmod_init(void)
3468 {
3469 int ret;
3470
3471 omap_hwmod_init();
3472 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3473
3474 if (!ret && soc_is_dra74x())
3475 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3476 else if (!ret && soc_is_dra72x())
3477 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3478
3479 return ret;
3480 }
Linux with added FPC-III support