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mm: hugetlb: fix hugepage memory leak caused by wrong reserve count
[linux/fpc-iii.git] / arch / arm / mach-pxa / lpd270.c
blob5fcd4f094900b810b6fd902903c53fe27fb672ec
1 /*
2 * linux/arch/arm/mach-pxa/lpd270.c
3 *
4 * Support for the LogicPD PXA270 Card Engine.
5 * Derived from the mainstone code, which carries these notices:
6 *
7 * Author: Nicolas Pitre
8 * Created: Nov 05, 2002
9 * Copyright: MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #include <linux/gpio.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/interrupt.h>
20 #include <linux/sched.h>
21 #include <linux/bitops.h>
22 #include <linux/fb.h>
23 #include <linux/ioport.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/partitions.h>
26 #include <linux/pwm.h>
27 #include <linux/pwm_backlight.h>
28 #include <linux/smc91x.h>
29
30 #include <asm/types.h>
31 #include <asm/setup.h>
32 #include <asm/memory.h>
33 #include <asm/mach-types.h>
34 #include <mach/hardware.h>
35 #include <asm/irq.h>
36 #include <asm/sizes.h>
37
38 #include <asm/mach/arch.h>
39 #include <asm/mach/map.h>
40 #include <asm/mach/irq.h>
41 #include <asm/mach/flash.h>
42
43 #include <mach/pxa27x.h>
44 #include <mach/lpd270.h>
45 #include <mach/audio.h>
46 #include <linux/platform_data/video-pxafb.h>
47 #include <linux/platform_data/mmc-pxamci.h>
48 #include <linux/platform_data/irda-pxaficp.h>
49 #include <linux/platform_data/usb-ohci-pxa27x.h>
50 #include <mach/smemc.h>
51
52 #include "generic.h"
53 #include "devices.h"
54
55 static unsigned long lpd270_pin_config[] __initdata = {
56 /* Chip Selects */
57 GPIO15_nCS_1, /* Mainboard Flash */
58 GPIO78_nCS_2, /* CPLD + Ethernet */
59
60 /* LCD - 16bpp Active TFT */
61 GPIO58_LCD_LDD_0,
62 GPIO59_LCD_LDD_1,
63 GPIO60_LCD_LDD_2,
64 GPIO61_LCD_LDD_3,
65 GPIO62_LCD_LDD_4,
66 GPIO63_LCD_LDD_5,
67 GPIO64_LCD_LDD_6,
68 GPIO65_LCD_LDD_7,
69 GPIO66_LCD_LDD_8,
70 GPIO67_LCD_LDD_9,
71 GPIO68_LCD_LDD_10,
72 GPIO69_LCD_LDD_11,
73 GPIO70_LCD_LDD_12,
74 GPIO71_LCD_LDD_13,
75 GPIO72_LCD_LDD_14,
76 GPIO73_LCD_LDD_15,
77 GPIO74_LCD_FCLK,
78 GPIO75_LCD_LCLK,
79 GPIO76_LCD_PCLK,
80 GPIO77_LCD_BIAS,
81 GPIO16_PWM0_OUT, /* Backlight */
82
83 /* USB Host */
84 GPIO88_USBH1_PWR,
85 GPIO89_USBH1_PEN,
86
87 /* AC97 */
88 GPIO28_AC97_BITCLK,
89 GPIO29_AC97_SDATA_IN_0,
90 GPIO30_AC97_SDATA_OUT,
91 GPIO31_AC97_SYNC,
92 GPIO45_AC97_SYSCLK,
93
94 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
95 };
96
97 static unsigned int lpd270_irq_enabled;
98
99 static void lpd270_mask_irq(struct irq_data *d)
100 {
101 int lpd270_irq = d->irq - LPD270_IRQ(0);
102
103 __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
104
105 lpd270_irq_enabled &= ~(1 << lpd270_irq);
106 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
107 }
108
109 static void lpd270_unmask_irq(struct irq_data *d)
110 {
111 int lpd270_irq = d->irq - LPD270_IRQ(0);
112
113 lpd270_irq_enabled |= 1 << lpd270_irq;
114 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
115 }
116
117 static struct irq_chip lpd270_irq_chip = {
118 .name = "CPLD",
119 .irq_ack = lpd270_mask_irq,
120 .irq_mask = lpd270_mask_irq,
121 .irq_unmask = lpd270_unmask_irq,
122 };
123
124 static void lpd270_irq_handler(struct irq_desc *desc)
125 {
126 unsigned int irq;
127 unsigned long pending;
128
129 pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
130 do {
131 /* clear useless edge notification */
132 desc->irq_data.chip->irq_ack(&desc->irq_data);
133 if (likely(pending)) {
134 irq = LPD270_IRQ(0) + __ffs(pending);
135 generic_handle_irq(irq);
136
137 pending = __raw_readw(LPD270_INT_STATUS) &
138 lpd270_irq_enabled;
139 }
140 } while (pending);
141 }
142
143 static void __init lpd270_init_irq(void)
144 {
145 int irq;
146
147 pxa27x_init_irq();
148
149 __raw_writew(0, LPD270_INT_MASK);
150 __raw_writew(0, LPD270_INT_STATUS);
151
152 /* setup extra LogicPD PXA270 irqs */
153 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
154 irq_set_chip_and_handler(irq, &lpd270_irq_chip,
155 handle_level_irq);
156 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
157 }
158 irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
159 irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
160 }
161
162
163 #ifdef CONFIG_PM
164 static void lpd270_irq_resume(void)
165 {
166 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
167 }
168
169 static struct syscore_ops lpd270_irq_syscore_ops = {
170 .resume = lpd270_irq_resume,
171 };
172
173 static int __init lpd270_irq_device_init(void)
174 {
175 if (machine_is_logicpd_pxa270()) {
176 register_syscore_ops(&lpd270_irq_syscore_ops);
177 return 0;
178 }
179 return -ENODEV;
180 }
181
182 device_initcall(lpd270_irq_device_init);
183 #endif
184
185
186 static struct resource smc91x_resources[] = {
187 [0] = {
188 .start = LPD270_ETH_PHYS,
189 .end = (LPD270_ETH_PHYS + 0xfffff),
190 .flags = IORESOURCE_MEM,
191 },
192 [1] = {
193 .start = LPD270_ETHERNET_IRQ,
194 .end = LPD270_ETHERNET_IRQ,
195 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
196 },
197 };
198
199 struct smc91x_platdata smc91x_platdata = {
200 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
201 };
202
203 static struct platform_device smc91x_device = {
204 .name = "smc91x",
205 .id = 0,
206 .num_resources = ARRAY_SIZE(smc91x_resources),
207 .resource = smc91x_resources,
208 .dev.platform_data = &smc91x_platdata,
209 };
210
211 static struct resource lpd270_flash_resources[] = {
212 [0] = {
213 .start = PXA_CS0_PHYS,
214 .end = PXA_CS0_PHYS + SZ_64M - 1,
215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
218 .start = PXA_CS1_PHYS,
219 .end = PXA_CS1_PHYS + SZ_64M - 1,
220 .flags = IORESOURCE_MEM,
221 },
222 };
223
224 static struct mtd_partition lpd270_flash0_partitions[] = {
225 {
226 .name = "Bootloader",
227 .size = 0x00040000,
228 .offset = 0,
229 .mask_flags = MTD_WRITEABLE /* force read-only */
230 }, {
231 .name = "Kernel",
232 .size = 0x00400000,
233 .offset = 0x00040000,
234 }, {
235 .name = "Filesystem",
236 .size = MTDPART_SIZ_FULL,
237 .offset = 0x00440000
238 },
239 };
240
241 static struct flash_platform_data lpd270_flash_data[2] = {
242 {
243 .name = "processor-flash",
244 .map_name = "cfi_probe",
245 .parts = lpd270_flash0_partitions,
246 .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
247 }, {
248 .name = "mainboard-flash",
249 .map_name = "cfi_probe",
250 .parts = NULL,
251 .nr_parts = 0,
252 }
253 };
254
255 static struct platform_device lpd270_flash_device[2] = {
256 {
257 .name = "pxa2xx-flash",
258 .id = 0,
259 .dev = {
260 .platform_data = &lpd270_flash_data[0],
261 },
262 .resource = &lpd270_flash_resources[0],
263 .num_resources = 1,
264 }, {
265 .name = "pxa2xx-flash",
266 .id = 1,
267 .dev = {
268 .platform_data = &lpd270_flash_data[1],
269 },
270 .resource = &lpd270_flash_resources[1],
271 .num_resources = 1,
272 },
273 };
274
275 static struct pwm_lookup lpd270_pwm_lookup[] = {
276 PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
277 PWM_POLARITY_NORMAL),
278 };
279
280 static struct platform_pwm_backlight_data lpd270_backlight_data = {
281 .max_brightness = 1,
282 .dft_brightness = 1,
283 .enable_gpio = -1,
284 };
285
286 static struct platform_device lpd270_backlight_device = {
287 .name = "pwm-backlight",
288 .dev = {
289 .parent = &pxa27x_device_pwm0.dev,
290 .platform_data = &lpd270_backlight_data,
291 },
292 };
293
294 /* 5.7" TFT QVGA (LoLo display number 1) */
295 static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
296 .pixclock = 150000,
297 .xres = 320,
298 .yres = 240,
299 .bpp = 16,
300 .hsync_len = 0x14,
301 .left_margin = 0x28,
302 .right_margin = 0x0a,
303 .vsync_len = 0x02,
304 .upper_margin = 0x08,
305 .lower_margin = 0x14,
306 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
307 };
308
309 static struct pxafb_mach_info sharp_lq057q3dc02 = {
310 .modes = &sharp_lq057q3dc02_mode,
311 .num_modes = 1,
312 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
313 LCD_ALTERNATE_MAPPING,
314 };
315
316 /* 12.1" TFT SVGA (LoLo display number 2) */
317 static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
318 .pixclock = 50000,
319 .xres = 800,
320 .yres = 600,
321 .bpp = 16,
322 .hsync_len = 0x05,
323 .left_margin = 0x52,
324 .right_margin = 0x05,
325 .vsync_len = 0x04,
326 .upper_margin = 0x14,
327 .lower_margin = 0x0a,
328 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
329 };
330
331 static struct pxafb_mach_info sharp_lq121s1dg31 = {
332 .modes = &sharp_lq121s1dg31_mode,
333 .num_modes = 1,
334 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
335 LCD_ALTERNATE_MAPPING,
336 };
337
338 /* 3.6" TFT QVGA (LoLo display number 3) */
339 static struct pxafb_mode_info sharp_lq036q1da01_mode = {
340 .pixclock = 150000,
341 .xres = 320,
342 .yres = 240,
343 .bpp = 16,
344 .hsync_len = 0x0e,
345 .left_margin = 0x04,
346 .right_margin = 0x0a,
347 .vsync_len = 0x03,
348 .upper_margin = 0x03,
349 .lower_margin = 0x03,
350 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
351 };
352
353 static struct pxafb_mach_info sharp_lq036q1da01 = {
354 .modes = &sharp_lq036q1da01_mode,
355 .num_modes = 1,
356 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
357 LCD_ALTERNATE_MAPPING,
358 };
359
360 /* 6.4" TFT VGA (LoLo display number 5) */
361 static struct pxafb_mode_info sharp_lq64d343_mode = {
362 .pixclock = 25000,
363 .xres = 640,
364 .yres = 480,
365 .bpp = 16,
366 .hsync_len = 0x31,
367 .left_margin = 0x89,
368 .right_margin = 0x19,
369 .vsync_len = 0x12,
370 .upper_margin = 0x22,
371 .lower_margin = 0x00,
372 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
373 };
374
375 static struct pxafb_mach_info sharp_lq64d343 = {
376 .modes = &sharp_lq64d343_mode,
377 .num_modes = 1,
378 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
379 LCD_ALTERNATE_MAPPING,
380 };
381
382 /* 10.4" TFT VGA (LoLo display number 7) */
383 static struct pxafb_mode_info sharp_lq10d368_mode = {
384 .pixclock = 25000,
385 .xres = 640,
386 .yres = 480,
387 .bpp = 16,
388 .hsync_len = 0x31,
389 .left_margin = 0x89,
390 .right_margin = 0x19,
391 .vsync_len = 0x12,
392 .upper_margin = 0x22,
393 .lower_margin = 0x00,
394 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
395 };
396
397 static struct pxafb_mach_info sharp_lq10d368 = {
398 .modes = &sharp_lq10d368_mode,
399 .num_modes = 1,
400 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
401 LCD_ALTERNATE_MAPPING,
402 };
403
404 /* 3.5" TFT QVGA (LoLo display number 8) */
405 static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
406 .pixclock = 150000,
407 .xres = 240,
408 .yres = 320,
409 .bpp = 16,
410 .hsync_len = 0x0e,
411 .left_margin = 0x0a,
412 .right_margin = 0x0a,
413 .vsync_len = 0x03,
414 .upper_margin = 0x05,
415 .lower_margin = 0x14,
416 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
417 };
418
419 static struct pxafb_mach_info sharp_lq035q7db02_20 = {
420 .modes = &sharp_lq035q7db02_20_mode,
421 .num_modes = 1,
422 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
423 LCD_ALTERNATE_MAPPING,
424 };
425
426 static struct pxafb_mach_info *lpd270_lcd_to_use;
427
428 static int __init lpd270_set_lcd(char *str)
429 {
430 if (!strncasecmp(str, "lq057q3dc02", 11)) {
431 lpd270_lcd_to_use = &sharp_lq057q3dc02;
432 } else if (!strncasecmp(str, "lq121s1dg31", 11)) {
433 lpd270_lcd_to_use = &sharp_lq121s1dg31;
434 } else if (!strncasecmp(str, "lq036q1da01", 11)) {
435 lpd270_lcd_to_use = &sharp_lq036q1da01;
436 } else if (!strncasecmp(str, "lq64d343", 8)) {
437 lpd270_lcd_to_use = &sharp_lq64d343;
438 } else if (!strncasecmp(str, "lq10d368", 8)) {
439 lpd270_lcd_to_use = &sharp_lq10d368;
440 } else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
441 lpd270_lcd_to_use = &sharp_lq035q7db02_20;
442 } else {
443 printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
444 }
445
446 return 1;
447 }
448
449 __setup("lcd=", lpd270_set_lcd);
450
451 static struct platform_device *platform_devices[] __initdata = {
452 &smc91x_device,
453 &lpd270_backlight_device,
454 &lpd270_flash_device[0],
455 &lpd270_flash_device[1],
456 };
457
458 static struct pxaohci_platform_data lpd270_ohci_platform_data = {
459 .port_mode = PMM_PERPORT_MODE,
460 .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
461 };
462
463 static void __init lpd270_init(void)
464 {
465 pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
466
467 pxa_set_ffuart_info(NULL);
468 pxa_set_btuart_info(NULL);
469 pxa_set_stuart_info(NULL);
470
471 lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
472 lpd270_flash_data[1].width = 4;
473
474 /*
475 * System bus arbiter setting:
476 * - Core_Park
477 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
478 */
479 ARB_CNTRL = ARB_CORE_PARK | 0x234;
480
481 pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
482 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
483
484 pxa_set_ac97_info(NULL);
485
486 if (lpd270_lcd_to_use != NULL)
487 pxa_set_fb_info(NULL, lpd270_lcd_to_use);
488
489 pxa_set_ohci_info(&lpd270_ohci_platform_data);
490 }
491
492
493 static struct map_desc lpd270_io_desc[] __initdata = {
494 {
495 .virtual = (unsigned long)LPD270_CPLD_VIRT,
496 .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
497 .length = LPD270_CPLD_SIZE,
498 .type = MT_DEVICE,
499 },
500 };
501
502 static void __init lpd270_map_io(void)
503 {
504 pxa27x_map_io();
505 iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
506
507 /* for use I SRAM as framebuffer. */
508 PSLR |= 0x00000F04;
509 PCFR = 0x00000066;
510 }
511
512 MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
513 /* Maintainer: Peter Barada */
514 .atag_offset = 0x100,
515 .map_io = lpd270_map_io,
516 .nr_irqs = LPD270_NR_IRQS,
517 .init_irq = lpd270_init_irq,
518 .handle_irq = pxa27x_handle_irq,
519 .init_time = pxa_timer_init,
520 .init_machine = lpd270_init,
521 .restart = pxa_restart,
522 MACHINE_END
Linux with added FPC-III support