arch/arm64/boot/dts/broadcom/ns2.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34
  35 /memreserve/ 0x84b00000 0x00000008;
  36
  37 / {
  38         compatible = "brcm,ns2";
  39         interrupt-parent = <&gic>;
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42
  43         cpus {
  44                 #address-cells = <2>;
  45                 #size-cells = <0>;
  46
  47                 cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a57", "arm,armv8";
  50                         reg = <0 0>;
  51                         enable-method = "spin-table";
  52                         cpu-release-addr = <0 0x84b00000>;
  53                 };
  54
  55                 cpu@1 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a57", "arm,armv8";
  58                         reg = <0 1>;
  59                         enable-method = "spin-table";
  60                         cpu-release-addr = <0 0x84b00000>;
  61                 };
  62
  63                 cpu@2 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a57", "arm,armv8";
  66                         reg = <0 2>;
  67                         enable-method = "spin-table";
  68                         cpu-release-addr = <0 0x84b00000>;
  69                 };
  70
  71                 cpu@3 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a57", "arm,armv8";
  74                         reg = <0 3>;
  75                         enable-method = "spin-table";
  76                         cpu-release-addr = <0 0x84b00000>;
  77                 };
  78         };
  79
  80         timer {
  81                 compatible = "arm,armv8-timer";
  82                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
  83                               IRQ_TYPE_EDGE_RISING)>,
  84                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
  85                               IRQ_TYPE_EDGE_RISING)>,
  86                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
  87                               IRQ_TYPE_EDGE_RISING)>,
  88                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
  89                               IRQ_TYPE_EDGE_RISING)>;
  90         };
  91
  92         soc: soc {
  93                 compatible = "simple-bus";
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 ranges = <0 0 0 0xffffffff>;
  97
  98                 gic: interrupt-controller@65210000 {
  99                         compatible = "arm,gic-400";
 100                         #interrupt-cells = <3>;
 101                         interrupt-controller;
 102                         reg = <0x65210000 0x1000>,
 103                               <0x65220000 0x1000>,
 104                               <0x65240000 0x2000>,
 105                               <0x65260000 0x1000>;
 106                 };
 107
 108                 uart3: serial@66130000 {
 109                         compatible = "snps,dw-apb-uart";
 110                         reg = <0x66130000 0x100>;
 111                         interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
 112                         reg-shift = <2>;
 113                         reg-io-width = <4>;
 114                         clock-frequency = <23961600>;
 115                         status = "disabled";
 116                 };
 117         };
 118 };