| blob | f9c5a549c2c02ca691b75eadcd73032492528099 |
1 /*
2 * SAMSUNG EXYNOS7 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
12 #include <dt-bindings/clock/exynos7-clk.h>
14 / {
15 compatible = "samsung,exynos7";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 aliases {
21 pinctrl0 = &pinctrl_alive;
22 pinctrl1 = &pinctrl_bus0;
23 pinctrl2 = &pinctrl_nfc;
24 pinctrl3 = &pinctrl_touch;
25 pinctrl4 = &pinctrl_ff;
26 pinctrl5 = &pinctrl_ese;
27 pinctrl6 = &pinctrl_fsys0;
28 pinctrl7 = &pinctrl_fsys1;
29 pinctrl8 = &pinctrl_bus1;
30 };
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a57", "arm,armv8";
39 reg = <0x0>;
40 enable-method = "psci";
41 };
43 cpu@1 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a57", "arm,armv8";
46 reg = <0x1>;
47 enable-method = "psci";
48 };
50 cpu@2 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a57", "arm,armv8";
53 reg = <0x2>;
54 enable-method = "psci";
55 };
57 cpu@3 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a57", "arm,armv8";
60 reg = <0x3>;
61 enable-method = "psci";
62 };
63 };
65 psci {
66 compatible = "arm,psci-0.2";
67 method = "smc";
68 };
70 soc: soc {
71 compatible = "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges = <0 0 0 0x18000000>;
76 chipid@10000000 {
77 compatible = "samsung,exynos4210-chipid";
78 reg = <0x10000000 0x100>;
79 };
81 fin_pll: xxti {
82 compatible = "fixed-clock";
83 clock-output-names = "fin_pll";
84 #clock-cells = <0>;
85 };
87 gic: interrupt-controller@11001000 {
88 compatible = "arm,gic-400";
89 #interrupt-cells = <3>;
90 #address-cells = <0>;
91 interrupt-controller;
92 reg = <0x11001000 0x1000>,
93 <0x11002000 0x1000>,
94 <0x11004000 0x2000>,
95 <0x11006000 0x2000>;
96 };
98 clock_topc: clock-controller@10570000 {
99 compatible = "samsung,exynos7-clock-topc";
100 reg = <0x10570000 0x10000>;
101 #clock-cells = <1>;
102 };
104 clock_top0: clock-controller@105d0000 {
105 compatible = "samsung,exynos7-clock-top0";
106 reg = <0x105d0000 0xb000>;
107 #clock-cells = <1>;
108 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
109 <&clock_topc DOUT_SCLK_BUS1_PLL>,
110 <&clock_topc DOUT_SCLK_CC_PLL>,
111 <&clock_topc DOUT_SCLK_MFC_PLL>;
112 clock-names = "fin_pll", "dout_sclk_bus0_pll",
113 "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
114 "dout_sclk_mfc_pll";
115 };
117 clock_top1: clock-controller@105e0000 {
118 compatible = "samsung,exynos7-clock-top1";
119 reg = <0x105e0000 0xb000>;
120 #clock-cells = <1>;
121 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
122 <&clock_topc DOUT_SCLK_BUS1_PLL>,
123 <&clock_topc DOUT_SCLK_CC_PLL>,
124 <&clock_topc DOUT_SCLK_MFC_PLL>;
125 clock-names = "fin_pll", "dout_sclk_bus0_pll",
126 "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
127 "dout_sclk_mfc_pll";
128 };
130 clock_ccore: clock-controller@105b0000 {
131 compatible = "samsung,exynos7-clock-ccore";
132 reg = <0x105b0000 0xd00>;
133 #clock-cells = <1>;
134 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
135 clock-names = "fin_pll", "dout_aclk_ccore_133";
136 };
138 clock_peric0: clock-controller@13610000 {
139 compatible = "samsung,exynos7-clock-peric0";
140 reg = <0x13610000 0xd00>;
141 #clock-cells = <1>;
142 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
143 <&clock_top0 CLK_SCLK_UART0>;
144 clock-names = "fin_pll", "dout_aclk_peric0_66",
145 "sclk_uart0";
146 };
148 clock_peric1: clock-controller@14c80000 {
149 compatible = "samsung,exynos7-clock-peric1";
150 reg = <0x14c80000 0xd00>;
151 #clock-cells = <1>;
152 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
153 <&clock_top0 CLK_SCLK_UART1>,
154 <&clock_top0 CLK_SCLK_UART2>,
155 <&clock_top0 CLK_SCLK_UART3>;
156 clock-names = "fin_pll", "dout_aclk_peric1_66",
157 "sclk_uart1", "sclk_uart2", "sclk_uart3";
158 };
160 clock_peris: clock-controller@10040000 {
161 compatible = "samsung,exynos7-clock-peris";
162 reg = <0x10040000 0xd00>;
163 #clock-cells = <1>;
164 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
165 clock-names = "fin_pll", "dout_aclk_peris_66";
166 };
168 clock_fsys0: clock-controller@10e90000 {
169 compatible = "samsung,exynos7-clock-fsys0";
170 reg = <0x10e90000 0xd00>;
171 #clock-cells = <1>;
172 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
173 <&clock_top1 DOUT_SCLK_MMC2>;
174 clock-names = "fin_pll", "dout_aclk_fsys0_200",
175 "dout_sclk_mmc2";
176 };
178 clock_fsys1: clock-controller@156e0000 {
179 compatible = "samsung,exynos7-clock-fsys1";
180 reg = <0x156e0000 0xd00>;
181 #clock-cells = <1>;
182 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
183 <&clock_top1 DOUT_SCLK_MMC0>,
184 <&clock_top1 DOUT_SCLK_MMC1>;
185 clock-names = "fin_pll", "dout_aclk_fsys1_200",
186 "dout_sclk_mmc0", "dout_sclk_mmc1";
187 };
189 serial_0: serial@13630000 {
190 compatible = "samsung,exynos4210-uart";
191 reg = <0x13630000 0x100>;
192 interrupts = <0 440 0>;
193 clocks = <&clock_peric0 PCLK_UART0>,
194 <&clock_peric0 SCLK_UART0>;
195 clock-names = "uart", "clk_uart_baud0";
196 status = "disabled";
197 };
199 serial_1: serial@14c20000 {
200 compatible = "samsung,exynos4210-uart";
201 reg = <0x14c20000 0x100>;
202 interrupts = <0 456 0>;
203 clocks = <&clock_peric1 PCLK_UART1>,
204 <&clock_peric1 SCLK_UART1>;
205 clock-names = "uart", "clk_uart_baud0";
206 status = "disabled";
207 };
209 serial_2: serial@14c30000 {
210 compatible = "samsung,exynos4210-uart";
211 reg = <0x14c30000 0x100>;
212 interrupts = <0 457 0>;
213 clocks = <&clock_peric1 PCLK_UART2>,
214 <&clock_peric1 SCLK_UART2>;
215 clock-names = "uart", "clk_uart_baud0";
216 status = "disabled";
217 };
219 serial_3: serial@14c40000 {
220 compatible = "samsung,exynos4210-uart";
221 reg = <0x14c40000 0x100>;
222 interrupts = <0 458 0>;
223 clocks = <&clock_peric1 PCLK_UART3>,
224 <&clock_peric1 SCLK_UART3>;
225 clock-names = "uart", "clk_uart_baud0";
226 status = "disabled";
227 };
229 pinctrl_alive: pinctrl@10580000 {
230 compatible = "samsung,exynos7-pinctrl";
231 reg = <0x10580000 0x1000>;
233 wakeup-interrupt-controller {
234 compatible = "samsung,exynos7-wakeup-eint";
235 interrupt-parent = <&gic>;
236 interrupts = <0 16 0>;
237 };
238 };
240 pinctrl_bus0: pinctrl@13470000 {
241 compatible = "samsung,exynos7-pinctrl";
242 reg = <0x13470000 0x1000>;
243 interrupts = <0 383 0>;
244 };
246 pinctrl_nfc: pinctrl@14cd0000 {
247 compatible = "samsung,exynos7-pinctrl";
248 reg = <0x14cd0000 0x1000>;
249 interrupts = <0 473 0>;
250 };
252 pinctrl_touch: pinctrl@14ce0000 {
253 compatible = "samsung,exynos7-pinctrl";
254 reg = <0x14ce0000 0x1000>;
255 interrupts = <0 474 0>;
256 };
258 pinctrl_ff: pinctrl@14c90000 {
259 compatible = "samsung,exynos7-pinctrl";
260 reg = <0x14c90000 0x1000>;
261 interrupts = <0 475 0>;
262 };
264 pinctrl_ese: pinctrl@14ca0000 {
265 compatible = "samsung,exynos7-pinctrl";
266 reg = <0x14ca0000 0x1000>;
267 interrupts = <0 476 0>;
268 };
270 pinctrl_fsys0: pinctrl@10e60000 {
271 compatible = "samsung,exynos7-pinctrl";
272 reg = <0x10e60000 0x1000>;
273 interrupts = <0 221 0>;
274 };
276 pinctrl_fsys1: pinctrl@15690000 {
277 compatible = "samsung,exynos7-pinctrl";
278 reg = <0x15690000 0x1000>;
279 interrupts = <0 203 0>;
280 };
282 pinctrl_bus1: pinctrl@14870000 {
283 compatible = "samsung,exynos7-pinctrl";
284 reg = <0x14870000 0x1000>;
285 interrupts = <0 384 0>;
286 };
288 hsi2c_0: hsi2c@13640000 {
289 compatible = "samsung,exynos7-hsi2c";
290 reg = <0x13640000 0x1000>;
291 interrupts = <0 441 0>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&hs_i2c0_bus>;
296 clocks = <&clock_peric0 PCLK_HSI2C0>;
297 clock-names = "hsi2c";
298 status = "disabled";
299 };
301 hsi2c_1: hsi2c@13650000 {
302 compatible = "samsung,exynos7-hsi2c";
303 reg = <0x13650000 0x1000>;
304 interrupts = <0 442 0>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&hs_i2c1_bus>;
309 clocks = <&clock_peric0 PCLK_HSI2C1>;
310 clock-names = "hsi2c";
311 status = "disabled";
312 };
314 hsi2c_2: hsi2c@14e60000 {
315 compatible = "samsung,exynos7-hsi2c";
316 reg = <0x14e60000 0x1000>;
317 interrupts = <0 459 0>;
318 #address-cells = <1>;
319 #size-cells = <0>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&hs_i2c2_bus>;
322 clocks = <&clock_peric1 PCLK_HSI2C2>;
323 clock-names = "hsi2c";
324 status = "disabled";
325 };
327 hsi2c_3: hsi2c@14e70000 {
328 compatible = "samsung,exynos7-hsi2c";
329 reg = <0x14e70000 0x1000>;
330 interrupts = <0 460 0>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&hs_i2c3_bus>;
335 clocks = <&clock_peric1 PCLK_HSI2C3>;
336 clock-names = "hsi2c";
337 status = "disabled";
338 };
340 hsi2c_4: hsi2c@13660000 {
341 compatible = "samsung,exynos7-hsi2c";
342 reg = <0x13660000 0x1000>;
343 interrupts = <0 443 0>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&hs_i2c4_bus>;
348 clocks = <&clock_peric0 PCLK_HSI2C4>;
349 clock-names = "hsi2c";
350 status = "disabled";
351 };
353 hsi2c_5: hsi2c@13670000 {
354 compatible = "samsung,exynos7-hsi2c";
355 reg = <0x13670000 0x1000>;
356 interrupts = <0 444 0>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&hs_i2c5_bus>;
361 clocks = <&clock_peric0 PCLK_HSI2C5>;
362 clock-names = "hsi2c";
363 status = "disabled";
364 };
366 hsi2c_6: hsi2c@14e00000 {
367 compatible = "samsung,exynos7-hsi2c";
368 reg = <0x14e00000 0x1000>;
369 interrupts = <0 461 0>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&hs_i2c6_bus>;
374 clocks = <&clock_peric1 PCLK_HSI2C6>;
375 clock-names = "hsi2c";
376 status = "disabled";
377 };
379 hsi2c_7: hsi2c@13e10000 {
380 compatible = "samsung,exynos7-hsi2c";
381 reg = <0x13e10000 0x1000>;
382 interrupts = <0 462 0>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&hs_i2c7_bus>;
387 clocks = <&clock_peric1 PCLK_HSI2C7>;
388 clock-names = "hsi2c";
389 status = "disabled";
390 };
392 hsi2c_8: hsi2c@14e20000 {
393 compatible = "samsung,exynos7-hsi2c";
394 reg = <0x14e20000 0x1000>;
395 interrupts = <0 463 0>;
396 #address-cells = <1>;
397 #size-cells = <0>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&hs_i2c8_bus>;
400 clocks = <&clock_peric1 PCLK_HSI2C8>;
401 clock-names = "hsi2c";
402 status = "disabled";
403 };
405 hsi2c_9: hsi2c@13680000 {
406 compatible = "samsung,exynos7-hsi2c";
407 reg = <0x13680000 0x1000>;
408 interrupts = <0 445 0>;
409 #address-cells = <1>;
410 #size-cells = <0>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&hs_i2c9_bus>;
413 clocks = <&clock_peric0 PCLK_HSI2C9>;
414 clock-names = "hsi2c";
415 status = "disabled";
416 };
418 hsi2c_10: hsi2c@13690000 {
419 compatible = "samsung,exynos7-hsi2c";
420 reg = <0x13690000 0x1000>;
421 interrupts = <0 446 0>;
422 #address-cells = <1>;
423 #size-cells = <0>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&hs_i2c10_bus>;
426 clocks = <&clock_peric0 PCLK_HSI2C10>;
427 clock-names = "hsi2c";
428 status = "disabled";
429 };
431 hsi2c_11: hsi2c@136a0000 {
432 compatible = "samsung,exynos7-hsi2c";
433 reg = <0x136a0000 0x1000>;
434 interrupts = <0 447 0>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&hs_i2c11_bus>;
439 clocks = <&clock_peric0 PCLK_HSI2C11>;
440 clock-names = "hsi2c";
441 status = "disabled";
442 };
444 timer {
445 compatible = "arm,armv8-timer";
446 interrupts = <1 13 0xff01>,
447 <1 14 0xff01>,
448 <1 11 0xff01>,
449 <1 10 0xff01>;
450 };
452 pmu_system_controller: system-controller@105c0000 {
453 compatible = "samsung,exynos7-pmu", "syscon";
454 reg = <0x105c0000 0x5000>;
455 };
457 rtc: rtc@10590000 {
458 compatible = "samsung,s3c6410-rtc";
459 reg = <0x10590000 0x100>;
460 interrupts = <0 355 0>, <0 356 0>;
461 clocks = <&clock_ccore PCLK_RTC>;
462 clock-names = "rtc";
463 status = "disabled";
464 };
466 watchdog: watchdog@101d0000 {
467 compatible = "samsung,exynos7-wdt";
468 reg = <0x101d0000 0x100>;
469 interrupts = <0 110 0>;
470 clocks = <&clock_peris PCLK_WDT>;
471 clock-names = "watchdog";
472 samsung,syscon-phandle = <&pmu_system_controller>;
473 status = "disabled";
474 };
476 mmc_0: mmc@15740000 {
477 compatible = "samsung,exynos7-dw-mshc-smu";
478 interrupts = <0 201 0>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 reg = <0x15740000 0x2000>;
482 clocks = <&clock_fsys1 ACLK_MMC0>,
483 <&clock_top1 CLK_SCLK_MMC0>;
484 clock-names = "biu", "ciu";
485 fifo-depth = <0x40>;
486 status = "disabled";
487 };
489 mmc_1: mmc@15750000 {
490 compatible = "samsung,exynos7-dw-mshc";
491 interrupts = <0 202 0>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 reg = <0x15750000 0x2000>;
495 clocks = <&clock_fsys1 ACLK_MMC1>,
496 <&clock_top1 CLK_SCLK_MMC1>;
497 clock-names = "biu", "ciu";
498 fifo-depth = <0x40>;
499 status = "disabled";
500 };
502 mmc_2: mmc@15560000 {
503 compatible = "samsung,exynos7-dw-mshc-smu";
504 interrupts = <0 216 0>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 reg = <0x15560000 0x2000>;
508 clocks = <&clock_fsys0 ACLK_MMC2>,
509 <&clock_top1 CLK_SCLK_MMC2>;
510 clock-names = "biu", "ciu";
511 fifo-depth = <0x40>;
512 status = "disabled";
513 };
515 adc: adc@13620000 {
516 compatible = "samsung,exynos7-adc";
517 reg = <0x13620000 0x100>;
518 interrupts = <0 448 0>;
519 clocks = <&clock_peric0 PCLK_ADCIF>;
520 clock-names = "adc";
521 #io-channel-cells = <1>;
522 io-channel-ranges;
523 status = "disabled";
524 };
526 pwm: pwm@136c0000 {
527 compatible = "samsung,exynos4210-pwm";
528 reg = <0x136c0000 0x100>;
529 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
530 #pwm-cells = <3>;
531 clocks = <&clock_peric0 PCLK_PWM>;
532 clock-names = "timers";
533 };
534 };
535 };
537 #include "exynos7-pinctrl.dtsi"