arch/arm64/boot/dts/mediatek/mt6795.dtsi

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Mars.C <mars.cheng@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16
  17 / {
  18         compatible = "mediatek,mt6795";
  19         interrupt-parent = <&sysirq>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         psci {
  24                 compatible = "arm,psci-0.2";
  25                 method = "smc";
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu0: cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a53";
  35                         enable-method = "psci";
  36                         reg = <0x000>;
  37                 };
  38
  39                 cpu1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         enable-method = "psci";
  43                         reg = <0x001>;
  44                 };
  45
  46                 cpu2: cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         enable-method = "psci";
  50                         reg = <0x002>;
  51                 };
  52
  53                 cpu3: cpu@3 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53";
  56                         enable-method = "psci";
  57                         reg = <0x003>;
  58                 };
  59
  60                 cpu4: cpu@100 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         enable-method = "psci";
  64                         reg = <0x100>;
  65                 };
  66
  67                 cpu5: cpu@101 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a53";
  70                         enable-method = "psci";
  71                         reg = <0x101>;
  72                 };
  73
  74                 cpu6: cpu@102 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         enable-method = "psci";
  78                         reg = <0x102>;
  79                 };
  80
  81                 cpu7: cpu@103 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53";
  84                         enable-method = "psci";
  85                         reg = <0x103>;
  86                 };
  87         };
  88
  89         system_clk: dummy13m {
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <13000000>;
  92                 #clock-cells = <0>;
  93         };
  94
  95         rtc_clk: dummy32k {
  96                 compatible = "fixed-clock";
  97                 clock-frequency = <32000>;
  98                 #clock-cells = <0>;
  99         };
 100
 101         uart_clk: dummy26m {
 102                 compatible = "fixed-clock";
 103                 clock-frequency = <26000000>;
 104                 #clock-cells = <0>;
 105         };
 106
 107         timer {
 108                 compatible = "arm,armv8-timer";
 109                 interrupt-parent = <&gic>;
 110                 interrupts = <GIC_PPI 13
 111                              (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 112                              <GIC_PPI 14
 113                              (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 114                              <GIC_PPI 11
 115                              (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 116                              <GIC_PPI 10
 117                              (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 118         };
 119
 120         sysirq: intpol-controller@10200620 {
 121                 compatible = "mediatek,mt6795-sysirq",
 122                              "mediatek,mt6577-sysirq";
 123                 interrupt-controller;
 124                 #interrupt-cells = <3>;
 125                 interrupt-parent = <&gic>;
 126                 reg = <0 0x10200620 0 0x20>;
 127         };
 128
 129         gic: interrupt-controller@10221000 {
 130                 compatible = "arm,gic-400";
 131                 #interrupt-cells = <3>;
 132                 interrupt-parent = <&gic>;
 133                 interrupt-controller;
 134                 reg = <0 0x10221000 0 0x1000>,
 135                       <0 0x10222000 0 0x2000>,
 136                       <0 0x10224000 0 0x2000>,
 137                       <0 0x10226000 0 0x2000>;
 138         };
 139
 140         uart0: serial@11002000 {
 141                 compatible = "mediatek,mt6795-uart",
 142                              "mediatek,mt6577-uart";
 143                 reg = <0 0x11002000 0 0x400>;
 144                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 145                 clocks = <&uart_clk>;
 146                 status = "disabled";
 147         };
 148
 149         uart1: serial@11003000 {
 150                 compatible = "mediatek,mt6795-uart",
 151                              "mediatek,mt6577-uart";
 152                 reg = <0 0x11003000 0 0x400>;
 153                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 154                 clocks = <&uart_clk>;
 155                 status = "disabled";
 156         };
 157
 158         uart2: serial@11004000 {
 159                 compatible = "mediatek,mt6795-uart",
 160                              "mediatek,mt6577-uart";
 161                 reg = <0 0x11004000 0 0x400>;
 162                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 163                 clocks = <&uart_clk>;
 164                 status = "disabled";
 165         };
 166
 167         uart3: serial@11005000 {
 168                 compatible = "mediatek,mt6795-uart",
 169                              "mediatek,mt6577-uart";
 170                 reg = <0 0x11005000 0 0x400>;
 171                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 172                 clocks = <&uart_clk>;
 173                 status = "disabled";
 174         };
 175 };