| blob | 4dd5f93d0303f9302e80f171ed9bfbeff8bb994b |
1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/power/mt8173-power.h>
18 #include <dt-bindings/reset-controller/mt8173-resets.h>
19 #include "mt8173-pinfunc.h"
21 / {
22 compatible = "mediatek,mt8173";
23 interrupt-parent = <&sysirq>;
24 #address-cells = <2>;
25 #size-cells = <2>;
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
31 cpu-map {
32 cluster0 {
33 core0 {
34 cpu = <&cpu0>;
35 };
36 core1 {
37 cpu = <&cpu1>;
38 };
39 };
41 cluster1 {
42 core0 {
43 cpu = <&cpu2>;
44 };
45 core1 {
46 cpu = <&cpu3>;
47 };
48 };
49 };
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a53";
54 reg = <0x000>;
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
57 };
59 cpu1: cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x001>;
63 enable-method = "psci";
64 cpu-idle-states = <&CPU_SLEEP_0>;
65 };
67 cpu2: cpu@100 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a57";
70 reg = <0x100>;
71 enable-method = "psci";
72 cpu-idle-states = <&CPU_SLEEP_0>;
73 };
75 cpu3: cpu@101 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a57";
78 reg = <0x101>;
79 enable-method = "psci";
80 cpu-idle-states = <&CPU_SLEEP_0>;
81 };
83 idle-states {
84 entry-method = "psci";
86 CPU_SLEEP_0: cpu-sleep-0 {
87 compatible = "arm,idle-state";
88 local-timer-stop;
89 entry-latency-us = <639>;
90 exit-latency-us = <680>;
91 min-residency-us = <1088>;
92 arm,psci-suspend-param = <0x0010000>;
93 };
94 };
95 };
97 psci {
98 compatible = "arm,psci";
99 method = "smc";
100 cpu_suspend = <0x84000001>;
101 cpu_off = <0x84000002>;
102 cpu_on = <0x84000003>;
103 };
105 clk26m: oscillator@0 {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <26000000>;
109 clock-output-names = "clk26m";
110 };
112 clk32k: oscillator@1 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <32000>;
116 clock-output-names = "clk32k";
117 };
119 cpum_ck: oscillator@2 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "cpum_ck";
124 };
126 timer {
127 compatible = "arm,armv8-timer";
128 interrupt-parent = <&gic>;
129 interrupts = <GIC_PPI 13
130 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
131 <GIC_PPI 14
132 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
133 <GIC_PPI 11
134 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
135 <GIC_PPI 10
136 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
137 };
139 soc {
140 #address-cells = <2>;
141 #size-cells = <2>;
142 compatible = "simple-bus";
143 ranges;
145 topckgen: clock-controller@10000000 {
146 compatible = "mediatek,mt8173-topckgen";
147 reg = <0 0x10000000 0 0x1000>;
148 #clock-cells = <1>;
149 };
151 infracfg: power-controller@10001000 {
152 compatible = "mediatek,mt8173-infracfg", "syscon";
153 reg = <0 0x10001000 0 0x1000>;
154 #clock-cells = <1>;
155 #reset-cells = <1>;
156 };
158 pericfg: power-controller@10003000 {
159 compatible = "mediatek,mt8173-pericfg", "syscon";
160 reg = <0 0x10003000 0 0x1000>;
161 #clock-cells = <1>;
162 #reset-cells = <1>;
163 };
165 syscfg_pctl_a: syscfg_pctl_a@10005000 {
166 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
167 reg = <0 0x10005000 0 0x1000>;
168 };
170 pio: pinctrl@0x10005000 {
171 compatible = "mediatek,mt8173-pinctrl";
172 reg = <0 0x1000b000 0 0x1000>;
173 mediatek,pctl-regmap = <&syscfg_pctl_a>;
174 pins-are-numbered;
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
183 i2c0_pins_a: i2c0 {
184 pins1 {
185 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
186 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
187 bias-disable;
188 };
189 };
191 i2c1_pins_a: i2c1 {
192 pins1 {
193 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
194 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
195 bias-disable;
196 };
197 };
199 i2c2_pins_a: i2c2 {
200 pins1 {
201 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
202 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
203 bias-disable;
204 };
205 };
207 i2c3_pins_a: i2c3 {
208 pins1 {
209 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
210 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
211 bias-disable;
212 };
213 };
215 i2c4_pins_a: i2c4 {
216 pins1 {
217 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
218 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
219 bias-disable;
220 };
221 };
223 i2c6_pins_a: i2c6 {
224 pins1 {
225 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
226 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
227 bias-disable;
228 };
229 };
230 };
232 scpsys: scpsys@10006000 {
233 compatible = "mediatek,mt8173-scpsys";
234 #power-domain-cells = <1>;
235 reg = <0 0x10006000 0 0x1000>;
236 clocks = <&clk26m>,
237 <&topckgen CLK_TOP_MM_SEL>,
238 <&topckgen CLK_TOP_VENC_SEL>,
239 <&topckgen CLK_TOP_VENC_LT_SEL>;
240 clock-names = "mfg", "mm", "venc", "venc_lt";
241 infracfg = <&infracfg>;
242 };
244 watchdog: watchdog@10007000 {
245 compatible = "mediatek,mt8173-wdt",
246 "mediatek,mt6589-wdt";
247 reg = <0 0x10007000 0 0x100>;
248 };
250 pwrap: pwrap@1000d000 {
251 compatible = "mediatek,mt8173-pwrap";
252 reg = <0 0x1000d000 0 0x1000>;
253 reg-names = "pwrap";
254 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
255 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
256 reset-names = "pwrap";
257 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
258 clock-names = "spi", "wrap";
259 };
261 sysirq: intpol-controller@10200620 {
262 compatible = "mediatek,mt8173-sysirq",
263 "mediatek,mt6577-sysirq";
264 interrupt-controller;
265 #interrupt-cells = <3>;
266 interrupt-parent = <&gic>;
267 reg = <0 0x10200620 0 0x20>;
268 };
270 apmixedsys: clock-controller@10209000 {
271 compatible = "mediatek,mt8173-apmixedsys";
272 reg = <0 0x10209000 0 0x1000>;
273 #clock-cells = <1>;
274 };
276 gic: interrupt-controller@10220000 {
277 compatible = "arm,gic-400";
278 #interrupt-cells = <3>;
279 interrupt-parent = <&gic>;
280 interrupt-controller;
281 reg = <0 0x10221000 0 0x1000>,
282 <0 0x10222000 0 0x2000>,
283 <0 0x10224000 0 0x2000>,
284 <0 0x10226000 0 0x2000>;
285 interrupts = <GIC_PPI 9
286 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
287 };
289 uart0: serial@11002000 {
290 compatible = "mediatek,mt8173-uart",
291 "mediatek,mt6577-uart";
292 reg = <0 0x11002000 0 0x400>;
293 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
294 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
295 clock-names = "baud", "bus";
296 status = "disabled";
297 };
299 uart1: serial@11003000 {
300 compatible = "mediatek,mt8173-uart",
301 "mediatek,mt6577-uart";
302 reg = <0 0x11003000 0 0x400>;
303 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
304 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
305 clock-names = "baud", "bus";
306 status = "disabled";
307 };
309 uart2: serial@11004000 {
310 compatible = "mediatek,mt8173-uart",
311 "mediatek,mt6577-uart";
312 reg = <0 0x11004000 0 0x400>;
313 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
314 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
315 clock-names = "baud", "bus";
316 status = "disabled";
317 };
319 uart3: serial@11005000 {
320 compatible = "mediatek,mt8173-uart",
321 "mediatek,mt6577-uart";
322 reg = <0 0x11005000 0 0x400>;
323 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
324 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
325 clock-names = "baud", "bus";
326 status = "disabled";
327 };
329 i2c0: i2c@11007000 {
330 compatible = "mediatek,mt8173-i2c";
331 reg = <0 0x11007000 0 0x70>,
332 <0 0x11000100 0 0x80>;
333 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
334 clock-div = <16>;
335 clocks = <&pericfg CLK_PERI_I2C0>,
336 <&pericfg CLK_PERI_AP_DMA>;
337 clock-names = "main", "dma";
338 pinctrl-names = "default";
339 pinctrl-0 = <&i2c0_pins_a>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 status = "disabled";
343 };
345 i2c1: i2c@11008000 {
346 compatible = "mediatek,mt8173-i2c";
347 reg = <0 0x11008000 0 0x70>,
348 <0 0x11000180 0 0x80>;
349 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
350 clock-div = <16>;
351 clocks = <&pericfg CLK_PERI_I2C1>,
352 <&pericfg CLK_PERI_AP_DMA>;
353 clock-names = "main", "dma";
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c1_pins_a>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358 status = "disabled";
359 };
361 i2c2: i2c@11009000 {
362 compatible = "mediatek,mt8173-i2c";
363 reg = <0 0x11009000 0 0x70>,
364 <0 0x11000200 0 0x80>;
365 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
366 clock-div = <16>;
367 clocks = <&pericfg CLK_PERI_I2C2>,
368 <&pericfg CLK_PERI_AP_DMA>;
369 clock-names = "main", "dma";
370 pinctrl-names = "default";
371 pinctrl-0 = <&i2c2_pins_a>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374 status = "disabled";
375 };
377 spi: spi@1100a000 {
378 compatible = "mediatek,mt8173-spi";
379 #address-cells = <1>;
380 #size-cells = <0>;
381 reg = <0 0x1100a000 0 0x1000>;
382 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
383 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
384 <&topckgen CLK_TOP_SPI_SEL>,
385 <&pericfg CLK_PERI_SPI0>;
386 clock-names = "parent-clk", "sel-clk", "spi-clk";
387 status = "disabled";
388 };
390 i2c3: i2c@11010000 {
391 compatible = "mediatek,mt8173-i2c";
392 reg = <0 0x11010000 0 0x70>,
393 <0 0x11000280 0 0x80>;
394 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
395 clock-div = <16>;
396 clocks = <&pericfg CLK_PERI_I2C3>,
397 <&pericfg CLK_PERI_AP_DMA>;
398 clock-names = "main", "dma";
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2c3_pins_a>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403 status = "disabled";
404 };
406 i2c4: i2c@11011000 {
407 compatible = "mediatek,mt8173-i2c";
408 reg = <0 0x11011000 0 0x70>,
409 <0 0x11000300 0 0x80>;
410 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
411 clock-div = <16>;
412 clocks = <&pericfg CLK_PERI_I2C4>,
413 <&pericfg CLK_PERI_AP_DMA>;
414 clock-names = "main", "dma";
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2c4_pins_a>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 status = "disabled";
420 };
422 i2c6: i2c@11013000 {
423 compatible = "mediatek,mt8173-i2c";
424 reg = <0 0x11013000 0 0x70>,
425 <0 0x11000080 0 0x80>;
426 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
427 clock-div = <16>;
428 clocks = <&pericfg CLK_PERI_I2C6>,
429 <&pericfg CLK_PERI_AP_DMA>;
430 clock-names = "main", "dma";
431 pinctrl-names = "default";
432 pinctrl-0 = <&i2c6_pins_a>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 status = "disabled";
436 };
438 afe: audio-controller@11220000 {
439 compatible = "mediatek,mt8173-afe-pcm";
440 reg = <0 0x11220000 0 0x1000>;
441 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
442 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
443 clocks = <&infracfg CLK_INFRA_AUDIO>,
444 <&topckgen CLK_TOP_AUDIO_SEL>,
445 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
446 <&topckgen CLK_TOP_APLL1_DIV0>,
447 <&topckgen CLK_TOP_APLL2_DIV0>,
448 <&topckgen CLK_TOP_I2S0_M_SEL>,
449 <&topckgen CLK_TOP_I2S1_M_SEL>,
450 <&topckgen CLK_TOP_I2S2_M_SEL>,
451 <&topckgen CLK_TOP_I2S3_M_SEL>,
452 <&topckgen CLK_TOP_I2S3_B_SEL>;
453 clock-names = "infra_sys_audio_clk",
454 "top_pdn_audio",
455 "top_pdn_aud_intbus",
456 "bck0",
457 "bck1",
458 "i2s0_m",
459 "i2s1_m",
460 "i2s2_m",
461 "i2s3_m",
462 "i2s3_b";
463 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
464 <&topckgen CLK_TOP_AUD_2_SEL>;
465 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
466 <&topckgen CLK_TOP_APLL2>;
467 };
469 mmc0: mmc@11230000 {
470 compatible = "mediatek,mt8173-mmc",
471 "mediatek,mt8135-mmc";
472 reg = <0 0x11230000 0 0x1000>;
473 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
474 clocks = <&pericfg CLK_PERI_MSDC30_0>,
475 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
476 clock-names = "source", "hclk";
477 status = "disabled";
478 };
480 mmc1: mmc@11240000 {
481 compatible = "mediatek,mt8173-mmc",
482 "mediatek,mt8135-mmc";
483 reg = <0 0x11240000 0 0x1000>;
484 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
485 clocks = <&pericfg CLK_PERI_MSDC30_1>,
486 <&topckgen CLK_TOP_AXI_SEL>;
487 clock-names = "source", "hclk";
488 status = "disabled";
489 };
491 mmc2: mmc@11250000 {
492 compatible = "mediatek,mt8173-mmc",
493 "mediatek,mt8135-mmc";
494 reg = <0 0x11250000 0 0x1000>;
495 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
496 clocks = <&pericfg CLK_PERI_MSDC30_2>,
497 <&topckgen CLK_TOP_AXI_SEL>;
498 clock-names = "source", "hclk";
499 status = "disabled";
500 };
502 mmc3: mmc@11260000 {
503 compatible = "mediatek,mt8173-mmc",
504 "mediatek,mt8135-mmc";
505 reg = <0 0x11260000 0 0x1000>;
506 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
507 clocks = <&pericfg CLK_PERI_MSDC30_3>,
508 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
509 clock-names = "source", "hclk";
510 status = "disabled";
511 };
513 mmsys: clock-controller@14000000 {
514 compatible = "mediatek,mt8173-mmsys", "syscon";
515 reg = <0 0x14000000 0 0x1000>;
516 #clock-cells = <1>;
517 };
519 imgsys: clock-controller@15000000 {
520 compatible = "mediatek,mt8173-imgsys", "syscon";
521 reg = <0 0x15000000 0 0x1000>;
522 #clock-cells = <1>;
523 };
525 vdecsys: clock-controller@16000000 {
526 compatible = "mediatek,mt8173-vdecsys", "syscon";
527 reg = <0 0x16000000 0 0x1000>;
528 #clock-cells = <1>;
529 };
531 vencsys: clock-controller@18000000 {
532 compatible = "mediatek,mt8173-vencsys", "syscon";
533 reg = <0 0x18000000 0 0x1000>;
534 #clock-cells = <1>;
535 };
537 vencltsys: clock-controller@19000000 {
538 compatible = "mediatek,mt8173-vencltsys", "syscon";
539 reg = <0 0x19000000 0 0x1000>;
540 #clock-cells = <1>;
541 };
542 };
543 };