| blob | 8d184ff196429f2d7300d4f03a4edde343235b5b |
1 /*
2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
18 / {
19 model = "Qualcomm Technologies, Inc. MSM8916";
20 compatible = "qcom,msm8916";
22 interrupt-parent = <&intc>;
24 #address-cells = <2>;
25 #size-cells = <2>;
27 aliases {
28 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
29 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
30 };
32 chosen { };
34 memory {
35 device_type = "memory";
36 /* We expect the bootloader to fill in the reg */
37 reg = <0 0 0 0>;
38 };
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a53", "arm,armv8";
47 reg = <0x0>;
48 };
50 CPU1: cpu@1 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a53", "arm,armv8";
53 reg = <0x1>;
54 };
56 CPU2: cpu@2 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a53", "arm,armv8";
59 reg = <0x2>;
60 };
62 CPU3: cpu@3 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a53", "arm,armv8";
65 reg = <0x3>;
66 };
67 };
69 timer {
70 compatible = "arm,armv8-timer";
71 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
75 };
77 soc: soc {
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0 0 0xffffffff>;
81 compatible = "simple-bus";
83 restart@4ab000 {
84 compatible = "qcom,pshold";
85 reg = <0x4ab000 0x4>;
86 };
88 msmgpio: pinctrl@1000000 {
89 compatible = "qcom,msm8916-pinctrl";
90 reg = <0x1000000 0x300000>;
91 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
92 gpio-controller;
93 #gpio-cells = <2>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
96 };
98 gcc: qcom,gcc@1800000 {
99 compatible = "qcom,gcc-msm8916";
100 #clock-cells = <1>;
101 #reset-cells = <1>;
102 #power-domain-cells = <1>;
103 reg = <0x1800000 0x80000>;
104 };
106 blsp1_uart1: serial@78af000 {
107 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
108 reg = <0x78af000 0x200>;
109 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
111 clock-names = "core", "iface";
112 status = "disabled";
113 };
115 blsp1_uart2: serial@78b0000 {
116 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
117 reg = <0x78b0000 0x200>;
118 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
120 clock-names = "core", "iface";
121 status = "disabled";
122 };
124 blsp_dma: dma@7884000 {
125 compatible = "qcom,bam-v1.7.0";
126 reg = <0x07884000 0x23000>;
127 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
129 clock-names = "bam_clk";
130 #dma-cells = <1>;
131 qcom,ee = <0>;
132 status = "disabled";
133 };
135 blsp_spi1: spi@78b5000 {
136 compatible = "qcom,spi-qup-v2.2.1";
137 reg = <0x078b5000 0x600>;
138 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
140 <&gcc GCC_BLSP1_AHB_CLK>;
141 clock-names = "core", "iface";
142 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
143 dma-names = "rx", "tx";
144 pinctrl-names = "default", "sleep";
145 pinctrl-0 = <&spi1_default>;
146 pinctrl-1 = <&spi1_sleep>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 status = "disabled";
150 };
152 blsp_spi2: spi@78b6000 {
153 compatible = "qcom,spi-qup-v2.2.1";
154 reg = <0x078b6000 0x600>;
155 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
157 <&gcc GCC_BLSP1_AHB_CLK>;
158 clock-names = "core", "iface";
159 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
160 dma-names = "rx", "tx";
161 pinctrl-names = "default", "sleep";
162 pinctrl-0 = <&spi2_default>;
163 pinctrl-1 = <&spi2_sleep>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 status = "disabled";
167 };
169 blsp_spi3: spi@78b7000 {
170 compatible = "qcom,spi-qup-v2.2.1";
171 reg = <0x078b7000 0x600>;
172 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
174 <&gcc GCC_BLSP1_AHB_CLK>;
175 clock-names = "core", "iface";
176 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
177 dma-names = "rx", "tx";
178 pinctrl-names = "default", "sleep";
179 pinctrl-0 = <&spi3_default>;
180 pinctrl-1 = <&spi3_sleep>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 status = "disabled";
184 };
186 blsp_spi4: spi@78b8000 {
187 compatible = "qcom,spi-qup-v2.2.1";
188 reg = <0x078b8000 0x600>;
189 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
191 <&gcc GCC_BLSP1_AHB_CLK>;
192 clock-names = "core", "iface";
193 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
194 dma-names = "rx", "tx";
195 pinctrl-names = "default", "sleep";
196 pinctrl-0 = <&spi4_default>;
197 pinctrl-1 = <&spi4_sleep>;
198 #address-cells = <1>;
199 #size-cells = <0>;
200 status = "disabled";
201 };
203 blsp_spi5: spi@78b9000 {
204 compatible = "qcom,spi-qup-v2.2.1";
205 reg = <0x078b9000 0x600>;
206 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
208 <&gcc GCC_BLSP1_AHB_CLK>;
209 clock-names = "core", "iface";
210 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
211 dma-names = "rx", "tx";
212 pinctrl-names = "default", "sleep";
213 pinctrl-0 = <&spi5_default>;
214 pinctrl-1 = <&spi5_sleep>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 status = "disabled";
218 };
220 blsp_spi6: spi@78ba000 {
221 compatible = "qcom,spi-qup-v2.2.1";
222 reg = <0x078ba000 0x600>;
223 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
225 <&gcc GCC_BLSP1_AHB_CLK>;
226 clock-names = "core", "iface";
227 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
228 dma-names = "rx", "tx";
229 pinctrl-names = "default", "sleep";
230 pinctrl-0 = <&spi6_default>;
231 pinctrl-1 = <&spi6_sleep>;
232 #address-cells = <1>;
233 #size-cells = <0>;
234 status = "disabled";
235 };
237 blsp_i2c2: i2c@78b6000 {
238 compatible = "qcom,i2c-qup-v2.2.1";
239 reg = <0x78b6000 0x1000>;
240 interrupts = <GIC_SPI 96 0>;
241 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
242 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
243 clock-names = "iface", "core";
244 pinctrl-names = "default", "sleep";
245 pinctrl-0 = <&i2c2_default>;
246 pinctrl-1 = <&i2c2_sleep>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 status = "disabled";
250 };
252 blsp_i2c4: i2c@78b8000 {
253 compatible = "qcom,i2c-qup-v2.2.1";
254 reg = <0x78b8000 0x1000>;
255 interrupts = <GIC_SPI 98 0>;
256 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
257 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
258 clock-names = "iface", "core";
259 pinctrl-names = "default", "sleep";
260 pinctrl-0 = <&i2c4_default>;
261 pinctrl-1 = <&i2c4_sleep>;
262 #address-cells = <1>;
263 #size-cells = <0>;
264 status = "disabled";
265 };
267 blsp_i2c6: i2c@78ba000 {
268 compatible = "qcom,i2c-qup-v2.2.1";
269 reg = <0x78ba000 0x1000>;
270 interrupts = <GIC_SPI 100 0>;
271 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
272 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
273 clock-names = "iface", "core";
274 pinctrl-names = "default", "sleep";
275 pinctrl-0 = <&i2c6_default>;
276 pinctrl-1 = <&i2c6_sleep>;
277 #address-cells = <1>;
278 #size-cells = <0>;
279 status = "disabled";
280 };
282 sdhc_1: sdhci@07824000 {
283 compatible = "qcom,sdhci-msm-v4";
284 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
285 reg-names = "hc_mem", "core_mem";
287 interrupts = <0 123 0>, <0 138 0>;
288 interrupt-names = "hc_irq", "pwr_irq";
289 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
290 <&gcc GCC_SDCC1_AHB_CLK>;
291 clock-names = "core", "iface";
292 bus-width = <8>;
293 non-removable;
294 status = "disabled";
295 };
297 sdhc_2: sdhci@07864000 {
298 compatible = "qcom,sdhci-msm-v4";
299 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
300 reg-names = "hc_mem", "core_mem";
302 interrupts = <0 125 0>, <0 221 0>;
303 interrupt-names = "hc_irq", "pwr_irq";
304 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
305 <&gcc GCC_SDCC2_AHB_CLK>;
306 clock-names = "core", "iface";
307 bus-width = <4>;
308 status = "disabled";
309 };
311 usb_dev: usb@78d9000 {
312 compatible = "qcom,ci-hdrc";
313 reg = <0x78d9000 0x400>;
314 dr_mode = "peripheral";
315 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
316 usb-phy = <&usb_otg>;
317 status = "disabled";
318 };
320 usb_host: ehci@78d9000 {
321 compatible = "qcom,ehci-host";
322 reg = <0x78d9000 0x400>;
323 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
324 usb-phy = <&usb_otg>;
325 status = "disabled";
326 };
328 usb_otg: phy@78d9000 {
329 compatible = "qcom,usb-otg-snps";
330 reg = <0x78d9000 0x400>;
331 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
332 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
334 qcom,vdd-levels = <1 5 7>;
335 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
336 dr_mode = "peripheral";
337 qcom,otg-control = <2>; // PMIC
339 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
340 <&gcc GCC_USB_HS_SYSTEM_CLK>,
341 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
342 clock-names = "iface", "core", "sleep";
344 resets = <&gcc GCC_USB2A_PHY_BCR>,
345 <&gcc GCC_USB_HS_BCR>;
346 reset-names = "phy", "link";
347 status = "disabled";
348 };
350 intc: interrupt-controller@b000000 {
351 compatible = "qcom,msm-qgic2";
352 interrupt-controller;
353 #interrupt-cells = <3>;
354 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
355 };
357 timer@b020000 {
358 #address-cells = <1>;
359 #size-cells = <1>;
360 ranges;
361 compatible = "arm,armv7-timer-mem";
362 reg = <0xb020000 0x1000>;
363 clock-frequency = <19200000>;
365 frame@b021000 {
366 frame-number = <0>;
367 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
369 reg = <0xb021000 0x1000>,
370 <0xb022000 0x1000>;
371 };
373 frame@b023000 {
374 frame-number = <1>;
375 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
376 reg = <0xb023000 0x1000>;
377 status = "disabled";
378 };
380 frame@b024000 {
381 frame-number = <2>;
382 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
383 reg = <0xb024000 0x1000>;
384 status = "disabled";
385 };
387 frame@b025000 {
388 frame-number = <3>;
389 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
390 reg = <0xb025000 0x1000>;
391 status = "disabled";
392 };
394 frame@b026000 {
395 frame-number = <4>;
396 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
397 reg = <0xb026000 0x1000>;
398 status = "disabled";
399 };
401 frame@b027000 {
402 frame-number = <5>;
403 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
404 reg = <0xb027000 0x1000>;
405 status = "disabled";
406 };
408 frame@b028000 {
409 frame-number = <6>;
410 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
411 reg = <0xb028000 0x1000>;
412 status = "disabled";
413 };
414 };
416 spmi_bus: spmi@200f000 {
417 compatible = "qcom,spmi-pmic-arb";
418 reg = <0x200f000 0x001000>,
419 <0x2400000 0x400000>,
420 <0x2c00000 0x400000>,
421 <0x3800000 0x200000>,
422 <0x200a000 0x002100>;
423 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
424 interrupt-names = "periph_irq";
425 interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
426 qcom,ee = <0>;
427 qcom,channel = <0>;
428 #address-cells = <2>;
429 #size-cells = <0>;
430 interrupt-controller;
431 #interrupt-cells = <4>;
432 };
434 rng@22000 {
435 compatible = "qcom,prng";
436 reg = <0x00022000 0x200>;
437 clocks = <&gcc GCC_PRNG_AHB_CLK>;
438 clock-names = "core";
439 };
440 };
441 };
443 #include "msm8916-pins.dtsi"