arch/arm64/boot/dts/sprd/sc9836.dtsi

   1 /*
   2  * Spreadtrum SC9836 SoC DTS file
   3  *
   4  * Copyright (C) 2014, Spreadtrum Communications Inc.
   5  *
   6  * This file is licensed under a dual GPLv2 or X11 license.
   7  */
   8
   9 #include "sharkl64.dtsi"
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         compatible = "sprd,sc9836";
  14
  15         cpus {
  16                 #address-cells = <2>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         reg = <0x0 0x0>;
  23                         enable-method = "psci";
  24                 };
  25
  26                 cpu1: cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a53", "arm,armv8";
  29                         reg = <0x0 0x1>;
  30                         enable-method = "psci";
  31                 };
  32
  33                 cpu2: cpu@2 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53", "arm,armv8";
  36                         reg = <0x0 0x2>;
  37                         enable-method = "psci";
  38                 };
  39
  40                 cpu3: cpu@3 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53", "arm,armv8";
  43                         reg = <0x0 0x3>;
  44                         enable-method = "psci";
  45                 };
  46         };
  47
  48         etf@10003000 {
  49                 compatible = "arm,coresight-tmc", "arm,primecell";
  50                 reg = <0 0x10003000 0 0x1000>;
  51                 clocks = <&clk26mhz>;
  52                 clock-names = "apb_pclk";
  53                 port {
  54                         etf_in: endpoint {
  55                                 slave-mode;
  56                                 remote-endpoint = <&funnel_out_port0>;
  57                         };
  58                 };
  59         };
  60
  61         funnel@10001000 {
  62                 compatible = "arm,coresight-funnel", "arm,primecell";
  63                 reg = <0 0x10001000 0 0x1000>;
  64                 clocks = <&clk26mhz>;
  65                 clock-names = "apb_pclk";
  66                 ports {
  67                         #address-cells = <1>;
  68                         #size-cells = <0>;
  69
  70                         /* funnel output port */
  71                         port@0 {
  72                                 reg = <0>;
  73                                 funnel_out_port0: endpoint {
  74                                         remote-endpoint = <&etf_in>;
  75                                 };
  76                         };
  77
  78                         /* funnel input port 0-4 */
  79                         port@1 {
  80                                 reg = <0>;
  81                                 funnel_in_port0: endpoint {
  82                                         slave-mode;
  83                                         remote-endpoint = <&etm0_out>;
  84                                 };
  85                         };
  86
  87                         port@2 {
  88                                 reg = <1>;
  89                                 funnel_in_port1: endpoint {
  90                                         slave-mode;
  91                                         remote-endpoint = <&etm1_out>;
  92                                 };
  93                         };
  94
  95                         port@3 {
  96                                 reg = <2>;
  97                                 funnel_in_port2: endpoint {
  98                                         slave-mode;
  99                                         remote-endpoint = <&etm2_out>;
 100                                 };
 101                         };
 102
 103                         port@4 {
 104                                 reg = <3>;
 105                                 funnel_in_port3: endpoint {
 106                                         slave-mode;
 107                                         remote-endpoint = <&etm3_out>;
 108                                 };
 109                         };
 110
 111                         port@5 {
 112                                 reg = <4>;
 113                                 funnel_in_port4: endpoint {
 114                                         slave-mode;
 115                                         remote-endpoint = <&stm_out>;
 116                                 };
 117                         };
 118                         /* Other input ports aren't connected to anyone */
 119                 };
 120         };
 121
 122         etm@10440000 {
 123                 compatible = "arm,coresight-etm4x", "arm,primecell";
 124                 reg = <0 0x10440000 0 0x1000>;
 125
 126                 cpu = <&cpu0>;
 127                 clocks = <&clk26mhz>;
 128                 clock-names = "apb_pclk";
 129                 port {
 130                         etm0_out: endpoint {
 131                                 remote-endpoint = <&funnel_in_port0>;
 132                         };
 133                 };
 134         };
 135
 136         etm@10540000 {
 137                 compatible = "arm,coresight-etm4x", "arm,primecell";
 138                 reg = <0 0x10540000 0 0x1000>;
 139
 140                 cpu = <&cpu1>;
 141                 clocks = <&clk26mhz>;
 142                 clock-names = "apb_pclk";
 143                 port {
 144                         etm1_out: endpoint {
 145                                 remote-endpoint = <&funnel_in_port1>;
 146                         };
 147                 };
 148         };
 149
 150         etm@10640000 {
 151                 compatible = "arm,coresight-etm4x", "arm,primecell";
 152                 reg = <0 0x10640000 0 0x1000>;
 153
 154                 cpu = <&cpu2>;
 155                 clocks = <&clk26mhz>;
 156                 clock-names = "apb_pclk";
 157                 port {
 158                         etm2_out: endpoint {
 159                                 remote-endpoint = <&funnel_in_port2>;
 160                         };
 161                 };
 162         };
 163
 164         etm@10740000 {
 165                 compatible = "arm,coresight-etm4x", "arm,primecell";
 166                 reg = <0 0x10740000 0 0x1000>;
 167
 168                 cpu = <&cpu3>;
 169                 clocks = <&clk26mhz>;
 170                 clock-names = "apb_pclk";
 171                 port {
 172                         etm3_out: endpoint {
 173                                 remote-endpoint = <&funnel_in_port3>;
 174                         };
 175                 };
 176         };
 177
 178         stm@10006000 {
 179                 compatible = "arm,coresight-stm", "arm,primecell";
 180                 reg = <0 0x10006000 0 0x1000>,
 181                       <0 0x01000000 0 0x180000>;
 182                 reg-names = "stm-base", "stm-stimulus-base";
 183                 clocks = <&clk26mhz>;
 184                 clock-names = "apb_pclk";
 185                 port {
 186                         stm_out: endpoint {
 187                                 remote-endpoint = <&funnel_in_port4>;
 188                         };
 189                 };
 190         };
 191
 192         gic: interrupt-controller@12001000 {
 193                 compatible = "arm,gic-400";
 194                 reg = <0 0x12001000 0 0x1000>,
 195                       <0 0x12002000 0 0x2000>,
 196                       <0 0x12004000 0 0x2000>,
 197                       <0 0x12006000 0 0x2000>;
 198                 #interrupt-cells = <3>;
 199                 interrupt-controller;
 200                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 201         };
 202
 203         psci {
 204                 compatible      = "arm,psci";
 205                 method          = "smc";
 206                 cpu_on          = <0xc4000003>;
 207                 cpu_off         = <0x84000002>;
 208                 cpu_suspend     = <0xc4000001>;
 209         };
 210
 211         timer {
 212                 compatible = "arm,armv8-timer";
 213                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 214                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 215                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 216                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 217         };
 218 };