arch/arm64/include/asm/hw_breakpoint.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_HW_BREAKPOINT_H
  17 #define __ASM_HW_BREAKPOINT_H
  18
  19 #include <asm/cputype.h>
  20 #include <asm/cpufeature.h>
  21
  22 #ifdef __KERNEL__
  23
  24 struct arch_hw_breakpoint_ctrl {
  25         u32 __reserved  : 19,
  26         len             : 8,
  27         type            : 2,
  28         privilege       : 2,
  29         enabled         : 1;
  30 };
  31
  32 struct arch_hw_breakpoint {
  33         u64 address;
  34         u64 trigger;
  35         struct arch_hw_breakpoint_ctrl ctrl;
  36 };
  37
  38 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
  39 {
  40         return (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
  41                 ctrl.enabled;
  42 }
  43
  44 static inline void decode_ctrl_reg(u32 reg,
  45                                    struct arch_hw_breakpoint_ctrl *ctrl)
  46 {
  47         ctrl->enabled   = reg & 0x1;
  48         reg >>= 1;
  49         ctrl->privilege = reg & 0x3;
  50         reg >>= 2;
  51         ctrl->type      = reg & 0x3;
  52         reg >>= 2;
  53         ctrl->len       = reg & 0xff;
  54 }
  55
  56 /* Breakpoint */
  57 #define ARM_BREAKPOINT_EXECUTE  0
  58
  59 /* Watchpoints */
  60 #define ARM_BREAKPOINT_LOAD     1
  61 #define ARM_BREAKPOINT_STORE    2
  62 #define AARCH64_ESR_ACCESS_MASK (1 << 6)
  63
  64 /* Privilege Levels */
  65 #define AARCH64_BREAKPOINT_EL1  1
  66 #define AARCH64_BREAKPOINT_EL0  2
  67
  68 /* Lengths */
  69 #define ARM_BREAKPOINT_LEN_1    0x1
  70 #define ARM_BREAKPOINT_LEN_2    0x3
  71 #define ARM_BREAKPOINT_LEN_4    0xf
  72 #define ARM_BREAKPOINT_LEN_8    0xff
  73
  74 /* Kernel stepping */
  75 #define ARM_KERNEL_STEP_NONE    0
  76 #define ARM_KERNEL_STEP_ACTIVE  1
  77 #define ARM_KERNEL_STEP_SUSPEND 2
  78
  79 /*
  80  * Limits.
  81  * Changing these will require modifications to the register accessors.
  82  */
  83 #define ARM_MAX_BRP             16
  84 #define ARM_MAX_WRP             16
  85
  86 /* Virtual debug register bases. */
  87 #define AARCH64_DBG_REG_BVR     0
  88 #define AARCH64_DBG_REG_BCR     (AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
  89 #define AARCH64_DBG_REG_WVR     (AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
  90 #define AARCH64_DBG_REG_WCR     (AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
  91
  92 /* Debug register names. */
  93 #define AARCH64_DBG_REG_NAME_BVR        "bvr"
  94 #define AARCH64_DBG_REG_NAME_BCR        "bcr"
  95 #define AARCH64_DBG_REG_NAME_WVR        "wvr"
  96 #define AARCH64_DBG_REG_NAME_WCR        "wcr"
  97
  98 /* Accessor macros for the debug registers. */
  99 #define AARCH64_DBG_READ(N, REG, VAL) do {\
 100         asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\
 101 } while (0)
 102
 103 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\
 104         asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\
 105 } while (0)
 106
 107 struct task_struct;
 108 struct notifier_block;
 109 struct perf_event;
 110 struct pmu;
 111
 112 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
 113                                   int *gen_len, int *gen_type);
 114 extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
 115 extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
 116 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
 117                                            unsigned long val, void *data);
 118
 119 extern int arch_install_hw_breakpoint(struct perf_event *bp);
 120 extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
 121 extern void hw_breakpoint_pmu_read(struct perf_event *bp);
 122 extern int hw_breakpoint_slots(int type);
 123
 124 #ifdef CONFIG_HAVE_HW_BREAKPOINT
 125 extern void hw_breakpoint_thread_switch(struct task_struct *next);
 126 extern void ptrace_hw_copy_thread(struct task_struct *task);
 127 #else
 128 static inline void hw_breakpoint_thread_switch(struct task_struct *next)
 129 {
 130 }
 131 static inline void ptrace_hw_copy_thread(struct task_struct *task)
 132 {
 133 }
 134 #endif
 135
 136 extern struct pmu perf_ops_bp;
 137
 138 /* Determine number of BRP registers available. */
 139 static inline int get_num_brps(void)
 140 {
 141         u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
 142         return 1 +
 143                 cpuid_feature_extract_unsigned_field(dfr0,
 144                                                 ID_AA64DFR0_BRPS_SHIFT);
 145 }
 146
 147 /* Determine number of WRP registers available. */
 148 static inline int get_num_wrps(void)
 149 {
 150         u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
 151         return 1 +
 152                 cpuid_feature_extract_unsigned_field(dfr0,
 153                                                 ID_AA64DFR0_WRPS_SHIFT);
 154 }
 155
 156 #endif  /* __KERNEL__ */
 157 #endif  /* __ASM_BREAKPOINT_H */