arch/ia64/include/asm/native/inst.h

   1 /******************************************************************************
   2  * arch/ia64/include/asm/native/inst.h
   3  *
   4  * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #define DO_SAVE_MIN             IA64_NATIVE_DO_SAVE_MIN
  24
  25 #define MOV_FROM_IFA(reg)       \
  26         mov reg = cr.ifa
  27
  28 #define MOV_FROM_ITIR(reg)      \
  29         mov reg = cr.itir
  30
  31 #define MOV_FROM_ISR(reg)       \
  32         mov reg = cr.isr
  33
  34 #define MOV_FROM_IHA(reg)       \
  35         mov reg = cr.iha
  36
  37 #define MOV_FROM_IPSR(pred, reg)        \
  38 (pred)  mov reg = cr.ipsr
  39
  40 #define MOV_FROM_IIM(reg)       \
  41         mov reg = cr.iim
  42
  43 #define MOV_FROM_IIP(reg)       \
  44         mov reg = cr.iip
  45
  46 #define MOV_FROM_IVR(reg, clob) \
  47         mov reg = cr.ivr
  48
  49 #define MOV_FROM_PSR(pred, reg, clob)   \
  50 (pred)  mov reg = psr
  51
  52 #define MOV_FROM_ITC(pred, pred_clob, reg, clob)        \
  53 (pred)  mov reg = ar.itc
  54
  55 #define MOV_TO_IFA(reg, clob)   \
  56         mov cr.ifa = reg
  57
  58 #define MOV_TO_ITIR(pred, reg, clob)    \
  59 (pred)  mov cr.itir = reg
  60
  61 #define MOV_TO_IHA(pred, reg, clob)     \
  62 (pred)  mov cr.iha = reg
  63
  64 #define MOV_TO_IPSR(pred, reg, clob)            \
  65 (pred)  mov cr.ipsr = reg
  66
  67 #define MOV_TO_IFS(pred, reg, clob)     \
  68 (pred)  mov cr.ifs = reg
  69
  70 #define MOV_TO_IIP(reg, clob)   \
  71         mov cr.iip = reg
  72
  73 #define MOV_TO_KR(kr, reg, clob0, clob1)        \
  74         mov IA64_KR(kr) = reg
  75
  76 #define ITC_I(pred, reg, clob)  \
  77 (pred)  itc.i reg
  78
  79 #define ITC_D(pred, reg, clob)  \
  80 (pred)  itc.d reg
  81
  82 #define ITC_I_AND_D(pred_i, pred_d, reg, clob)  \
  83 (pred_i) itc.i reg;                             \
  84 (pred_d) itc.d reg
  85
  86 #define THASH(pred, reg0, reg1, clob)           \
  87 (pred)  thash reg0 = reg1
  88
  89 #define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1)            \
  90         ssm psr.ic | PSR_DEFAULT_BITS                                   \
  91         ;;                                                              \
  92         srlz.i /* guarantee that interruption collectin is on */        \
  93         ;;
  94
  95 #define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1)     \
  96         ssm psr.ic                              \
  97         ;;                                      \
  98         srlz.d
  99
 100 #define RSM_PSR_IC(clob)        \
 101         rsm psr.ic
 102
 103 #define SSM_PSR_I(pred, pred_clob, clob)        \
 104 (pred)  ssm psr.i
 105
 106 #define RSM_PSR_I(pred, clob0, clob1)   \
 107 (pred)  rsm psr.i
 108
 109 #define RSM_PSR_I_IC(clob0, clob1, clob2)       \
 110         rsm psr.i | psr.ic
 111
 112 #define RSM_PSR_DT              \
 113         rsm psr.dt
 114
 115 #define RSM_PSR_BE_I(clob0, clob1)      \
 116         rsm psr.be | psr.i
 117
 118 #define SSM_PSR_DT_AND_SRLZ_I   \
 119         ssm psr.dt              \
 120         ;;                      \
 121         srlz.i
 122
 123 #define BSW_0(clob0, clob1, clob2)      \
 124         bsw.0
 125
 126 #define BSW_1(clob0, clob1)     \
 127         bsw.1
 128
 129 #define COVER   \
 130         cover
 131
 132 #define RFI     \
 133         rfi