mm: hugetlb: fix hugepage memory leak caused by wrong reserve count
[linux/fpc-iii.git] / arch / mips / pci / fixup-cobalt.c
blobb3ab59318d91a7a2817e6615efba1ef3fc0a2c37
1 /*
2 * Cobalt Qube/Raq PCI support
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
8 * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
16 #include <asm/io.h>
17 #include <asm/gt64120.h>
19 #include <cobalt.h>
20 #include <irq.h>
23 * PCI slot numbers
25 #define COBALT_PCICONF_CPU 0x06
26 #define COBALT_PCICONF_ETH0 0x07
27 #define COBALT_PCICONF_RAQSCSI 0x08
28 #define COBALT_PCICONF_VIA 0x09
29 #define COBALT_PCICONF_PCISLOT 0x0A
30 #define COBALT_PCICONF_ETH1 0x0C
33 * The Cobalt board ID information. The boards have an ID number wired
34 * into the VIA that is available in the high nibble of register 94.
36 #define VIA_COBALT_BRD_ID_REG 0x94
37 #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
39 static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
41 if (dev->devfn == PCI_DEVFN(0, 0) &&
42 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
44 dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
46 printk(KERN_INFO "Galileo: fixed bridge class\n");
50 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
51 qube_raq_galileo_early_fixup);
53 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
55 unsigned short cfgword;
56 unsigned char lt;
58 /* Enable Bus Mastering and fast back to back. */
59 pci_read_config_word(dev, PCI_COMMAND, &cfgword);
60 cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
61 pci_write_config_word(dev, PCI_COMMAND, cfgword);
63 /* Enable both ide interfaces. ROM only enables primary one. */
64 pci_write_config_byte(dev, 0x40, 0xb);
66 /* Set latency timer to reasonable value. */
67 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
68 if (lt < 64)
69 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
70 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
73 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
74 qube_raq_via_bmIDE_fixup);
76 static void qube_raq_galileo_fixup(struct pci_dev *dev)
78 if (dev->devfn != PCI_DEVFN(0, 0))
79 return;
81 /* Fix PCI latency-timer and cache-line-size values in Galileo
82 * host bridge.
84 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
85 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
88 * The code described by the comment below has been removed
89 * as it causes bus mastering by the Ethernet controllers
90 * to break under any kind of network load. We always set
91 * the retry timeouts to their maximum.
93 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
95 * On all machines prior to Q2, we had the STOP line disconnected
96 * from Galileo to VIA on PCI. The new Galileo does not function
97 * correctly unless we have it connected.
99 * Therefore we must set the disconnect/retry cycle values to
100 * something sensible when using the new Galileo.
103 printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
105 #if 0
106 if (dev->revision >= 0x10) {
107 /* New Galileo, assumes PCI stop line to VIA is connected. */
108 GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
109 } else if (dev->revision == 0x1 || dev->revision == 0x2)
110 #endif
112 signed int timeo;
113 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
114 timeo = GT_READ(GT_PCI0_TOR_OFS);
115 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
116 GT_WRITE(GT_PCI0_TOR_OFS,
117 (0xff << 16) | /* retry count */
118 (0xff << 8) | /* timeout 1 */
119 0xff); /* timeout 0 */
121 /* enable PCI retry exceeded interrupt */
122 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
127 qube_raq_galileo_fixup);
129 int cobalt_board_id;
131 static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
133 u8 id;
134 int retval;
136 retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
137 if (retval) {
138 panic("Cannot read board ID");
139 return;
142 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
144 printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
148 qube_raq_via_board_id_fixup);
150 static char irq_tab_qube1[] __initdata = {
151 [COBALT_PCICONF_CPU] = 0,
152 [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
153 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
154 [COBALT_PCICONF_VIA] = 0,
155 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
156 [COBALT_PCICONF_ETH1] = 0
159 static char irq_tab_cobalt[] __initdata = {
160 [COBALT_PCICONF_CPU] = 0,
161 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
162 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
163 [COBALT_PCICONF_VIA] = 0,
164 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
165 [COBALT_PCICONF_ETH1] = ETH1_IRQ
168 static char irq_tab_raq2[] __initdata = {
169 [COBALT_PCICONF_CPU] = 0,
170 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
171 [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
172 [COBALT_PCICONF_VIA] = 0,
173 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
174 [COBALT_PCICONF_ETH1] = ETH1_IRQ
177 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
179 if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
180 return irq_tab_qube1[slot];
182 if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
183 return irq_tab_raq2[slot];
185 return irq_tab_cobalt[slot];
188 /* Do platform specific device initialization at pci_enable_device() time */
189 int pcibios_plat_dev_init(struct pci_dev *dev)
191 return 0;