drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32
  33 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  34 {
  35         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  36
  37         if (robj) {
  38                 if (robj->gem_base.import_attach)
  39                         drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
  40                 amdgpu_mn_unregister(robj);
  41                 amdgpu_bo_unref(&robj);
  42         }
  43 }
  44
  45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  46                                 int alignment, u32 initial_domain,
  47                                 u64 flags, bool kernel,
  48                                 struct drm_gem_object **obj)
  49 {
  50         struct amdgpu_bo *robj;
  51         unsigned long max_size;
  52         int r;
  53
  54         *obj = NULL;
  55         /* At least align on page size */
  56         if (alignment < PAGE_SIZE) {
  57                 alignment = PAGE_SIZE;
  58         }
  59
  60         if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
  61                 /* Maximum bo size is the unpinned gtt size since we use the gtt to
  62                  * handle vram to system pool migrations.
  63                  */
  64                 max_size = adev->mc.gtt_size - adev->gart_pin_size;
  65                 if (size > max_size) {
  66                         DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
  67                                   size >> 20, max_size >> 20);
  68                         return -ENOMEM;
  69                 }
  70         }
  71 retry:
  72         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
  73                              flags, NULL, NULL, &robj);
  74         if (r) {
  75                 if (r != -ERESTARTSYS) {
  76                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  77                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  78                                 goto retry;
  79                         }
  80                         DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  81                                   size, initial_domain, alignment, r);
  82                 }
  83                 return r;
  84         }
  85         *obj = &robj->gem_base;
  86         robj->pid = task_pid_nr(current);
  87
  88         mutex_lock(&adev->gem.mutex);
  89         list_add_tail(&robj->list, &adev->gem.objects);
  90         mutex_unlock(&adev->gem.mutex);
  91
  92         return 0;
  93 }
  94
  95 int amdgpu_gem_init(struct amdgpu_device *adev)
  96 {
  97         INIT_LIST_HEAD(&adev->gem.objects);
  98         return 0;
  99 }
 100
 101 void amdgpu_gem_fini(struct amdgpu_device *adev)
 102 {
 103         amdgpu_bo_force_delete(adev);
 104 }
 105
 106 /*
 107  * Call from drm_gem_handle_create which appear in both new and open ioctl
 108  * case.
 109  */
 110 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
 111 {
 112         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
 113         struct amdgpu_device *adev = rbo->adev;
 114         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 115         struct amdgpu_vm *vm = &fpriv->vm;
 116         struct amdgpu_bo_va *bo_va;
 117         int r;
 118         r = amdgpu_bo_reserve(rbo, false);
 119         if (r)
 120                 return r;
 121
 122         bo_va = amdgpu_vm_bo_find(vm, rbo);
 123         if (!bo_va) {
 124                 bo_va = amdgpu_vm_bo_add(adev, vm, rbo);
 125         } else {
 126                 ++bo_va->ref_count;
 127         }
 128         amdgpu_bo_unreserve(rbo);
 129         return 0;
 130 }
 131
 132 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 133                              struct drm_file *file_priv)
 134 {
 135         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
 136         struct amdgpu_device *adev = rbo->adev;
 137         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 138         struct amdgpu_vm *vm = &fpriv->vm;
 139         struct amdgpu_bo_va *bo_va;
 140         int r;
 141         r = amdgpu_bo_reserve(rbo, true);
 142         if (r) {
 143                 dev_err(adev->dev, "leaking bo va because "
 144                         "we fail to reserve bo (%d)\n", r);
 145                 return;
 146         }
 147         bo_va = amdgpu_vm_bo_find(vm, rbo);
 148         if (bo_va) {
 149                 if (--bo_va->ref_count == 0) {
 150                         amdgpu_vm_bo_rmv(adev, bo_va);
 151                 }
 152         }
 153         amdgpu_bo_unreserve(rbo);
 154 }
 155
 156 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
 157 {
 158         if (r == -EDEADLK) {
 159                 r = amdgpu_gpu_reset(adev);
 160                 if (!r)
 161                         r = -EAGAIN;
 162         }
 163         return r;
 164 }
 165
 166 /*
 167  * GEM ioctls.
 168  */
 169 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 170                             struct drm_file *filp)
 171 {
 172         struct amdgpu_device *adev = dev->dev_private;
 173         union drm_amdgpu_gem_create *args = data;
 174         uint64_t size = args->in.bo_size;
 175         struct drm_gem_object *gobj;
 176         uint32_t handle;
 177         bool kernel = false;
 178         int r;
 179
 180         /* create a gem object to contain this object in */
 181         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 182             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 183                 kernel = true;
 184                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
 185                         size = size << AMDGPU_GDS_SHIFT;
 186                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
 187                         size = size << AMDGPU_GWS_SHIFT;
 188                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
 189                         size = size << AMDGPU_OA_SHIFT;
 190                 else {
 191                         r = -EINVAL;
 192                         goto error_unlock;
 193                 }
 194         }
 195         size = roundup(size, PAGE_SIZE);
 196
 197         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 198                                      (u32)(0xffffffff & args->in.domains),
 199                                      args->in.domain_flags,
 200                                      kernel, &gobj);
 201         if (r)
 202                 goto error_unlock;
 203
 204         r = drm_gem_handle_create(filp, gobj, &handle);
 205         /* drop reference from allocate - handle holds it now */
 206         drm_gem_object_unreference_unlocked(gobj);
 207         if (r)
 208                 goto error_unlock;
 209
 210         memset(args, 0, sizeof(*args));
 211         args->out.handle = handle;
 212         return 0;
 213
 214 error_unlock:
 215         r = amdgpu_gem_handle_lockup(adev, r);
 216         return r;
 217 }
 218
 219 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 220                              struct drm_file *filp)
 221 {
 222         struct amdgpu_device *adev = dev->dev_private;
 223         struct drm_amdgpu_gem_userptr *args = data;
 224         struct drm_gem_object *gobj;
 225         struct amdgpu_bo *bo;
 226         uint32_t handle;
 227         int r;
 228
 229         if (offset_in_page(args->addr | args->size))
 230                 return -EINVAL;
 231
 232         /* reject unknown flag values */
 233         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 234             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 235             AMDGPU_GEM_USERPTR_REGISTER))
 236                 return -EINVAL;
 237
 238         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && (
 239              !(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) ||
 240              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER))) {
 241
 242                 /* if we want to write to it we must require anonymous
 243                    memory and install a MMU notifier */
 244                 return -EACCES;
 245         }
 246
 247         /* create a gem object to contain this object in */
 248         r = amdgpu_gem_object_create(adev, args->size, 0,
 249                                      AMDGPU_GEM_DOMAIN_CPU, 0,
 250                                      0, &gobj);
 251         if (r)
 252                 goto handle_lockup;
 253
 254         bo = gem_to_amdgpu_bo(gobj);
 255         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 256         if (r)
 257                 goto release_object;
 258
 259         if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
 260                 r = amdgpu_mn_register(bo, args->addr);
 261                 if (r)
 262                         goto release_object;
 263         }
 264
 265         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 266                 down_read(&current->mm->mmap_sem);
 267                 r = amdgpu_bo_reserve(bo, true);
 268                 if (r) {
 269                         up_read(&current->mm->mmap_sem);
 270                         goto release_object;
 271                 }
 272
 273                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 274                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 275                 amdgpu_bo_unreserve(bo);
 276                 up_read(&current->mm->mmap_sem);
 277                 if (r)
 278                         goto release_object;
 279         }
 280
 281         r = drm_gem_handle_create(filp, gobj, &handle);
 282         /* drop reference from allocate - handle holds it now */
 283         drm_gem_object_unreference_unlocked(gobj);
 284         if (r)
 285                 goto handle_lockup;
 286
 287         args->handle = handle;
 288         return 0;
 289
 290 release_object:
 291         drm_gem_object_unreference_unlocked(gobj);
 292
 293 handle_lockup:
 294         r = amdgpu_gem_handle_lockup(adev, r);
 295
 296         return r;
 297 }
 298
 299 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 300                           struct drm_device *dev,
 301                           uint32_t handle, uint64_t *offset_p)
 302 {
 303         struct drm_gem_object *gobj;
 304         struct amdgpu_bo *robj;
 305
 306         gobj = drm_gem_object_lookup(dev, filp, handle);
 307         if (gobj == NULL) {
 308                 return -ENOENT;
 309         }
 310         robj = gem_to_amdgpu_bo(gobj);
 311         if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) ||
 312             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 313                 drm_gem_object_unreference_unlocked(gobj);
 314                 return -EPERM;
 315         }
 316         *offset_p = amdgpu_bo_mmap_offset(robj);
 317         drm_gem_object_unreference_unlocked(gobj);
 318         return 0;
 319 }
 320
 321 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 322                           struct drm_file *filp)
 323 {
 324         union drm_amdgpu_gem_mmap *args = data;
 325         uint32_t handle = args->in.handle;
 326         memset(args, 0, sizeof(*args));
 327         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 328 }
 329
 330 /**
 331  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 332  *
 333  * @timeout_ns: timeout in ns
 334  *
 335  * Calculate the timeout in jiffies from an absolute timeout in ns.
 336  */
 337 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 338 {
 339         unsigned long timeout_jiffies;
 340         ktime_t timeout;
 341
 342         /* clamp timeout if it's to large */
 343         if (((int64_t)timeout_ns) < 0)
 344                 return MAX_SCHEDULE_TIMEOUT;
 345
 346         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 347         if (ktime_to_ns(timeout) < 0)
 348                 return 0;
 349
 350         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 351         /*  clamp timeout to avoid unsigned-> signed overflow */
 352         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 353                 return MAX_SCHEDULE_TIMEOUT - 1;
 354
 355         return timeout_jiffies;
 356 }
 357
 358 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 359                               struct drm_file *filp)
 360 {
 361         struct amdgpu_device *adev = dev->dev_private;
 362         union drm_amdgpu_gem_wait_idle *args = data;
 363         struct drm_gem_object *gobj;
 364         struct amdgpu_bo *robj;
 365         uint32_t handle = args->in.handle;
 366         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 367         int r = 0;
 368         long ret;
 369
 370         gobj = drm_gem_object_lookup(dev, filp, handle);
 371         if (gobj == NULL) {
 372                 return -ENOENT;
 373         }
 374         robj = gem_to_amdgpu_bo(gobj);
 375         if (timeout == 0)
 376                 ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
 377         else
 378                 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout);
 379
 380         /* ret == 0 means not signaled,
 381          * ret > 0 means signaled
 382          * ret < 0 means interrupted before timeout
 383          */
 384         if (ret >= 0) {
 385                 memset(args, 0, sizeof(*args));
 386                 args->out.status = (ret == 0);
 387         } else
 388                 r = ret;
 389
 390         drm_gem_object_unreference_unlocked(gobj);
 391         r = amdgpu_gem_handle_lockup(adev, r);
 392         return r;
 393 }
 394
 395 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 396                                 struct drm_file *filp)
 397 {
 398         struct drm_amdgpu_gem_metadata *args = data;
 399         struct drm_gem_object *gobj;
 400         struct amdgpu_bo *robj;
 401         int r = -1;
 402
 403         DRM_DEBUG("%d \n", args->handle);
 404         gobj = drm_gem_object_lookup(dev, filp, args->handle);
 405         if (gobj == NULL)
 406                 return -ENOENT;
 407         robj = gem_to_amdgpu_bo(gobj);
 408
 409         r = amdgpu_bo_reserve(robj, false);
 410         if (unlikely(r != 0))
 411                 goto out;
 412
 413         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 414                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 415                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 416                                            sizeof(args->data.data),
 417                                            &args->data.data_size_bytes,
 418                                            &args->data.flags);
 419         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 420                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 421                         r = -EINVAL;
 422                         goto unreserve;
 423                 }
 424                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 425                 if (!r)
 426                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 427                                                    args->data.data_size_bytes,
 428                                                    args->data.flags);
 429         }
 430
 431 unreserve:
 432         amdgpu_bo_unreserve(robj);
 433 out:
 434         drm_gem_object_unreference_unlocked(gobj);
 435         return r;
 436 }
 437
 438 /**
 439  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 440  *
 441  * @adev: amdgpu_device pointer
 442  * @bo_va: bo_va to update
 443  *
 444  * Update the bo_va directly after setting it's address. Errors are not
 445  * vital here, so they are not reported back to userspace.
 446  */
 447 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 448                                     struct amdgpu_bo_va *bo_va, uint32_t operation)
 449 {
 450         struct ttm_validate_buffer tv, *entry;
 451         struct amdgpu_bo_list_entry *vm_bos;
 452         struct ww_acquire_ctx ticket;
 453         struct list_head list, duplicates;
 454         unsigned domain;
 455         int r;
 456
 457         INIT_LIST_HEAD(&list);
 458         INIT_LIST_HEAD(&duplicates);
 459
 460         tv.bo = &bo_va->bo->tbo;
 461         tv.shared = true;
 462         list_add(&tv.head, &list);
 463
 464         vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list);
 465         if (!vm_bos)
 466                 return;
 467
 468         /* Provide duplicates to avoid -EALREADY */
 469         r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
 470         if (r)
 471                 goto error_free;
 472
 473         list_for_each_entry(entry, &list, head) {
 474                 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
 475                 /* if anything is swapped out don't swap it in here,
 476                    just abort and wait for the next CS */
 477                 if (domain == AMDGPU_GEM_DOMAIN_CPU)
 478                         goto error_unreserve;
 479         }
 480         list_for_each_entry(entry, &duplicates, head) {
 481                 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
 482                 /* if anything is swapped out don't swap it in here,
 483                    just abort and wait for the next CS */
 484                 if (domain == AMDGPU_GEM_DOMAIN_CPU)
 485                         goto error_unreserve;
 486         }
 487
 488         r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
 489         if (r)
 490                 goto error_unreserve;
 491
 492         r = amdgpu_vm_clear_freed(adev, bo_va->vm);
 493         if (r)
 494                 goto error_unreserve;
 495
 496         if (operation == AMDGPU_VA_OP_MAP)
 497                 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
 498
 499 error_unreserve:
 500         ttm_eu_backoff_reservation(&ticket, &list);
 501
 502 error_free:
 503         drm_free_large(vm_bos);
 504
 505         if (r && r != -ERESTARTSYS)
 506                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 507 }
 508
 509
 510
 511 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 512                           struct drm_file *filp)
 513 {
 514         struct drm_amdgpu_gem_va *args = data;
 515         struct drm_gem_object *gobj;
 516         struct amdgpu_device *adev = dev->dev_private;
 517         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 518         struct amdgpu_bo *rbo;
 519         struct amdgpu_bo_va *bo_va;
 520         struct ttm_validate_buffer tv, tv_pd;
 521         struct ww_acquire_ctx ticket;
 522         struct list_head list, duplicates;
 523         uint32_t invalid_flags, va_flags = 0;
 524         int r = 0;
 525
 526         if (!adev->vm_manager.enabled)
 527                 return -ENOTTY;
 528
 529         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 530                 dev_err(&dev->pdev->dev,
 531                         "va_address 0x%lX is in reserved area 0x%X\n",
 532                         (unsigned long)args->va_address,
 533                         AMDGPU_VA_RESERVED_SIZE);
 534                 return -EINVAL;
 535         }
 536
 537         invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
 538                         AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
 539         if ((args->flags & invalid_flags)) {
 540                 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
 541                         args->flags, invalid_flags);
 542                 return -EINVAL;
 543         }
 544
 545         switch (args->operation) {
 546         case AMDGPU_VA_OP_MAP:
 547         case AMDGPU_VA_OP_UNMAP:
 548                 break;
 549         default:
 550                 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
 551                         args->operation);
 552                 return -EINVAL;
 553         }
 554
 555         gobj = drm_gem_object_lookup(dev, filp, args->handle);
 556         if (gobj == NULL)
 557                 return -ENOENT;
 558         rbo = gem_to_amdgpu_bo(gobj);
 559         INIT_LIST_HEAD(&list);
 560         INIT_LIST_HEAD(&duplicates);
 561         tv.bo = &rbo->tbo;
 562         tv.shared = true;
 563         list_add(&tv.head, &list);
 564
 565         if (args->operation == AMDGPU_VA_OP_MAP) {
 566                 tv_pd.bo = &fpriv->vm.page_directory->tbo;
 567                 tv_pd.shared = true;
 568                 list_add(&tv_pd.head, &list);
 569         }
 570         r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
 571         if (r) {
 572                 drm_gem_object_unreference_unlocked(gobj);
 573                 return r;
 574         }
 575
 576         bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
 577         if (!bo_va) {
 578                 ttm_eu_backoff_reservation(&ticket, &list);
 579                 drm_gem_object_unreference_unlocked(gobj);
 580                 return -ENOENT;
 581         }
 582
 583         switch (args->operation) {
 584         case AMDGPU_VA_OP_MAP:
 585                 if (args->flags & AMDGPU_VM_PAGE_READABLE)
 586                         va_flags |= AMDGPU_PTE_READABLE;
 587                 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
 588                         va_flags |= AMDGPU_PTE_WRITEABLE;
 589                 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
 590                         va_flags |= AMDGPU_PTE_EXECUTABLE;
 591                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 592                                      args->offset_in_bo, args->map_size,
 593                                      va_flags);
 594                 break;
 595         case AMDGPU_VA_OP_UNMAP:
 596                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 597                 break;
 598         default:
 599                 break;
 600         }
 601         ttm_eu_backoff_reservation(&ticket, &list);
 602         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
 603                 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
 604
 605         drm_gem_object_unreference_unlocked(gobj);
 606         return r;
 607 }
 608
 609 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 610                         struct drm_file *filp)
 611 {
 612         struct drm_amdgpu_gem_op *args = data;
 613         struct drm_gem_object *gobj;
 614         struct amdgpu_bo *robj;
 615         int r;
 616
 617         gobj = drm_gem_object_lookup(dev, filp, args->handle);
 618         if (gobj == NULL) {
 619                 return -ENOENT;
 620         }
 621         robj = gem_to_amdgpu_bo(gobj);
 622
 623         r = amdgpu_bo_reserve(robj, false);
 624         if (unlikely(r))
 625                 goto out;
 626
 627         switch (args->op) {
 628         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 629                 struct drm_amdgpu_gem_create_in info;
 630                 void __user *out = (void __user *)(long)args->value;
 631
 632                 info.bo_size = robj->gem_base.size;
 633                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 634                 info.domains = robj->initial_domain;
 635                 info.domain_flags = robj->flags;
 636                 amdgpu_bo_unreserve(robj);
 637                 if (copy_to_user(out, &info, sizeof(info)))
 638                         r = -EFAULT;
 639                 break;
 640         }
 641         case AMDGPU_GEM_OP_SET_PLACEMENT:
 642                 if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) {
 643                         r = -EPERM;
 644                         amdgpu_bo_unreserve(robj);
 645                         break;
 646                 }
 647                 robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 648                                                       AMDGPU_GEM_DOMAIN_GTT |
 649                                                       AMDGPU_GEM_DOMAIN_CPU);
 650                 amdgpu_bo_unreserve(robj);
 651                 break;
 652         default:
 653                 amdgpu_bo_unreserve(robj);
 654                 r = -EINVAL;
 655         }
 656
 657 out:
 658         drm_gem_object_unreference_unlocked(gobj);
 659         return r;
 660 }
 661
 662 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 663                             struct drm_device *dev,
 664                             struct drm_mode_create_dumb *args)
 665 {
 666         struct amdgpu_device *adev = dev->dev_private;
 667         struct drm_gem_object *gobj;
 668         uint32_t handle;
 669         int r;
 670
 671         args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
 672         args->size = (u64)args->pitch * args->height;
 673         args->size = ALIGN(args->size, PAGE_SIZE);
 674
 675         r = amdgpu_gem_object_create(adev, args->size, 0,
 676                                      AMDGPU_GEM_DOMAIN_VRAM,
 677                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 678                                      ttm_bo_type_device,
 679                                      &gobj);
 680         if (r)
 681                 return -ENOMEM;
 682
 683         r = drm_gem_handle_create(file_priv, gobj, &handle);
 684         /* drop reference from allocate - handle holds it now */
 685         drm_gem_object_unreference_unlocked(gobj);
 686         if (r) {
 687                 return r;
 688         }
 689         args->handle = handle;
 690         return 0;
 691 }
 692
 693 #if defined(CONFIG_DEBUG_FS)
 694 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 695 {
 696         struct drm_info_node *node = (struct drm_info_node *)m->private;
 697         struct drm_device *dev = node->minor->dev;
 698         struct amdgpu_device *adev = dev->dev_private;
 699         struct amdgpu_bo *rbo;
 700         unsigned i = 0;
 701
 702         mutex_lock(&adev->gem.mutex);
 703         list_for_each_entry(rbo, &adev->gem.objects, list) {
 704                 unsigned domain;
 705                 const char *placement;
 706
 707                 domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type);
 708                 switch (domain) {
 709                 case AMDGPU_GEM_DOMAIN_VRAM:
 710                         placement = "VRAM";
 711                         break;
 712                 case AMDGPU_GEM_DOMAIN_GTT:
 713                         placement = " GTT";
 714                         break;
 715                 case AMDGPU_GEM_DOMAIN_CPU:
 716                 default:
 717                         placement = " CPU";
 718                         break;
 719                 }
 720                 seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
 721                            i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20,
 722                            placement, (unsigned long)rbo->pid);
 723                 i++;
 724         }
 725         mutex_unlock(&adev->gem.mutex);
 726         return 0;
 727 }
 728
 729 static struct drm_info_list amdgpu_debugfs_gem_list[] = {
 730         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 731 };
 732 #endif
 733
 734 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
 735 {
 736 #if defined(CONFIG_DEBUG_FS)
 737         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 738 #endif
 739         return 0;
 740 }