| blob | d98aa9d82fa193dc5e13a98a34df6ab87733e597 |
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #ifndef VI_H
24 #define VI_H
28 #define SDMA_MAX_INSTANCE 2
30 /* crtc instance offsets */
31 #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
32 #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
33 #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c)
34 #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c)
35 #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c)
36 #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c)
37 #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c)
39 /* dig instance offsets */
40 #define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00)
41 #define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00)
42 #define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00)
43 #define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00)
44 #define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00)
45 #define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00)
46 #define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00)
47 #define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00)
48 #define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00)
50 /* audio endpt instance offsets */
51 #define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8)
52 #define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8)
53 #define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8)
54 #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8)
55 #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8)
56 #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8)
57 #define AUD6_REGISTER_OFFSET (0x17c4 - 0x17a8)
59 /* hpd instance offsets */
60 #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898)
61 #define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
62 #define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
63 #define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
64 #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
65 #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
67 #define AMDGPU_NUM_OF_VMIDS 8
69 #define PIPEID(x) ((x) << 0)
70 #define MEID(x) ((x) << 2)
71 #define VMID(x) ((x) << 4)
72 #define QUEUEID(x) ((x) << 8)
74 #define RB_BITMAP_WIDTH_PER_SH 2
76 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
77 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
78 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
79 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
80 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
81 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
82 #define MC_SEQ_MISC0__MT__HBM 0x60000000
83 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
85 /*
86 * PM4
87 */
88 #define PACKET_TYPE0 0
89 #define PACKET_TYPE1 1
90 #define PACKET_TYPE2 2
91 #define PACKET_TYPE3 3
93 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
94 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
95 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
96 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
97 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
98 ((reg) & 0xFFFF) | \
99 ((n) & 0x3FFF) << 16)
100 #define CP_PACKET2 0x80000000
101 #define PACKET2_PAD_SHIFT 0
102 #define PACKET2_PAD_MASK (0x3fffffff << 0)
104 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
106 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
107 (((op) & 0xFF) << 8) | \
108 ((n) & 0x3FFF) << 16)
110 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
112 /* Packet 3 types */
113 #define PACKET3_NOP 0x10
114 #define PACKET3_SET_BASE 0x11
115 #define PACKET3_BASE_INDEX(x) ((x) << 0)
116 #define CE_PARTITION_BASE 3
117 #define PACKET3_CLEAR_STATE 0x12
118 #define PACKET3_INDEX_BUFFER_SIZE 0x13
119 #define PACKET3_DISPATCH_DIRECT 0x15
120 #define PACKET3_DISPATCH_INDIRECT 0x16
121 #define PACKET3_ATOMIC_GDS 0x1D
122 #define PACKET3_ATOMIC_MEM 0x1E
123 #define PACKET3_OCCLUSION_QUERY 0x1F
124 #define PACKET3_SET_PREDICATION 0x20
125 #define PACKET3_REG_RMW 0x21
126 #define PACKET3_COND_EXEC 0x22
127 #define PACKET3_PRED_EXEC 0x23
128 #define PACKET3_DRAW_INDIRECT 0x24
129 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
130 #define PACKET3_INDEX_BASE 0x26
131 #define PACKET3_DRAW_INDEX_2 0x27
132 #define PACKET3_CONTEXT_CONTROL 0x28
133 #define PACKET3_INDEX_TYPE 0x2A
134 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
135 #define PACKET3_DRAW_INDEX_AUTO 0x2D
136 #define PACKET3_NUM_INSTANCES 0x2F
137 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
138 #define PACKET3_INDIRECT_BUFFER_CONST 0x33
139 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
140 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
141 #define PACKET3_DRAW_PREAMBLE 0x36
142 #define PACKET3_WRITE_DATA 0x37
143 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
144 /* 0 - register
145 * 1 - memory (sync - via GRBM)
146 * 2 - gl2
147 * 3 - gds
148 * 4 - reserved
149 * 5 - memory (async - direct)
150 */
151 #define WR_ONE_ADDR (1 << 16)
152 #define WR_CONFIRM (1 << 20)
153 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
154 /* 0 - LRU
155 * 1 - Stream
156 */
157 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
158 /* 0 - me
159 * 1 - pfp
160 * 2 - ce
161 */
162 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
163 #define PACKET3_MEM_SEMAPHORE 0x39
164 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
167 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
168 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
169 #define PACKET3_WAIT_REG_MEM 0x3C
170 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
171 /* 0 - always
172 * 1 - <
173 * 2 - <=
174 * 3 - ==
175 * 4 - !=
176 * 5 - >=
177 * 6 - >
178 */
179 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
180 /* 0 - reg
181 * 1 - mem
182 */
183 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
184 /* 0 - wait_reg_mem
185 * 1 - wr_wait_wr_reg
186 */
187 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
188 /* 0 - me
189 * 1 - pfp
190 */
191 #define PACKET3_INDIRECT_BUFFER 0x3F
192 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
193 #define INDIRECT_BUFFER_VALID (1 << 23)
194 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
195 /* 0 - LRU
196 * 1 - Stream
197 * 2 - Bypass
198 */
199 #define PACKET3_COPY_DATA 0x40
200 #define PACKET3_PFP_SYNC_ME 0x42
201 #define PACKET3_SURFACE_SYNC 0x43
202 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
203 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
204 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
205 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
206 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
207 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
208 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
209 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
210 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
211 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
212 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
213 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
216 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
217 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
218 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
220 # define PACKET3_CB_ACTION_ENA (1 << 25)
221 # define PACKET3_DB_ACTION_ENA (1 << 26)
222 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
223 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
224 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
225 #define PACKET3_COND_WRITE 0x45
226 #define PACKET3_EVENT_WRITE 0x46
227 #define EVENT_TYPE(x) ((x) << 0)
228 #define EVENT_INDEX(x) ((x) << 8)
229 /* 0 - any non-TS event
230 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
231 * 2 - SAMPLE_PIPELINESTAT
232 * 3 - SAMPLE_STREAMOUTSTAT*
233 * 4 - *S_PARTIAL_FLUSH
234 * 5 - EOP events
235 * 6 - EOS events
236 */
237 #define PACKET3_EVENT_WRITE_EOP 0x47
238 #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
241 #define EOP_TCL1_ACTION_EN (1 << 16)
243 #define EOP_TCL2_VOLATILE (1 << 24)
244 #define EOP_CACHE_POLICY(x) ((x) << 25)
245 /* 0 - LRU
246 * 1 - Stream
247 * 2 - Bypass
248 */
249 #define DATA_SEL(x) ((x) << 29)
250 /* 0 - discard
251 * 1 - send low 32bit data
252 * 2 - send 64bit data
253 * 3 - send 64bit GPU counter value
254 * 4 - send 64bit sys counter value
255 */
256 #define INT_SEL(x) ((x) << 24)
257 /* 0 - none
258 * 1 - interrupt only (DATA_SEL = 0)
259 * 2 - interrupt when data write is confirmed
260 */
261 #define DST_SEL(x) ((x) << 16)
262 /* 0 - MC
263 * 1 - TC/L2
264 */
265 #define PACKET3_EVENT_WRITE_EOS 0x48
266 #define PACKET3_RELEASE_MEM 0x49
267 #define PACKET3_PREAMBLE_CNTL 0x4A
268 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
269 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
270 #define PACKET3_DMA_DATA 0x50
271 /* 1. header
272 * 2. CONTROL
273 * 3. SRC_ADDR_LO or DATA [31:0]
274 * 4. SRC_ADDR_HI [31:0]
275 * 5. DST_ADDR_LO [31:0]
276 * 6. DST_ADDR_HI [7:0]
277 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
278 */
279 /* CONTROL */
280 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
281 /* 0 - ME
282 * 1 - PFP
283 */
284 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
285 /* 0 - LRU
286 * 1 - Stream
287 * 2 - Bypass
288 */
289 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
290 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
291 /* 0 - DST_ADDR using DAS
292 * 1 - GDS
293 * 3 - DST_ADDR using L2
294 */
295 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
296 /* 0 - LRU
297 * 1 - Stream
298 * 2 - Bypass
299 */
300 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
301 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
302 /* 0 - SRC_ADDR using SAS
303 * 1 - GDS
304 * 2 - DATA
305 * 3 - SRC_ADDR using L2
306 */
307 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
308 /* COMMAND */
309 # define PACKET3_DMA_DATA_DIS_WC (1 << 21)
310 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
311 /* 0 - none
312 * 1 - 8 in 16
313 * 2 - 8 in 32
314 * 3 - 8 in 64
315 */
316 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
317 /* 0 - none
318 * 1 - 8 in 16
319 * 2 - 8 in 32
320 * 3 - 8 in 64
321 */
322 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
323 /* 0 - memory
324 * 1 - register
325 */
326 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
327 /* 0 - memory
328 * 1 - register
329 */
330 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
331 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
332 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
333 #define PACKET3_AQUIRE_MEM 0x58
334 #define PACKET3_REWIND 0x59
335 #define PACKET3_LOAD_UCONFIG_REG 0x5E
336 #define PACKET3_LOAD_SH_REG 0x5F
337 #define PACKET3_LOAD_CONFIG_REG 0x60
338 #define PACKET3_LOAD_CONTEXT_REG 0x61
339 #define PACKET3_SET_CONFIG_REG 0x68
340 #define PACKET3_SET_CONFIG_REG_START 0x00002000
341 #define PACKET3_SET_CONFIG_REG_END 0x00002c00
342 #define PACKET3_SET_CONTEXT_REG 0x69
343 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000
344 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400
345 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
346 #define PACKET3_SET_SH_REG 0x76
347 #define PACKET3_SET_SH_REG_START 0x00002c00
348 #define PACKET3_SET_SH_REG_END 0x00003000
349 #define PACKET3_SET_SH_REG_OFFSET 0x77
350 #define PACKET3_SET_QUEUE_REG 0x78
351 #define PACKET3_SET_UCONFIG_REG 0x79
352 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000
353 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400
354 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
355 #define PACKET3_SCRATCH_RAM_READ 0x7E
356 #define PACKET3_LOAD_CONST_RAM 0x80
357 #define PACKET3_WRITE_CONST_RAM 0x81
358 #define PACKET3_DUMP_CONST_RAM 0x83
359 #define PACKET3_INCREMENT_CE_COUNTER 0x84
360 #define PACKET3_INCREMENT_DE_COUNTER 0x85
361 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
362 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
363 #define PACKET3_SWITCH_BUFFER 0x8B
365 #define VCE_CMD_NO_OP 0x00000000
366 #define VCE_CMD_END 0x00000001
367 #define VCE_CMD_IB 0x00000002
368 #define VCE_CMD_FENCE 0x00000003
369 #define VCE_CMD_TRAP 0x00000004
370 #define VCE_CMD_IB_AUTO 0x00000005
371 #define VCE_CMD_SEMAPHORE 0x00000006
373 #endif