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mm: hugetlb: fix hugepage memory leak caused by wrong reserve count
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_display.c
blob22e86d2e408d9493e6c2ea6a60e689a5c03934a9
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
79 };
80
81 /* Cursor formats */
82 static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84 };
85
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137 {
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147 }
148
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151 {
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169 }
170
171 int
172 intel_pch_rawclk(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179 }
180
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212 }
213
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
215 {
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223 }
224
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
227 {
228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
233 }
234
235 static const intel_limit_t intel_limits_i8xx_dac = {
236 .dot = { .min = 25000, .max = 350000 },
237 .vco = { .min = 908000, .max = 1512000 },
238 .n = { .min = 2, .max = 16 },
239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
246 };
247
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259 };
260
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
272 };
273
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
298 };
299
300
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
313 },
314 };
315
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
327 };
328
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
340 },
341 };
342
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
354 },
355 };
356
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const intel_limit_t intel_limits_pineview_lvds = {
373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 /* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
390 static const intel_limit_t intel_limits_ironlake_dac = {
391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
401 };
402
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
414 };
415
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
427 };
428
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
451 .p1 = { .min = 2, .max = 6 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 static const intel_limit_t intel_limits_vlv = {
457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464 .vco = { .min = 4000000, .max = 6000000 },
465 .n = { .min = 1, .max = 7 },
466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
468 .p1 = { .min = 2, .max = 3 },
469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
470 };
471
472 static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
480 .vco = { .min = 4800000, .max = 6480000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486 };
487
488 static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
491 .vco = { .min = 4800000, .max = 6700000 },
492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498 };
499
500 static bool
501 needs_modeset(struct drm_crtc_state *state)
502 {
503 return drm_atomic_crtc_needs_modeset(state);
504 }
505
506 /**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
510 {
511 struct drm_device *dev = crtc->base.dev;
512 struct intel_encoder *encoder;
513
514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515 if (encoder->type == type)
516 return true;
517
518 return false;
519 }
520
521 /**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
529 {
530 struct drm_atomic_state *state = crtc_state->base.state;
531 struct drm_connector *connector;
532 struct drm_connector_state *connector_state;
533 struct intel_encoder *encoder;
534 int i, num_connectors = 0;
535
536 for_each_connector_in_state(state, connector, connector_state, i) {
537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
541
542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
544 return true;
545 }
546
547 WARN_ON(num_connectors == 0);
548
549 return false;
550 }
551
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
554 {
555 struct drm_device *dev = crtc_state->base.crtc->dev;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559 if (intel_is_dual_link_lvds(dev)) {
560 if (refclk == 100000)
561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
565 if (refclk == 100000)
566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
570 } else
571 limit = &intel_limits_ironlake_dac;
572
573 return limit;
574 }
575
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
578 {
579 struct drm_device *dev = crtc_state->base.crtc->dev;
580 const intel_limit_t *limit;
581
582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583 if (intel_is_dual_link_lvds(dev))
584 limit = &intel_limits_g4x_dual_channel_lvds;
585 else
586 limit = &intel_limits_g4x_single_channel_lvds;
587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 limit = &intel_limits_g4x_hdmi;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591 limit = &intel_limits_g4x_sdvo;
592 } else /* The option is for other outputs */
593 limit = &intel_limits_i9xx_sdvo;
594
595 return limit;
596 }
597
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
600 {
601 struct drm_device *dev = crtc_state->base.crtc->dev;
602 const intel_limit_t *limit;
603
604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
607 limit = intel_ironlake_limit(crtc_state, refclk);
608 else if (IS_G4X(dev)) {
609 limit = intel_g4x_limit(crtc_state);
610 } else if (IS_PINEVIEW(dev)) {
611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612 limit = &intel_limits_pineview_lvds;
613 else
614 limit = &intel_limits_pineview_sdvo;
615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
617 } else if (IS_VALLEYVIEW(dev)) {
618 limit = &intel_limits_vlv;
619 } else if (!IS_GEN2(dev)) {
620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
624 } else {
625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626 limit = &intel_limits_i8xx_lvds;
627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628 limit = &intel_limits_i8xx_dvo;
629 else
630 limit = &intel_limits_i8xx_dac;
631 }
632 return limit;
633 }
634
635 /*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
645 {
646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
648 if (WARN_ON(clock->n == 0 || clock->p == 0))
649 return 0;
650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
652
653 return clock->dot;
654 }
655
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657 {
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659 }
660
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
662 {
663 clock->m = i9xx_dpll_compute_m(clock);
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
666 return 0;
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
669
670 return clock->dot;
671 }
672
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
674 {
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
678 return 0;
679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
681
682 return clock->dot / 5;
683 }
684
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
686 {
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
690 return 0;
691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
694
695 return clock->dot / 5;
696 }
697
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
699 /**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
707 {
708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
715 INTELPllInvalid("m1 out of range\n");
716
717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734 INTELPllInvalid("dot out of range\n");
735
736 return true;
737 }
738
739 static int
740 i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
743 {
744 struct drm_device *dev = crtc_state->base.crtc->dev;
745
746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
747 /*
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
751 */
752 if (intel_is_dual_link_lvds(dev))
753 return limit->p2.p2_fast;
754 else
755 return limit->p2.p2_slow;
756 } else {
757 if (target < limit->p2.dot_limit)
758 return limit->p2.p2_slow;
759 else
760 return limit->p2.p2_fast;
761 }
762 }
763
764 static bool
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769 {
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 if (clock.m2 >= clock.m1)
783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
788 int this_err;
789
790 i9xx_calc_dpll_params(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809 }
810
811 static bool
812 pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
816 {
817 struct drm_device *dev = crtc_state->base.crtc->dev;
818 intel_clock_t clock;
819 int err = target;
820
821 memset(best_clock, 0, sizeof(*best_clock));
822
823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
833 int this_err;
834
835 pnv_calc_dpll_params(refclk, &clock);
836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
838 continue;
839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854 }
855
856 static bool
857 g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
861 {
862 struct drm_device *dev = crtc_state->base.crtc->dev;
863 intel_clock_t clock;
864 int max_n;
865 bool found = false;
866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
868
869 memset(best_clock, 0, sizeof(*best_clock));
870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
873 max_n = limit->n.max;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
885 i9xx_calc_dpll_params(refclk, &clock);
886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
888 continue;
889
890 this_err = abs(clock.dot - target);
891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
901 return found;
902 }
903
904 /*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913 {
914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942 }
943
944 static bool
945 vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
949 {
950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951 struct drm_device *dev = crtc->base.dev;
952 intel_clock_t clock;
953 unsigned int bestppm = 1000000;
954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
956 bool found = false;
957
958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
961
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967 clock.p = clock.p1 * clock.p2;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
970 unsigned int ppm;
971
972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
975 vlv_calc_dpll_params(refclk, &clock);
976
977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
979 continue;
980
981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
986
987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
990 }
991 }
992 }
993 }
994
995 return found;
996 }
997
998 static bool
999 chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003 {
1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005 struct drm_device *dev = crtc->base.dev;
1006 unsigned int best_error_ppm;
1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
1012 best_error_ppm = 1000000;
1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026 unsigned int error_ppm;
1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
1038 chv_calc_dpll_params(refclk, &clock);
1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
1050 }
1051 }
1052
1053 return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058 {
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1074 *
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
1081 */
1082 return intel_crtc->active && crtc->primary->state->fb &&
1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088 {
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092 return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
1108 msleep(5);
1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112 }
1113
1114 /*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1128 *
1129 */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132 struct drm_device *dev = crtc->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135 enum pipe pipe = crtc->pipe;
1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
1138 int reg = PIPECONF(cpu_transcoder);
1139
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
1143 WARN(1, "pipe_off wait timed out\n");
1144 } else {
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1148 }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153 return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159 {
1160 u32 val;
1161 bool cur_state;
1162
1163 val = I915_READ(DPLL(pipe));
1164 cur_state = !!(val & DPLL_VCO_ENABLE);
1165 I915_STATE_WARN(cur_state != state,
1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173 u32 val;
1174 bool cur_state;
1175
1176 mutex_lock(&dev_priv->sb_lock);
1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178 mutex_unlock(&dev_priv->sb_lock);
1179
1180 cur_state = val & DSI_PLL_VCO_EN;
1181 I915_STATE_WARN(cur_state != state,
1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193 if (crtc->config->shared_dpll < 0)
1194 return NULL;
1195
1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
1203 {
1204 bool cur_state;
1205 struct intel_dpll_hw_state hw_state;
1206
1207 if (WARN (!pll,
1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
1209 return;
1210
1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212 I915_STATE_WARN(cur_state != state,
1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 bool cur_state;
1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
1223
1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228 } else {
1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
1232 I915_STATE_WARN(cur_state != state,
1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(FDI_RX_CTL(pipe));
1246 cur_state = !!(val & FDI_RX_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256 {
1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261 return;
1262
1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264 if (HAS_DDI(dev_priv->dev))
1265 return;
1266
1267 val = I915_READ(FDI_TX_CTL(pipe));
1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
1273 {
1274 u32 val;
1275 bool cur_state;
1276
1277 val = I915_READ(FDI_RX_CTL(pipe));
1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279 I915_STATE_WARN(cur_state != state,
1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
1286 {
1287 struct drm_device *dev = dev_priv->dev;
1288 int pp_reg;
1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
1291 bool locked = true;
1292
1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
1299 pp_reg = PCH_PP_CONTROL;
1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
1310 } else {
1311 pp_reg = PP_CONTROL;
1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319 locked = false;
1320
1321 I915_STATE_WARN(panel_pipe == pipe && locked,
1322 "panel assertion failure, pipe %c regs locked\n",
1323 pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
1332 if (IS_845G(dev) || IS_I865G(dev))
1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334 else
1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337 I915_STATE_WARN(cur_state != state,
1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
1346 {
1347 bool cur_state;
1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
1350
1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354 state = true;
1355
1356 if (!intel_display_power_is_enabled(dev_priv,
1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358 cur_state = false;
1359 } else {
1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
1364 I915_STATE_WARN(cur_state != state,
1365 "pipe %c assertion failure (expected %s, current %s)\n",
1366 pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
1371 {
1372 u32 val;
1373 bool cur_state;
1374
1375 val = I915_READ(DSPCNTR(plane));
1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377 I915_STATE_WARN(cur_state != state,
1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387 {
1388 struct drm_device *dev = dev_priv->dev;
1389 int i;
1390
1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
1393 u32 val = I915_READ(DSPCNTR(pipe));
1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
1397 return;
1398 }
1399
1400 /* Need to check both planes against the pipe */
1401 for_each_pipe(dev_priv, i) {
1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404 DISPPLANE_SEL_PIPE_SHIFT;
1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
1408 }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413 {
1414 struct drm_device *dev = dev_priv->dev;
1415 int sprite;
1416
1417 if (INTEL_INFO(dev)->gen >= 9) {
1418 for_each_sprite(dev_priv, pipe, sprite) {
1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
1425 for_each_sprite(dev_priv, pipe, sprite) {
1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
1427 I915_STATE_WARN(val & SP_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 sprite_name(pipe, sprite), pipe_name(pipe));
1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
1432 u32 val = I915_READ(SPRCTL(pipe));
1433 I915_STATE_WARN(val & SPRITE_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
1437 u32 val = I915_READ(DVSCNTR(pipe));
1438 I915_STATE_WARN(val & DVS_ENABLE,
1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440 plane_name(pipe), pipe_name(pipe));
1441 }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452 u32 val;
1453 bool enabled;
1454
1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 u32 val;
1467 bool enabled;
1468
1469 val = I915_READ(PCH_TRANSCONF(pipe));
1470 enabled = !!(val & TRANS_ENABLE);
1471 I915_STATE_WARN(enabled,
1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486 return false;
1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489 return false;
1490 } else {
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492 return false;
1493 }
1494 return true;
1495 }
1496
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499 {
1500 if ((val & SDVO_ENABLE) == 0)
1501 return false;
1502
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1505 return false;
1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508 return false;
1509 } else {
1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1511 return false;
1512 }
1513 return true;
1514 }
1515
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518 {
1519 if ((val & LVDS_PORT_EN) == 0)
1520 return false;
1521
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527 return false;
1528 }
1529 return true;
1530 }
1531
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1534 {
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1536 return false;
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539 return false;
1540 } else {
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542 return false;
1543 }
1544 return true;
1545 }
1546
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548 enum pipe pipe, int reg, u32 port_sel)
1549 {
1550 u32 val = I915_READ(reg);
1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553 reg, pipe_name(pipe));
1554
1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556 && (val & DP_PIPEB_SELECT),
1557 "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1562 {
1563 u32 val = I915_READ(reg);
1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566 reg, pipe_name(pipe));
1567
1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569 && (val & SDVO_PIPE_B_SELECT),
1570 "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575 {
1576 u32 val;
1577
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582 val = I915_READ(PCH_ADPA);
1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 val = I915_READ(PCH_LVDS);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1599 {
1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605 assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1638 {
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649 mutex_lock(&dev_priv->sb_lock);
1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656 mutex_unlock(&dev_priv->sb_lock);
1657
1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672 POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
1681 count += crtc->base.state->active &&
1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684 return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694 assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
1715
1716 /*
1717 * Apparently we need to have VGA mode enabled prior to changing
1718 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719 * dividers, even though the register value does change.
1720 */
1721 I915_WRITE(reg, 0);
1722
1723 I915_WRITE(reg, dpll);
1724
1725 /* Wait for the clocks to stabilize. */
1726 POSTING_READ(reg);
1727 udelay(150);
1728
1729 if (INTEL_INFO(dev)->gen >= 4) {
1730 I915_WRITE(DPLL_MD(crtc->pipe),
1731 crtc->config->dpll_hw_state.dpll_md);
1732 } else {
1733 /* The pixel multiplier can only be updated once the
1734 * DPLL is enabled and the clocks are stable.
1735 *
1736 * So write it again.
1737 */
1738 I915_WRITE(reg, dpll);
1739 }
1740
1741 /* We do this three times for luck */
1742 I915_WRITE(reg, dpll);
1743 POSTING_READ(reg);
1744 udelay(150); /* wait for warmup */
1745 I915_WRITE(reg, dpll);
1746 POSTING_READ(reg);
1747 udelay(150); /* wait for warmup */
1748 I915_WRITE(reg, dpll);
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754 * i9xx_disable_pll - disable a PLL
1755 * @dev_priv: i915 private structure
1756 * @pipe: pipe PLL to disable
1757 *
1758 * Disable the PLL for @pipe, making sure the pipe is off first.
1759 *
1760 * Note! This is for pre-ILK only.
1761 */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764 struct drm_device *dev = crtc->base.dev;
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 enum pipe pipe = crtc->pipe;
1767
1768 /* Disable DVO 2x clock on both PLLs if necessary */
1769 if (IS_I830(dev) &&
1770 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771 !intel_num_dvo_pipes(dev)) {
1772 I915_WRITE(DPLL(PIPE_B),
1773 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774 I915_WRITE(DPLL(PIPE_A),
1775 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776 }
1777
1778 /* Don't disable pipe or pipe PLLs if needed */
1779 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781 return;
1782
1783 /* Make sure the pipe isn't still relying on us */
1784 assert_pipe_disabled(dev_priv, pipe);
1785
1786 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787 POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792 u32 val;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
1797 /*
1798 * Leave integrated clock source and reference clock enabled for pipe B.
1799 * The latter is needed for VGA hotplug / manual detection.
1800 */
1801 val = DPLL_VGA_MODE_DIS;
1802 if (pipe == PIPE_B)
1803 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804 I915_WRITE(DPLL(pipe), val);
1805 POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812 u32 val;
1813
1814 /* Make sure the pipe isn't still relying on us */
1815 assert_pipe_disabled(dev_priv, pipe);
1816
1817 /* Set PLL en = 0 */
1818 val = DPLL_SSC_REF_CLK_CHV |
1819 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
1824
1825 mutex_lock(&dev_priv->sb_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832 mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836 struct intel_digital_port *dport,
1837 unsigned int expected_mask)
1838 {
1839 u32 port_mask;
1840 int dpll_reg;
1841
1842 switch (dport->port) {
1843 case PORT_B:
1844 port_mask = DPLL_PORTB_READY_MASK;
1845 dpll_reg = DPLL(0);
1846 break;
1847 case PORT_C:
1848 port_mask = DPLL_PORTC_READY_MASK;
1849 dpll_reg = DPLL(0);
1850 expected_mask <<= 4;
1851 break;
1852 case PORT_D:
1853 port_mask = DPLL_PORTD_READY_MASK;
1854 dpll_reg = DPIO_PHY_STATUS;
1855 break;
1856 default:
1857 BUG();
1858 }
1859
1860 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867 struct drm_device *dev = crtc->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871 if (WARN_ON(pll == NULL))
1872 return;
1873
1874 WARN_ON(!pll->config.crtc_mask);
1875 if (pll->active == 0) {
1876 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877 WARN_ON(pll->on);
1878 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880 pll->mode_set(dev_priv, pll);
1881 }
1882 }
1883
1884 /**
1885 * intel_enable_shared_dpll - enable PCH PLL
1886 * @dev_priv: i915 private structure
1887 * @pipe: pipe PLL to enable
1888 *
1889 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890 * drives the transcoder clock.
1891 */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894 struct drm_device *dev = crtc->base.dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1896 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898 if (WARN_ON(pll == NULL))
1899 return;
1900
1901 if (WARN_ON(pll->config.crtc_mask == 0))
1902 return;
1903
1904 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905 pll->name, pll->active, pll->on,
1906 crtc->base.base.id);
1907
1908 if (pll->active++) {
1909 WARN_ON(!pll->on);
1910 assert_shared_dpll_enabled(dev_priv, pll);
1911 return;
1912 }
1913 WARN_ON(pll->on);
1914
1915 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918 pll->enable(dev_priv, pll);
1919 pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924 struct drm_device *dev = crtc->base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928 /* PCH only available on ILK+ */
1929 if (INTEL_INFO(dev)->gen < 5)
1930 return;
1931
1932 if (pll == NULL)
1933 return;
1934
1935 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936 return;
1937
1938 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939 pll->name, pll->active, pll->on,
1940 crtc->base.base.id);
1941
1942 if (WARN_ON(pll->active == 0)) {
1943 assert_shared_dpll_disabled(dev_priv, pll);
1944 return;
1945 }
1946
1947 assert_shared_dpll_enabled(dev_priv, pll);
1948 WARN_ON(!pll->on);
1949 if (--pll->active)
1950 return;
1951
1952 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953 pll->disable(dev_priv, pll);
1954 pll->on = false;
1955
1956 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960 enum pipe pipe)
1961 {
1962 struct drm_device *dev = dev_priv->dev;
1963 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965 uint32_t reg, val, pipeconf_val;
1966
1967 /* PCH only available on ILK+ */
1968 BUG_ON(!HAS_PCH_SPLIT(dev));
1969
1970 /* Make sure PCH DPLL is enabled */
1971 assert_shared_dpll_enabled(dev_priv,
1972 intel_crtc_to_shared_dpll(intel_crtc));
1973
1974 /* FDI must be feeding us bits for PCH ports */
1975 assert_fdi_tx_enabled(dev_priv, pipe);
1976 assert_fdi_rx_enabled(dev_priv, pipe);
1977
1978 if (HAS_PCH_CPT(dev)) {
1979 /* Workaround: Set the timing override bit before enabling the
1980 * pch transcoder. */
1981 reg = TRANS_CHICKEN2(pipe);
1982 val = I915_READ(reg);
1983 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984 I915_WRITE(reg, val);
1985 }
1986
1987 reg = PCH_TRANSCONF(pipe);
1988 val = I915_READ(reg);
1989 pipeconf_val = I915_READ(PIPECONF(pipe));
1990
1991 if (HAS_PCH_IBX(dev_priv->dev)) {
1992 /*
1993 * Make the BPC in transcoder be consistent with
1994 * that in pipeconf reg. For HDMI we must use 8bpc
1995 * here for both 8bpc and 12bpc.
1996 */
1997 val &= ~PIPECONF_BPC_MASK;
1998 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1999 val |= PIPECONF_8BPC;
2000 else
2001 val |= pipeconf_val & PIPECONF_BPC_MASK;
2002 }
2003
2004 val &= ~TRANS_INTERLACE_MASK;
2005 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2006 if (HAS_PCH_IBX(dev_priv->dev) &&
2007 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2008 val |= TRANS_LEGACY_INTERLACED_ILK;
2009 else
2010 val |= TRANS_INTERLACED;
2011 else
2012 val |= TRANS_PROGRESSIVE;
2013
2014 I915_WRITE(reg, val | TRANS_ENABLE);
2015 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2016 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2017 }
2018
2019 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2020 enum transcoder cpu_transcoder)
2021 {
2022 u32 val, pipeconf_val;
2023
2024 /* PCH only available on ILK+ */
2025 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2026
2027 /* FDI must be feeding us bits for PCH ports */
2028 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2029 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2030
2031 /* Workaround: set timing override bit. */
2032 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2033 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2034 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2035
2036 val = TRANS_ENABLE;
2037 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2038
2039 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2040 PIPECONF_INTERLACED_ILK)
2041 val |= TRANS_INTERLACED;
2042 else
2043 val |= TRANS_PROGRESSIVE;
2044
2045 I915_WRITE(LPT_TRANSCONF, val);
2046 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2047 DRM_ERROR("Failed to enable PCH transcoder\n");
2048 }
2049
2050 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2051 enum pipe pipe)
2052 {
2053 struct drm_device *dev = dev_priv->dev;
2054 uint32_t reg, val;
2055
2056 /* FDI relies on the transcoder */
2057 assert_fdi_tx_disabled(dev_priv, pipe);
2058 assert_fdi_rx_disabled(dev_priv, pipe);
2059
2060 /* Ports must be off as well */
2061 assert_pch_ports_disabled(dev_priv, pipe);
2062
2063 reg = PCH_TRANSCONF(pipe);
2064 val = I915_READ(reg);
2065 val &= ~TRANS_ENABLE;
2066 I915_WRITE(reg, val);
2067 /* wait for PCH transcoder off, transcoder state */
2068 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2069 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2070
2071 if (!HAS_PCH_IBX(dev)) {
2072 /* Workaround: Clear the timing override chicken bit again. */
2073 reg = TRANS_CHICKEN2(pipe);
2074 val = I915_READ(reg);
2075 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2076 I915_WRITE(reg, val);
2077 }
2078 }
2079
2080 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2081 {
2082 u32 val;
2083
2084 val = I915_READ(LPT_TRANSCONF);
2085 val &= ~TRANS_ENABLE;
2086 I915_WRITE(LPT_TRANSCONF, val);
2087 /* wait for PCH transcoder off, transcoder state */
2088 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2089 DRM_ERROR("Failed to disable PCH transcoder\n");
2090
2091 /* Workaround: clear timing override bit. */
2092 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2093 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2095 }
2096
2097 /**
2098 * intel_enable_pipe - enable a pipe, asserting requirements
2099 * @crtc: crtc responsible for the pipe
2100 *
2101 * Enable @crtc's pipe, making sure that various hardware specific requirements
2102 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2103 */
2104 static void intel_enable_pipe(struct intel_crtc *crtc)
2105 {
2106 struct drm_device *dev = crtc->base.dev;
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 enum pipe pipe = crtc->pipe;
2109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2110 pipe);
2111 enum pipe pch_transcoder;
2112 int reg;
2113 u32 val;
2114
2115 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2116
2117 assert_planes_disabled(dev_priv, pipe);
2118 assert_cursor_disabled(dev_priv, pipe);
2119 assert_sprites_disabled(dev_priv, pipe);
2120
2121 if (HAS_PCH_LPT(dev_priv->dev))
2122 pch_transcoder = TRANSCODER_A;
2123 else
2124 pch_transcoder = pipe;
2125
2126 /*
2127 * A pipe without a PLL won't actually be able to drive bits from
2128 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2129 * need the check.
2130 */
2131 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2132 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2133 assert_dsi_pll_enabled(dev_priv);
2134 else
2135 assert_pll_enabled(dev_priv, pipe);
2136 else {
2137 if (crtc->config->has_pch_encoder) {
2138 /* if driving the PCH, we need FDI enabled */
2139 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2140 assert_fdi_tx_pll_enabled(dev_priv,
2141 (enum pipe) cpu_transcoder);
2142 }
2143 /* FIXME: assert CPU port conditions for SNB+ */
2144 }
2145
2146 reg = PIPECONF(cpu_transcoder);
2147 val = I915_READ(reg);
2148 if (val & PIPECONF_ENABLE) {
2149 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2150 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2151 return;
2152 }
2153
2154 I915_WRITE(reg, val | PIPECONF_ENABLE);
2155 POSTING_READ(reg);
2156 }
2157
2158 /**
2159 * intel_disable_pipe - disable a pipe, asserting requirements
2160 * @crtc: crtc whose pipes is to be disabled
2161 *
2162 * Disable the pipe of @crtc, making sure that various hardware
2163 * specific requirements are met, if applicable, e.g. plane
2164 * disabled, panel fitter off, etc.
2165 *
2166 * Will wait until the pipe has shut down before returning.
2167 */
2168 static void intel_disable_pipe(struct intel_crtc *crtc)
2169 {
2170 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2171 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2172 enum pipe pipe = crtc->pipe;
2173 int reg;
2174 u32 val;
2175
2176 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2177
2178 /*
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2181 */
2182 assert_planes_disabled(dev_priv, pipe);
2183 assert_cursor_disabled(dev_priv, pipe);
2184 assert_sprites_disabled(dev_priv, pipe);
2185
2186 reg = PIPECONF(cpu_transcoder);
2187 val = I915_READ(reg);
2188 if ((val & PIPECONF_ENABLE) == 0)
2189 return;
2190
2191 /*
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2194 */
2195 if (crtc->config->double_wide)
2196 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198 /* Don't disable pipe or pipe PLLs if needed */
2199 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2201 val &= ~PIPECONF_ENABLE;
2202
2203 I915_WRITE(reg, val);
2204 if ((val & PIPECONF_ENABLE) == 0)
2205 intel_wait_for_pipe_off(crtc);
2206 }
2207
2208 static bool need_vtd_wa(struct drm_device *dev)
2209 {
2210 #ifdef CONFIG_INTEL_IOMMU
2211 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2212 return true;
2213 #endif
2214 return false;
2215 }
2216
2217 unsigned int
2218 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2219 uint64_t fb_format_modifier, unsigned int plane)
2220 {
2221 unsigned int tile_height;
2222 uint32_t pixel_bytes;
2223
2224 switch (fb_format_modifier) {
2225 case DRM_FORMAT_MOD_NONE:
2226 tile_height = 1;
2227 break;
2228 case I915_FORMAT_MOD_X_TILED:
2229 tile_height = IS_GEN2(dev) ? 16 : 8;
2230 break;
2231 case I915_FORMAT_MOD_Y_TILED:
2232 tile_height = 32;
2233 break;
2234 case I915_FORMAT_MOD_Yf_TILED:
2235 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2236 switch (pixel_bytes) {
2237 default:
2238 case 1:
2239 tile_height = 64;
2240 break;
2241 case 2:
2242 case 4:
2243 tile_height = 32;
2244 break;
2245 case 8:
2246 tile_height = 16;
2247 break;
2248 case 16:
2249 WARN_ONCE(1,
2250 "128-bit pixels are not supported for display!");
2251 tile_height = 16;
2252 break;
2253 }
2254 break;
2255 default:
2256 MISSING_CASE(fb_format_modifier);
2257 tile_height = 1;
2258 break;
2259 }
2260
2261 return tile_height;
2262 }
2263
2264 unsigned int
2265 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2266 uint32_t pixel_format, uint64_t fb_format_modifier)
2267 {
2268 return ALIGN(height, intel_tile_height(dev, pixel_format,
2269 fb_format_modifier, 0));
2270 }
2271
2272 static int
2273 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2274 const struct drm_plane_state *plane_state)
2275 {
2276 struct intel_rotation_info *info = &view->rotation_info;
2277 unsigned int tile_height, tile_pitch;
2278
2279 *view = i915_ggtt_view_normal;
2280
2281 if (!plane_state)
2282 return 0;
2283
2284 if (!intel_rotation_90_or_270(plane_state->rotation))
2285 return 0;
2286
2287 *view = i915_ggtt_view_rotated;
2288
2289 info->height = fb->height;
2290 info->pixel_format = fb->pixel_format;
2291 info->pitch = fb->pitches[0];
2292 info->uv_offset = fb->offsets[1];
2293 info->fb_modifier = fb->modifier[0];
2294
2295 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2296 fb->modifier[0], 0);
2297 tile_pitch = PAGE_SIZE / tile_height;
2298 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2300 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2301
2302 if (info->pixel_format == DRM_FORMAT_NV12) {
2303 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304 fb->modifier[0], 1);
2305 tile_pitch = PAGE_SIZE / tile_height;
2306 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2307 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2308 tile_height);
2309 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2310 PAGE_SIZE;
2311 }
2312
2313 return 0;
2314 }
2315
2316 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2317 {
2318 if (INTEL_INFO(dev_priv)->gen >= 9)
2319 return 256 * 1024;
2320 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2321 IS_VALLEYVIEW(dev_priv))
2322 return 128 * 1024;
2323 else if (INTEL_INFO(dev_priv)->gen >= 4)
2324 return 4 * 1024;
2325 else
2326 return 0;
2327 }
2328
2329 int
2330 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2331 struct drm_framebuffer *fb,
2332 const struct drm_plane_state *plane_state,
2333 struct intel_engine_cs *pipelined,
2334 struct drm_i915_gem_request **pipelined_request)
2335 {
2336 struct drm_device *dev = fb->dev;
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2339 struct i915_ggtt_view view;
2340 u32 alignment;
2341 int ret;
2342
2343 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2344
2345 switch (fb->modifier[0]) {
2346 case DRM_FORMAT_MOD_NONE:
2347 alignment = intel_linear_alignment(dev_priv);
2348 break;
2349 case I915_FORMAT_MOD_X_TILED:
2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
2356 break;
2357 case I915_FORMAT_MOD_Y_TILED:
2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
2364 default:
2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
2367 }
2368
2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
2390 dev_priv->mm.interruptible = false;
2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2392 pipelined_request, &view);
2393 if (ret)
2394 goto err_interruptible;
2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
2401 if (view.type == I915_GGTT_VIEW_NORMAL) {
2402 ret = i915_gem_object_get_fence(obj);
2403 if (ret == -EDEADLK) {
2404 /*
2405 * -EDEADLK means there are no free fences
2406 * no pending flips.
2407 *
2408 * This is propagated to atomic, but it uses
2409 * -EDEADLK to force a locking recovery, so
2410 * change the returned error to -EBUSY.
2411 */
2412 ret = -EBUSY;
2413 goto err_unpin;
2414 } else if (ret)
2415 goto err_unpin;
2416
2417 i915_gem_object_pin_fence(obj);
2418 }
2419
2420 dev_priv->mm.interruptible = true;
2421 intel_runtime_pm_put(dev_priv);
2422 return 0;
2423
2424 err_unpin:
2425 i915_gem_object_unpin_from_display_plane(obj, &view);
2426 err_interruptible:
2427 dev_priv->mm.interruptible = true;
2428 intel_runtime_pm_put(dev_priv);
2429 return ret;
2430 }
2431
2432 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2433 const struct drm_plane_state *plane_state)
2434 {
2435 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2436 struct i915_ggtt_view view;
2437 int ret;
2438
2439 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2440
2441 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2442 WARN_ONCE(ret, "Couldn't get view from plane state!");
2443
2444 if (view.type == I915_GGTT_VIEW_NORMAL)
2445 i915_gem_object_unpin_fence(obj);
2446
2447 i915_gem_object_unpin_from_display_plane(obj, &view);
2448 }
2449
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451 * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2453 int *x, int *y,
2454 unsigned int tiling_mode,
2455 unsigned int cpp,
2456 unsigned int pitch)
2457 {
2458 if (tiling_mode != I915_TILING_NONE) {
2459 unsigned int tile_rows, tiles;
2460
2461 tile_rows = *y / 8;
2462 *y %= 8;
2463
2464 tiles = *x / (512/cpp);
2465 *x %= 512/cpp;
2466
2467 return tile_rows * pitch * 8 + tiles * 4096;
2468 } else {
2469 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2470 unsigned int offset;
2471
2472 offset = *y * pitch + *x * cpp;
2473 *y = (offset & alignment) / pitch;
2474 *x = ((offset & alignment) - *y * pitch) / cpp;
2475 return offset & ~alignment;
2476 }
2477 }
2478
2479 static int i9xx_format_to_fourcc(int format)
2480 {
2481 switch (format) {
2482 case DISPPLANE_8BPP:
2483 return DRM_FORMAT_C8;
2484 case DISPPLANE_BGRX555:
2485 return DRM_FORMAT_XRGB1555;
2486 case DISPPLANE_BGRX565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case DISPPLANE_BGRX888:
2490 return DRM_FORMAT_XRGB8888;
2491 case DISPPLANE_RGBX888:
2492 return DRM_FORMAT_XBGR8888;
2493 case DISPPLANE_BGRX101010:
2494 return DRM_FORMAT_XRGB2101010;
2495 case DISPPLANE_RGBX101010:
2496 return DRM_FORMAT_XBGR2101010;
2497 }
2498 }
2499
2500 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2501 {
2502 switch (format) {
2503 case PLANE_CTL_FORMAT_RGB_565:
2504 return DRM_FORMAT_RGB565;
2505 default:
2506 case PLANE_CTL_FORMAT_XRGB_8888:
2507 if (rgb_order) {
2508 if (alpha)
2509 return DRM_FORMAT_ABGR8888;
2510 else
2511 return DRM_FORMAT_XBGR8888;
2512 } else {
2513 if (alpha)
2514 return DRM_FORMAT_ARGB8888;
2515 else
2516 return DRM_FORMAT_XRGB8888;
2517 }
2518 case PLANE_CTL_FORMAT_XRGB_2101010:
2519 if (rgb_order)
2520 return DRM_FORMAT_XBGR2101010;
2521 else
2522 return DRM_FORMAT_XRGB2101010;
2523 }
2524 }
2525
2526 static bool
2527 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528 struct intel_initial_plane_config *plane_config)
2529 {
2530 struct drm_device *dev = crtc->base.dev;
2531 struct drm_i915_private *dev_priv = to_i915(dev);
2532 struct drm_i915_gem_object *obj = NULL;
2533 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2534 struct drm_framebuffer *fb = &plane_config->fb->base;
2535 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2536 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2537 PAGE_SIZE);
2538
2539 size_aligned -= base_aligned;
2540
2541 if (plane_config->size == 0)
2542 return false;
2543
2544 /* If the FB is too big, just don't use it since fbdev is not very
2545 * important and we should probably use that space with FBC or other
2546 * features. */
2547 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2548 return false;
2549
2550 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2551 base_aligned,
2552 base_aligned,
2553 size_aligned);
2554 if (!obj)
2555 return false;
2556
2557 obj->tiling_mode = plane_config->tiling;
2558 if (obj->tiling_mode == I915_TILING_X)
2559 obj->stride = fb->pitches[0];
2560
2561 mode_cmd.pixel_format = fb->pixel_format;
2562 mode_cmd.width = fb->width;
2563 mode_cmd.height = fb->height;
2564 mode_cmd.pitches[0] = fb->pitches[0];
2565 mode_cmd.modifier[0] = fb->modifier[0];
2566 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2567
2568 mutex_lock(&dev->struct_mutex);
2569 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2570 &mode_cmd, obj)) {
2571 DRM_DEBUG_KMS("intel fb init failed\n");
2572 goto out_unref_obj;
2573 }
2574 mutex_unlock(&dev->struct_mutex);
2575
2576 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2577 return true;
2578
2579 out_unref_obj:
2580 drm_gem_object_unreference(&obj->base);
2581 mutex_unlock(&dev->struct_mutex);
2582 return false;
2583 }
2584
2585 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2586 static void
2587 update_state_fb(struct drm_plane *plane)
2588 {
2589 if (plane->fb == plane->state->fb)
2590 return;
2591
2592 if (plane->state->fb)
2593 drm_framebuffer_unreference(plane->state->fb);
2594 plane->state->fb = plane->fb;
2595 if (plane->state->fb)
2596 drm_framebuffer_reference(plane->state->fb);
2597 }
2598
2599 static void
2600 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2601 struct intel_initial_plane_config *plane_config)
2602 {
2603 struct drm_device *dev = intel_crtc->base.dev;
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 struct drm_crtc *c;
2606 struct intel_crtc *i;
2607 struct drm_i915_gem_object *obj;
2608 struct drm_plane *primary = intel_crtc->base.primary;
2609 struct drm_plane_state *plane_state = primary->state;
2610 struct drm_framebuffer *fb;
2611
2612 if (!plane_config->fb)
2613 return;
2614
2615 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2616 fb = &plane_config->fb->base;
2617 goto valid_fb;
2618 }
2619
2620 kfree(plane_config->fb);
2621
2622 /*
2623 * Failed to alloc the obj, check to see if we should share
2624 * an fb with another CRTC instead
2625 */
2626 for_each_crtc(dev, c) {
2627 i = to_intel_crtc(c);
2628
2629 if (c == &intel_crtc->base)
2630 continue;
2631
2632 if (!i->active)
2633 continue;
2634
2635 fb = c->primary->fb;
2636 if (!fb)
2637 continue;
2638
2639 obj = intel_fb_obj(fb);
2640 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2641 drm_framebuffer_reference(fb);
2642 goto valid_fb;
2643 }
2644 }
2645
2646 return;
2647
2648 valid_fb:
2649 plane_state->src_x = 0;
2650 plane_state->src_y = 0;
2651 plane_state->src_w = fb->width << 16;
2652 plane_state->src_h = fb->height << 16;
2653
2654 plane_state->crtc_x = 0;
2655 plane_state->crtc_y = 0;
2656 plane_state->crtc_w = fb->width;
2657 plane_state->crtc_h = fb->height;
2658
2659 obj = intel_fb_obj(fb);
2660 if (obj->tiling_mode != I915_TILING_NONE)
2661 dev_priv->preserve_bios_swizzle = true;
2662
2663 drm_framebuffer_reference(fb);
2664 primary->fb = primary->state->fb = fb;
2665 primary->crtc = primary->state->crtc = &intel_crtc->base;
2666 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2667 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2668 }
2669
2670 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2671 struct drm_framebuffer *fb,
2672 int x, int y)
2673 {
2674 struct drm_device *dev = crtc->dev;
2675 struct drm_i915_private *dev_priv = dev->dev_private;
2676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2677 struct drm_plane *primary = crtc->primary;
2678 bool visible = to_intel_plane_state(primary->state)->visible;
2679 struct drm_i915_gem_object *obj;
2680 int plane = intel_crtc->plane;
2681 unsigned long linear_offset;
2682 u32 dspcntr;
2683 u32 reg = DSPCNTR(plane);
2684 int pixel_size;
2685
2686 if (!visible || !fb) {
2687 I915_WRITE(reg, 0);
2688 if (INTEL_INFO(dev)->gen >= 4)
2689 I915_WRITE(DSPSURF(plane), 0);
2690 else
2691 I915_WRITE(DSPADDR(plane), 0);
2692 POSTING_READ(reg);
2693 return;
2694 }
2695
2696 obj = intel_fb_obj(fb);
2697 if (WARN_ON(obj == NULL))
2698 return;
2699
2700 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2701
2702 dspcntr = DISPPLANE_GAMMA_ENABLE;
2703
2704 dspcntr |= DISPLAY_PLANE_ENABLE;
2705
2706 if (INTEL_INFO(dev)->gen < 4) {
2707 if (intel_crtc->pipe == PIPE_B)
2708 dspcntr |= DISPPLANE_SEL_PIPE_B;
2709
2710 /* pipesrc and dspsize control the size that is scaled from,
2711 * which should always be the user's requested size.
2712 */
2713 I915_WRITE(DSPSIZE(plane),
2714 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2715 (intel_crtc->config->pipe_src_w - 1));
2716 I915_WRITE(DSPPOS(plane), 0);
2717 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2718 I915_WRITE(PRIMSIZE(plane),
2719 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2720 (intel_crtc->config->pipe_src_w - 1));
2721 I915_WRITE(PRIMPOS(plane), 0);
2722 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2723 }
2724
2725 switch (fb->pixel_format) {
2726 case DRM_FORMAT_C8:
2727 dspcntr |= DISPPLANE_8BPP;
2728 break;
2729 case DRM_FORMAT_XRGB1555:
2730 dspcntr |= DISPPLANE_BGRX555;
2731 break;
2732 case DRM_FORMAT_RGB565:
2733 dspcntr |= DISPPLANE_BGRX565;
2734 break;
2735 case DRM_FORMAT_XRGB8888:
2736 dspcntr |= DISPPLANE_BGRX888;
2737 break;
2738 case DRM_FORMAT_XBGR8888:
2739 dspcntr |= DISPPLANE_RGBX888;
2740 break;
2741 case DRM_FORMAT_XRGB2101010:
2742 dspcntr |= DISPPLANE_BGRX101010;
2743 break;
2744 case DRM_FORMAT_XBGR2101010:
2745 dspcntr |= DISPPLANE_RGBX101010;
2746 break;
2747 default:
2748 BUG();
2749 }
2750
2751 if (INTEL_INFO(dev)->gen >= 4 &&
2752 obj->tiling_mode != I915_TILING_NONE)
2753 dspcntr |= DISPPLANE_TILED;
2754
2755 if (IS_G4X(dev))
2756 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2757
2758 linear_offset = y * fb->pitches[0] + x * pixel_size;
2759
2760 if (INTEL_INFO(dev)->gen >= 4) {
2761 intel_crtc->dspaddr_offset =
2762 intel_gen4_compute_page_offset(dev_priv,
2763 &x, &y, obj->tiling_mode,
2764 pixel_size,
2765 fb->pitches[0]);
2766 linear_offset -= intel_crtc->dspaddr_offset;
2767 } else {
2768 intel_crtc->dspaddr_offset = linear_offset;
2769 }
2770
2771 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2772 dspcntr |= DISPPLANE_ROTATE_180;
2773
2774 x += (intel_crtc->config->pipe_src_w - 1);
2775 y += (intel_crtc->config->pipe_src_h - 1);
2776
2777 /* Finding the last pixel of the last line of the display
2778 data and adding to linear_offset*/
2779 linear_offset +=
2780 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2781 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2782 }
2783
2784 intel_crtc->adjusted_x = x;
2785 intel_crtc->adjusted_y = y;
2786
2787 I915_WRITE(reg, dspcntr);
2788
2789 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2790 if (INTEL_INFO(dev)->gen >= 4) {
2791 I915_WRITE(DSPSURF(plane),
2792 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2793 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2794 I915_WRITE(DSPLINOFF(plane), linear_offset);
2795 } else
2796 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2797 POSTING_READ(reg);
2798 }
2799
2800 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2801 struct drm_framebuffer *fb,
2802 int x, int y)
2803 {
2804 struct drm_device *dev = crtc->dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807 struct drm_plane *primary = crtc->primary;
2808 bool visible = to_intel_plane_state(primary->state)->visible;
2809 struct drm_i915_gem_object *obj;
2810 int plane = intel_crtc->plane;
2811 unsigned long linear_offset;
2812 u32 dspcntr;
2813 u32 reg = DSPCNTR(plane);
2814 int pixel_size;
2815
2816 if (!visible || !fb) {
2817 I915_WRITE(reg, 0);
2818 I915_WRITE(DSPSURF(plane), 0);
2819 POSTING_READ(reg);
2820 return;
2821 }
2822
2823 obj = intel_fb_obj(fb);
2824 if (WARN_ON(obj == NULL))
2825 return;
2826
2827 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2828
2829 dspcntr = DISPPLANE_GAMMA_ENABLE;
2830
2831 dspcntr |= DISPLAY_PLANE_ENABLE;
2832
2833 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2834 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2835
2836 switch (fb->pixel_format) {
2837 case DRM_FORMAT_C8:
2838 dspcntr |= DISPPLANE_8BPP;
2839 break;
2840 case DRM_FORMAT_RGB565:
2841 dspcntr |= DISPPLANE_BGRX565;
2842 break;
2843 case DRM_FORMAT_XRGB8888:
2844 dspcntr |= DISPPLANE_BGRX888;
2845 break;
2846 case DRM_FORMAT_XBGR8888:
2847 dspcntr |= DISPPLANE_RGBX888;
2848 break;
2849 case DRM_FORMAT_XRGB2101010:
2850 dspcntr |= DISPPLANE_BGRX101010;
2851 break;
2852 case DRM_FORMAT_XBGR2101010:
2853 dspcntr |= DISPPLANE_RGBX101010;
2854 break;
2855 default:
2856 BUG();
2857 }
2858
2859 if (obj->tiling_mode != I915_TILING_NONE)
2860 dspcntr |= DISPPLANE_TILED;
2861
2862 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2863 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2864
2865 linear_offset = y * fb->pitches[0] + x * pixel_size;
2866 intel_crtc->dspaddr_offset =
2867 intel_gen4_compute_page_offset(dev_priv,
2868 &x, &y, obj->tiling_mode,
2869 pixel_size,
2870 fb->pitches[0]);
2871 linear_offset -= intel_crtc->dspaddr_offset;
2872 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2873 dspcntr |= DISPPLANE_ROTATE_180;
2874
2875 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2876 x += (intel_crtc->config->pipe_src_w - 1);
2877 y += (intel_crtc->config->pipe_src_h - 1);
2878
2879 /* Finding the last pixel of the last line of the display
2880 data and adding to linear_offset*/
2881 linear_offset +=
2882 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2883 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2884 }
2885 }
2886
2887 intel_crtc->adjusted_x = x;
2888 intel_crtc->adjusted_y = y;
2889
2890 I915_WRITE(reg, dspcntr);
2891
2892 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2893 I915_WRITE(DSPSURF(plane),
2894 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2895 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2896 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2897 } else {
2898 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2899 I915_WRITE(DSPLINOFF(plane), linear_offset);
2900 }
2901 POSTING_READ(reg);
2902 }
2903
2904 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2905 uint32_t pixel_format)
2906 {
2907 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2908
2909 /*
2910 * The stride is either expressed as a multiple of 64 bytes
2911 * chunks for linear buffers or in number of tiles for tiled
2912 * buffers.
2913 */
2914 switch (fb_modifier) {
2915 case DRM_FORMAT_MOD_NONE:
2916 return 64;
2917 case I915_FORMAT_MOD_X_TILED:
2918 if (INTEL_INFO(dev)->gen == 2)
2919 return 128;
2920 return 512;
2921 case I915_FORMAT_MOD_Y_TILED:
2922 /* No need to check for old gens and Y tiling since this is
2923 * about the display engine and those will be blocked before
2924 * we get here.
2925 */
2926 return 128;
2927 case I915_FORMAT_MOD_Yf_TILED:
2928 if (bits_per_pixel == 8)
2929 return 64;
2930 else
2931 return 128;
2932 default:
2933 MISSING_CASE(fb_modifier);
2934 return 64;
2935 }
2936 }
2937
2938 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2939 struct drm_i915_gem_object *obj,
2940 unsigned int plane)
2941 {
2942 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2943 struct i915_vma *vma;
2944 unsigned char *offset;
2945
2946 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2947 view = &i915_ggtt_view_rotated;
2948
2949 vma = i915_gem_obj_to_ggtt_view(obj, view);
2950 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2951 view->type))
2952 return -1;
2953
2954 offset = (unsigned char *)vma->node.start;
2955
2956 if (plane == 1) {
2957 offset += vma->ggtt_view.rotation_info.uv_start_page *
2958 PAGE_SIZE;
2959 }
2960
2961 return (unsigned long)offset;
2962 }
2963
2964 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2965 {
2966 struct drm_device *dev = intel_crtc->base.dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968
2969 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2970 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2971 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2972 }
2973
2974 /*
2975 * This function detaches (aka. unbinds) unused scalers in hardware
2976 */
2977 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2978 {
2979 struct intel_crtc_scaler_state *scaler_state;
2980 int i;
2981
2982 scaler_state = &intel_crtc->config->scaler_state;
2983
2984 /* loop through and disable scalers that aren't in use */
2985 for (i = 0; i < intel_crtc->num_scalers; i++) {
2986 if (!scaler_state->scalers[i].in_use)
2987 skl_detach_scaler(intel_crtc, i);
2988 }
2989 }
2990
2991 u32 skl_plane_ctl_format(uint32_t pixel_format)
2992 {
2993 switch (pixel_format) {
2994 case DRM_FORMAT_C8:
2995 return PLANE_CTL_FORMAT_INDEXED;
2996 case DRM_FORMAT_RGB565:
2997 return PLANE_CTL_FORMAT_RGB_565;
2998 case DRM_FORMAT_XBGR8888:
2999 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3000 case DRM_FORMAT_XRGB8888:
3001 return PLANE_CTL_FORMAT_XRGB_8888;
3002 /*
3003 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3004 * to be already pre-multiplied. We need to add a knob (or a different
3005 * DRM_FORMAT) for user-space to configure that.
3006 */
3007 case DRM_FORMAT_ABGR8888:
3008 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3009 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3010 case DRM_FORMAT_ARGB8888:
3011 return PLANE_CTL_FORMAT_XRGB_8888 |
3012 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3013 case DRM_FORMAT_XRGB2101010:
3014 return PLANE_CTL_FORMAT_XRGB_2101010;
3015 case DRM_FORMAT_XBGR2101010:
3016 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3017 case DRM_FORMAT_YUYV:
3018 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3019 case DRM_FORMAT_YVYU:
3020 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3021 case DRM_FORMAT_UYVY:
3022 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3023 case DRM_FORMAT_VYUY:
3024 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3025 default:
3026 MISSING_CASE(pixel_format);
3027 }
3028
3029 return 0;
3030 }
3031
3032 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3033 {
3034 switch (fb_modifier) {
3035 case DRM_FORMAT_MOD_NONE:
3036 break;
3037 case I915_FORMAT_MOD_X_TILED:
3038 return PLANE_CTL_TILED_X;
3039 case I915_FORMAT_MOD_Y_TILED:
3040 return PLANE_CTL_TILED_Y;
3041 case I915_FORMAT_MOD_Yf_TILED:
3042 return PLANE_CTL_TILED_YF;
3043 default:
3044 MISSING_CASE(fb_modifier);
3045 }
3046
3047 return 0;
3048 }
3049
3050 u32 skl_plane_ctl_rotation(unsigned int rotation)
3051 {
3052 switch (rotation) {
3053 case BIT(DRM_ROTATE_0):
3054 break;
3055 /*
3056 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3057 * while i915 HW rotation is clockwise, thats why this swapping.
3058 */
3059 case BIT(DRM_ROTATE_90):
3060 return PLANE_CTL_ROTATE_270;
3061 case BIT(DRM_ROTATE_180):
3062 return PLANE_CTL_ROTATE_180;
3063 case BIT(DRM_ROTATE_270):
3064 return PLANE_CTL_ROTATE_90;
3065 default:
3066 MISSING_CASE(rotation);
3067 }
3068
3069 return 0;
3070 }
3071
3072 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3073 struct drm_framebuffer *fb,
3074 int x, int y)
3075 {
3076 struct drm_device *dev = crtc->dev;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3079 struct drm_plane *plane = crtc->primary;
3080 bool visible = to_intel_plane_state(plane->state)->visible;
3081 struct drm_i915_gem_object *obj;
3082 int pipe = intel_crtc->pipe;
3083 u32 plane_ctl, stride_div, stride;
3084 u32 tile_height, plane_offset, plane_size;
3085 unsigned int rotation;
3086 int x_offset, y_offset;
3087 unsigned long surf_addr;
3088 struct intel_crtc_state *crtc_state = intel_crtc->config;
3089 struct intel_plane_state *plane_state;
3090 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3091 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3092 int scaler_id = -1;
3093
3094 plane_state = to_intel_plane_state(plane->state);
3095
3096 if (!visible || !fb) {
3097 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3098 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3099 POSTING_READ(PLANE_CTL(pipe, 0));
3100 return;
3101 }
3102
3103 plane_ctl = PLANE_CTL_ENABLE |
3104 PLANE_CTL_PIPE_GAMMA_ENABLE |
3105 PLANE_CTL_PIPE_CSC_ENABLE;
3106
3107 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3108 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3109 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3110
3111 rotation = plane->state->rotation;
3112 plane_ctl |= skl_plane_ctl_rotation(rotation);
3113
3114 obj = intel_fb_obj(fb);
3115 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3116 fb->pixel_format);
3117 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3118
3119 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3120
3121 scaler_id = plane_state->scaler_id;
3122 src_x = plane_state->src.x1 >> 16;
3123 src_y = plane_state->src.y1 >> 16;
3124 src_w = drm_rect_width(&plane_state->src) >> 16;
3125 src_h = drm_rect_height(&plane_state->src) >> 16;
3126 dst_x = plane_state->dst.x1;
3127 dst_y = plane_state->dst.y1;
3128 dst_w = drm_rect_width(&plane_state->dst);
3129 dst_h = drm_rect_height(&plane_state->dst);
3130
3131 WARN_ON(x != src_x || y != src_y);
3132
3133 if (intel_rotation_90_or_270(rotation)) {
3134 /* stride = Surface height in tiles */
3135 tile_height = intel_tile_height(dev, fb->pixel_format,
3136 fb->modifier[0], 0);
3137 stride = DIV_ROUND_UP(fb->height, tile_height);
3138 x_offset = stride * tile_height - y - src_h;
3139 y_offset = x;
3140 plane_size = (src_w - 1) << 16 | (src_h - 1);
3141 } else {
3142 stride = fb->pitches[0] / stride_div;
3143 x_offset = x;
3144 y_offset = y;
3145 plane_size = (src_h - 1) << 16 | (src_w - 1);
3146 }
3147 plane_offset = y_offset << 16 | x_offset;
3148
3149 intel_crtc->adjusted_x = x_offset;
3150 intel_crtc->adjusted_y = y_offset;
3151
3152 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3153 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3154 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3155 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3156
3157 if (scaler_id >= 0) {
3158 uint32_t ps_ctrl = 0;
3159
3160 WARN_ON(!dst_w || !dst_h);
3161 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3162 crtc_state->scaler_state.scalers[scaler_id].mode;
3163 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3164 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3165 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3166 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3167 I915_WRITE(PLANE_POS(pipe, 0), 0);
3168 } else {
3169 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3170 }
3171
3172 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3173
3174 POSTING_READ(PLANE_SURF(pipe, 0));
3175 }
3176
3177 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3178 static int
3179 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3180 int x, int y, enum mode_set_atomic state)
3181 {
3182 struct drm_device *dev = crtc->dev;
3183 struct drm_i915_private *dev_priv = dev->dev_private;
3184
3185 if (dev_priv->fbc.disable_fbc)
3186 dev_priv->fbc.disable_fbc(dev_priv);
3187
3188 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3189
3190 return 0;
3191 }
3192
3193 static void intel_complete_page_flips(struct drm_device *dev)
3194 {
3195 struct drm_crtc *crtc;
3196
3197 for_each_crtc(dev, crtc) {
3198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3199 enum plane plane = intel_crtc->plane;
3200
3201 intel_prepare_page_flip(dev, plane);
3202 intel_finish_page_flip_plane(dev, plane);
3203 }
3204 }
3205
3206 static void intel_update_primary_planes(struct drm_device *dev)
3207 {
3208 struct drm_crtc *crtc;
3209
3210 for_each_crtc(dev, crtc) {
3211 struct intel_plane *plane = to_intel_plane(crtc->primary);
3212 struct intel_plane_state *plane_state;
3213
3214 drm_modeset_lock_crtc(crtc, &plane->base);
3215
3216 plane_state = to_intel_plane_state(plane->base.state);
3217
3218 if (plane_state->base.fb)
3219 plane->commit_plane(&plane->base, plane_state);
3220
3221 drm_modeset_unlock_crtc(crtc);
3222 }
3223 }
3224
3225 void intel_prepare_reset(struct drm_device *dev)
3226 {
3227 /* no reset support for gen2 */
3228 if (IS_GEN2(dev))
3229 return;
3230
3231 /* reset doesn't touch the display */
3232 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3233 return;
3234
3235 drm_modeset_lock_all(dev);
3236 /*
3237 * Disabling the crtcs gracefully seems nicer. Also the
3238 * g33 docs say we should at least disable all the planes.
3239 */
3240 intel_display_suspend(dev);
3241 }
3242
3243 void intel_finish_reset(struct drm_device *dev)
3244 {
3245 struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247 /*
3248 * Flips in the rings will be nuked by the reset,
3249 * so complete all pending flips so that user space
3250 * will get its events and not get stuck.
3251 */
3252 intel_complete_page_flips(dev);
3253
3254 /* no reset support for gen2 */
3255 if (IS_GEN2(dev))
3256 return;
3257
3258 /* reset doesn't touch the display */
3259 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3260 /*
3261 * Flips in the rings have been nuked by the reset,
3262 * so update the base address of all primary
3263 * planes to the the last fb to make sure we're
3264 * showing the correct fb after a reset.
3265 *
3266 * FIXME: Atomic will make this obsolete since we won't schedule
3267 * CS-based flips (which might get lost in gpu resets) any more.
3268 */
3269 intel_update_primary_planes(dev);
3270 return;
3271 }
3272
3273 /*
3274 * The display has been reset as well,
3275 * so need a full re-initialization.
3276 */
3277 intel_runtime_pm_disable_interrupts(dev_priv);
3278 intel_runtime_pm_enable_interrupts(dev_priv);
3279
3280 intel_modeset_init_hw(dev);
3281
3282 spin_lock_irq(&dev_priv->irq_lock);
3283 if (dev_priv->display.hpd_irq_setup)
3284 dev_priv->display.hpd_irq_setup(dev);
3285 spin_unlock_irq(&dev_priv->irq_lock);
3286
3287 intel_display_resume(dev);
3288
3289 intel_hpd_init(dev_priv);
3290
3291 drm_modeset_unlock_all(dev);
3292 }
3293
3294 static void
3295 intel_finish_fb(struct drm_framebuffer *old_fb)
3296 {
3297 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3298 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3299 bool was_interruptible = dev_priv->mm.interruptible;
3300 int ret;
3301
3302 /* Big Hammer, we also need to ensure that any pending
3303 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3304 * current scanout is retired before unpinning the old
3305 * framebuffer. Note that we rely on userspace rendering
3306 * into the buffer attached to the pipe they are waiting
3307 * on. If not, userspace generates a GPU hang with IPEHR
3308 * point to the MI_WAIT_FOR_EVENT.
3309 *
3310 * This should only fail upon a hung GPU, in which case we
3311 * can safely continue.
3312 */
3313 dev_priv->mm.interruptible = false;
3314 ret = i915_gem_object_wait_rendering(obj, true);
3315 dev_priv->mm.interruptible = was_interruptible;
3316
3317 WARN_ON(ret);
3318 }
3319
3320 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3321 {
3322 struct drm_device *dev = crtc->dev;
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3325 bool pending;
3326
3327 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3328 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3329 return false;
3330
3331 spin_lock_irq(&dev->event_lock);
3332 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3333 spin_unlock_irq(&dev->event_lock);
3334
3335 return pending;
3336 }
3337
3338 static void intel_update_pipe_config(struct intel_crtc *crtc,
3339 struct intel_crtc_state *old_crtc_state)
3340 {
3341 struct drm_device *dev = crtc->base.dev;
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343 struct intel_crtc_state *pipe_config =
3344 to_intel_crtc_state(crtc->base.state);
3345
3346 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3347 crtc->base.mode = crtc->base.state->mode;
3348
3349 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3350 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3351 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3352
3353 if (HAS_DDI(dev))
3354 intel_set_pipe_csc(&crtc->base);
3355
3356 /*
3357 * Update pipe size and adjust fitter if needed: the reason for this is
3358 * that in compute_mode_changes we check the native mode (not the pfit
3359 * mode) to see if we can flip rather than do a full mode set. In the
3360 * fastboot case, we'll flip, but if we don't update the pipesrc and
3361 * pfit state, we'll end up with a big fb scanned out into the wrong
3362 * sized surface.
3363 */
3364
3365 I915_WRITE(PIPESRC(crtc->pipe),
3366 ((pipe_config->pipe_src_w - 1) << 16) |
3367 (pipe_config->pipe_src_h - 1));
3368
3369 /* on skylake this is done by detaching scalers */
3370 if (INTEL_INFO(dev)->gen >= 9) {
3371 skl_detach_scalers(crtc);
3372
3373 if (pipe_config->pch_pfit.enabled)
3374 skylake_pfit_enable(crtc);
3375 } else if (HAS_PCH_SPLIT(dev)) {
3376 if (pipe_config->pch_pfit.enabled)
3377 ironlake_pfit_enable(crtc);
3378 else if (old_crtc_state->pch_pfit.enabled)
3379 ironlake_pfit_disable(crtc, true);
3380 }
3381 }
3382
3383 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3384 {
3385 struct drm_device *dev = crtc->dev;
3386 struct drm_i915_private *dev_priv = dev->dev_private;
3387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3388 int pipe = intel_crtc->pipe;
3389 u32 reg, temp;
3390
3391 /* enable normal train */
3392 reg = FDI_TX_CTL(pipe);
3393 temp = I915_READ(reg);
3394 if (IS_IVYBRIDGE(dev)) {
3395 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3396 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3397 } else {
3398 temp &= ~FDI_LINK_TRAIN_NONE;
3399 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3400 }
3401 I915_WRITE(reg, temp);
3402
3403 reg = FDI_RX_CTL(pipe);
3404 temp = I915_READ(reg);
3405 if (HAS_PCH_CPT(dev)) {
3406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3407 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3408 } else {
3409 temp &= ~FDI_LINK_TRAIN_NONE;
3410 temp |= FDI_LINK_TRAIN_NONE;
3411 }
3412 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3413
3414 /* wait one idle pattern time */
3415 POSTING_READ(reg);
3416 udelay(1000);
3417
3418 /* IVB wants error correction enabled */
3419 if (IS_IVYBRIDGE(dev))
3420 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3421 FDI_FE_ERRC_ENABLE);
3422 }
3423
3424 /* The FDI link training functions for ILK/Ibexpeak. */
3425 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3426 {
3427 struct drm_device *dev = crtc->dev;
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3430 int pipe = intel_crtc->pipe;
3431 u32 reg, temp, tries;
3432
3433 /* FDI needs bits from pipe first */
3434 assert_pipe_enabled(dev_priv, pipe);
3435
3436 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3437 for train result */
3438 reg = FDI_RX_IMR(pipe);
3439 temp = I915_READ(reg);
3440 temp &= ~FDI_RX_SYMBOL_LOCK;
3441 temp &= ~FDI_RX_BIT_LOCK;
3442 I915_WRITE(reg, temp);
3443 I915_READ(reg);
3444 udelay(150);
3445
3446 /* enable CPU FDI TX and PCH FDI RX */
3447 reg = FDI_TX_CTL(pipe);
3448 temp = I915_READ(reg);
3449 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3450 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3451 temp &= ~FDI_LINK_TRAIN_NONE;
3452 temp |= FDI_LINK_TRAIN_PATTERN_1;
3453 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3454
3455 reg = FDI_RX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_1;
3459 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3460
3461 POSTING_READ(reg);
3462 udelay(150);
3463
3464 /* Ironlake workaround, enable clock pointer after FDI enable*/
3465 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3466 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3467 FDI_RX_PHASE_SYNC_POINTER_EN);
3468
3469 reg = FDI_RX_IIR(pipe);
3470 for (tries = 0; tries < 5; tries++) {
3471 temp = I915_READ(reg);
3472 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3473
3474 if ((temp & FDI_RX_BIT_LOCK)) {
3475 DRM_DEBUG_KMS("FDI train 1 done.\n");
3476 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3477 break;
3478 }
3479 }
3480 if (tries == 5)
3481 DRM_ERROR("FDI train 1 fail!\n");
3482
3483 /* Train 2 */
3484 reg = FDI_TX_CTL(pipe);
3485 temp = I915_READ(reg);
3486 temp &= ~FDI_LINK_TRAIN_NONE;
3487 temp |= FDI_LINK_TRAIN_PATTERN_2;
3488 I915_WRITE(reg, temp);
3489
3490 reg = FDI_RX_CTL(pipe);
3491 temp = I915_READ(reg);
3492 temp &= ~FDI_LINK_TRAIN_NONE;
3493 temp |= FDI_LINK_TRAIN_PATTERN_2;
3494 I915_WRITE(reg, temp);
3495
3496 POSTING_READ(reg);
3497 udelay(150);
3498
3499 reg = FDI_RX_IIR(pipe);
3500 for (tries = 0; tries < 5; tries++) {
3501 temp = I915_READ(reg);
3502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3503
3504 if (temp & FDI_RX_SYMBOL_LOCK) {
3505 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3506 DRM_DEBUG_KMS("FDI train 2 done.\n");
3507 break;
3508 }
3509 }
3510 if (tries == 5)
3511 DRM_ERROR("FDI train 2 fail!\n");
3512
3513 DRM_DEBUG_KMS("FDI train done\n");
3514
3515 }
3516
3517 static const int snb_b_fdi_train_param[] = {
3518 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3519 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3520 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3521 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3522 };
3523
3524 /* The FDI link training functions for SNB/Cougarpoint. */
3525 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3526 {
3527 struct drm_device *dev = crtc->dev;
3528 struct drm_i915_private *dev_priv = dev->dev_private;
3529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3530 int pipe = intel_crtc->pipe;
3531 u32 reg, temp, i, retry;
3532
3533 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3534 for train result */
3535 reg = FDI_RX_IMR(pipe);
3536 temp = I915_READ(reg);
3537 temp &= ~FDI_RX_SYMBOL_LOCK;
3538 temp &= ~FDI_RX_BIT_LOCK;
3539 I915_WRITE(reg, temp);
3540
3541 POSTING_READ(reg);
3542 udelay(150);
3543
3544 /* enable CPU FDI TX and PCH FDI RX */
3545 reg = FDI_TX_CTL(pipe);
3546 temp = I915_READ(reg);
3547 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3548 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3549 temp &= ~FDI_LINK_TRAIN_NONE;
3550 temp |= FDI_LINK_TRAIN_PATTERN_1;
3551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3552 /* SNB-B */
3553 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3554 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3555
3556 I915_WRITE(FDI_RX_MISC(pipe),
3557 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3558
3559 reg = FDI_RX_CTL(pipe);
3560 temp = I915_READ(reg);
3561 if (HAS_PCH_CPT(dev)) {
3562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3563 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3564 } else {
3565 temp &= ~FDI_LINK_TRAIN_NONE;
3566 temp |= FDI_LINK_TRAIN_PATTERN_1;
3567 }
3568 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3569
3570 POSTING_READ(reg);
3571 udelay(150);
3572
3573 for (i = 0; i < 4; i++) {
3574 reg = FDI_TX_CTL(pipe);
3575 temp = I915_READ(reg);
3576 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577 temp |= snb_b_fdi_train_param[i];
3578 I915_WRITE(reg, temp);
3579
3580 POSTING_READ(reg);
3581 udelay(500);
3582
3583 for (retry = 0; retry < 5; retry++) {
3584 reg = FDI_RX_IIR(pipe);
3585 temp = I915_READ(reg);
3586 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3587 if (temp & FDI_RX_BIT_LOCK) {
3588 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3589 DRM_DEBUG_KMS("FDI train 1 done.\n");
3590 break;
3591 }
3592 udelay(50);
3593 }
3594 if (retry < 5)
3595 break;
3596 }
3597 if (i == 4)
3598 DRM_ERROR("FDI train 1 fail!\n");
3599
3600 /* Train 2 */
3601 reg = FDI_TX_CTL(pipe);
3602 temp = I915_READ(reg);
3603 temp &= ~FDI_LINK_TRAIN_NONE;
3604 temp |= FDI_LINK_TRAIN_PATTERN_2;
3605 if (IS_GEN6(dev)) {
3606 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3607 /* SNB-B */
3608 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3609 }
3610 I915_WRITE(reg, temp);
3611
3612 reg = FDI_RX_CTL(pipe);
3613 temp = I915_READ(reg);
3614 if (HAS_PCH_CPT(dev)) {
3615 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3616 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3617 } else {
3618 temp &= ~FDI_LINK_TRAIN_NONE;
3619 temp |= FDI_LINK_TRAIN_PATTERN_2;
3620 }
3621 I915_WRITE(reg, temp);
3622
3623 POSTING_READ(reg);
3624 udelay(150);
3625
3626 for (i = 0; i < 4; i++) {
3627 reg = FDI_TX_CTL(pipe);
3628 temp = I915_READ(reg);
3629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3630 temp |= snb_b_fdi_train_param[i];
3631 I915_WRITE(reg, temp);
3632
3633 POSTING_READ(reg);
3634 udelay(500);
3635
3636 for (retry = 0; retry < 5; retry++) {
3637 reg = FDI_RX_IIR(pipe);
3638 temp = I915_READ(reg);
3639 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3640 if (temp & FDI_RX_SYMBOL_LOCK) {
3641 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3642 DRM_DEBUG_KMS("FDI train 2 done.\n");
3643 break;
3644 }
3645 udelay(50);
3646 }
3647 if (retry < 5)
3648 break;
3649 }
3650 if (i == 4)
3651 DRM_ERROR("FDI train 2 fail!\n");
3652
3653 DRM_DEBUG_KMS("FDI train done.\n");
3654 }
3655
3656 /* Manual link training for Ivy Bridge A0 parts */
3657 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3658 {
3659 struct drm_device *dev = crtc->dev;
3660 struct drm_i915_private *dev_priv = dev->dev_private;
3661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3662 int pipe = intel_crtc->pipe;
3663 u32 reg, temp, i, j;
3664
3665 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3666 for train result */
3667 reg = FDI_RX_IMR(pipe);
3668 temp = I915_READ(reg);
3669 temp &= ~FDI_RX_SYMBOL_LOCK;
3670 temp &= ~FDI_RX_BIT_LOCK;
3671 I915_WRITE(reg, temp);
3672
3673 POSTING_READ(reg);
3674 udelay(150);
3675
3676 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3677 I915_READ(FDI_RX_IIR(pipe)));
3678
3679 /* Try each vswing and preemphasis setting twice before moving on */
3680 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3681 /* disable first in case we need to retry */
3682 reg = FDI_TX_CTL(pipe);
3683 temp = I915_READ(reg);
3684 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3685 temp &= ~FDI_TX_ENABLE;
3686 I915_WRITE(reg, temp);
3687
3688 reg = FDI_RX_CTL(pipe);
3689 temp = I915_READ(reg);
3690 temp &= ~FDI_LINK_TRAIN_AUTO;
3691 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3692 temp &= ~FDI_RX_ENABLE;
3693 I915_WRITE(reg, temp);
3694
3695 /* enable CPU FDI TX and PCH FDI RX */
3696 reg = FDI_TX_CTL(pipe);
3697 temp = I915_READ(reg);
3698 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3699 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3700 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3701 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3702 temp |= snb_b_fdi_train_param[j/2];
3703 temp |= FDI_COMPOSITE_SYNC;
3704 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3705
3706 I915_WRITE(FDI_RX_MISC(pipe),
3707 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3708
3709 reg = FDI_RX_CTL(pipe);
3710 temp = I915_READ(reg);
3711 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3712 temp |= FDI_COMPOSITE_SYNC;
3713 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3714
3715 POSTING_READ(reg);
3716 udelay(1); /* should be 0.5us */
3717
3718 for (i = 0; i < 4; i++) {
3719 reg = FDI_RX_IIR(pipe);
3720 temp = I915_READ(reg);
3721 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3722
3723 if (temp & FDI_RX_BIT_LOCK ||
3724 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3725 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3726 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3727 i);
3728 break;
3729 }
3730 udelay(1); /* should be 0.5us */
3731 }
3732 if (i == 4) {
3733 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3734 continue;
3735 }
3736
3737 /* Train 2 */
3738 reg = FDI_TX_CTL(pipe);
3739 temp = I915_READ(reg);
3740 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3741 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3742 I915_WRITE(reg, temp);
3743
3744 reg = FDI_RX_CTL(pipe);
3745 temp = I915_READ(reg);
3746 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3747 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3748 I915_WRITE(reg, temp);
3749
3750 POSTING_READ(reg);
3751 udelay(2); /* should be 1.5us */
3752
3753 for (i = 0; i < 4; i++) {
3754 reg = FDI_RX_IIR(pipe);
3755 temp = I915_READ(reg);
3756 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3757
3758 if (temp & FDI_RX_SYMBOL_LOCK ||
3759 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3760 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3761 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3762 i);
3763 goto train_done;
3764 }
3765 udelay(2); /* should be 1.5us */
3766 }
3767 if (i == 4)
3768 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3769 }
3770
3771 train_done:
3772 DRM_DEBUG_KMS("FDI train done.\n");
3773 }
3774
3775 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3776 {
3777 struct drm_device *dev = intel_crtc->base.dev;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779 int pipe = intel_crtc->pipe;
3780 u32 reg, temp;
3781
3782
3783 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3784 reg = FDI_RX_CTL(pipe);
3785 temp = I915_READ(reg);
3786 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3787 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3788 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3789 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3790
3791 POSTING_READ(reg);
3792 udelay(200);
3793
3794 /* Switch from Rawclk to PCDclk */
3795 temp = I915_READ(reg);
3796 I915_WRITE(reg, temp | FDI_PCDCLK);
3797
3798 POSTING_READ(reg);
3799 udelay(200);
3800
3801 /* Enable CPU FDI TX PLL, always on for Ironlake */
3802 reg = FDI_TX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3805 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3806
3807 POSTING_READ(reg);
3808 udelay(100);
3809 }
3810 }
3811
3812 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3813 {
3814 struct drm_device *dev = intel_crtc->base.dev;
3815 struct drm_i915_private *dev_priv = dev->dev_private;
3816 int pipe = intel_crtc->pipe;
3817 u32 reg, temp;
3818
3819 /* Switch from PCDclk to Rawclk */
3820 reg = FDI_RX_CTL(pipe);
3821 temp = I915_READ(reg);
3822 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3823
3824 /* Disable CPU FDI TX PLL */
3825 reg = FDI_TX_CTL(pipe);
3826 temp = I915_READ(reg);
3827 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3828
3829 POSTING_READ(reg);
3830 udelay(100);
3831
3832 reg = FDI_RX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3835
3836 /* Wait for the clocks to turn off. */
3837 POSTING_READ(reg);
3838 udelay(100);
3839 }
3840
3841 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3842 {
3843 struct drm_device *dev = crtc->dev;
3844 struct drm_i915_private *dev_priv = dev->dev_private;
3845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846 int pipe = intel_crtc->pipe;
3847 u32 reg, temp;
3848
3849 /* disable CPU FDI tx and PCH FDI rx */
3850 reg = FDI_TX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3853 POSTING_READ(reg);
3854
3855 reg = FDI_RX_CTL(pipe);
3856 temp = I915_READ(reg);
3857 temp &= ~(0x7 << 16);
3858 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3859 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3860
3861 POSTING_READ(reg);
3862 udelay(100);
3863
3864 /* Ironlake workaround, disable clock pointer after downing FDI */
3865 if (HAS_PCH_IBX(dev))
3866 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3867
3868 /* still set train pattern 1 */
3869 reg = FDI_TX_CTL(pipe);
3870 temp = I915_READ(reg);
3871 temp &= ~FDI_LINK_TRAIN_NONE;
3872 temp |= FDI_LINK_TRAIN_PATTERN_1;
3873 I915_WRITE(reg, temp);
3874
3875 reg = FDI_RX_CTL(pipe);
3876 temp = I915_READ(reg);
3877 if (HAS_PCH_CPT(dev)) {
3878 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3879 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3880 } else {
3881 temp &= ~FDI_LINK_TRAIN_NONE;
3882 temp |= FDI_LINK_TRAIN_PATTERN_1;
3883 }
3884 /* BPC in FDI rx is consistent with that in PIPECONF */
3885 temp &= ~(0x07 << 16);
3886 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3887 I915_WRITE(reg, temp);
3888
3889 POSTING_READ(reg);
3890 udelay(100);
3891 }
3892
3893 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3894 {
3895 struct intel_crtc *crtc;
3896
3897 /* Note that we don't need to be called with mode_config.lock here
3898 * as our list of CRTC objects is static for the lifetime of the
3899 * device and so cannot disappear as we iterate. Similarly, we can
3900 * happily treat the predicates as racy, atomic checks as userspace
3901 * cannot claim and pin a new fb without at least acquring the
3902 * struct_mutex and so serialising with us.
3903 */
3904 for_each_intel_crtc(dev, crtc) {
3905 if (atomic_read(&crtc->unpin_work_count) == 0)
3906 continue;
3907
3908 if (crtc->unpin_work)
3909 intel_wait_for_vblank(dev, crtc->pipe);
3910
3911 return true;
3912 }
3913
3914 return false;
3915 }
3916
3917 static void page_flip_completed(struct intel_crtc *intel_crtc)
3918 {
3919 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3920 struct intel_unpin_work *work = intel_crtc->unpin_work;
3921
3922 /* ensure that the unpin work is consistent wrt ->pending. */
3923 smp_rmb();
3924 intel_crtc->unpin_work = NULL;
3925
3926 if (work->event)
3927 drm_send_vblank_event(intel_crtc->base.dev,
3928 intel_crtc->pipe,
3929 work->event);
3930
3931 drm_crtc_vblank_put(&intel_crtc->base);
3932
3933 wake_up_all(&dev_priv->pending_flip_queue);
3934 queue_work(dev_priv->wq, &work->work);
3935
3936 trace_i915_flip_complete(intel_crtc->plane,
3937 work->pending_flip_obj);
3938 }
3939
3940 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3941 {
3942 struct drm_device *dev = crtc->dev;
3943 struct drm_i915_private *dev_priv = dev->dev_private;
3944
3945 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3946 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3947 !intel_crtc_has_pending_flip(crtc),
3948 60*HZ) == 0)) {
3949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3950
3951 spin_lock_irq(&dev->event_lock);
3952 if (intel_crtc->unpin_work) {
3953 WARN_ONCE(1, "Removing stuck page flip\n");
3954 page_flip_completed(intel_crtc);
3955 }
3956 spin_unlock_irq(&dev->event_lock);
3957 }
3958
3959 if (crtc->primary->fb) {
3960 mutex_lock(&dev->struct_mutex);
3961 intel_finish_fb(crtc->primary->fb);
3962 mutex_unlock(&dev->struct_mutex);
3963 }
3964 }
3965
3966 /* Program iCLKIP clock to the desired frequency */
3967 static void lpt_program_iclkip(struct drm_crtc *crtc)
3968 {
3969 struct drm_device *dev = crtc->dev;
3970 struct drm_i915_private *dev_priv = dev->dev_private;
3971 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3972 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3973 u32 temp;
3974
3975 mutex_lock(&dev_priv->sb_lock);
3976
3977 /* It is necessary to ungate the pixclk gate prior to programming
3978 * the divisors, and gate it back when it is done.
3979 */
3980 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3981
3982 /* Disable SSCCTL */
3983 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3984 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3985 SBI_SSCCTL_DISABLE,
3986 SBI_ICLK);
3987
3988 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3989 if (clock == 20000) {
3990 auxdiv = 1;
3991 divsel = 0x41;
3992 phaseinc = 0x20;
3993 } else {
3994 /* The iCLK virtual clock root frequency is in MHz,
3995 * but the adjusted_mode->crtc_clock in in KHz. To get the
3996 * divisors, it is necessary to divide one by another, so we
3997 * convert the virtual clock precision to KHz here for higher
3998 * precision.
3999 */
4000 u32 iclk_virtual_root_freq = 172800 * 1000;
4001 u32 iclk_pi_range = 64;
4002 u32 desired_divisor, msb_divisor_value, pi_value;
4003
4004 desired_divisor = (iclk_virtual_root_freq / clock);
4005 msb_divisor_value = desired_divisor / iclk_pi_range;
4006 pi_value = desired_divisor % iclk_pi_range;
4007
4008 auxdiv = 0;
4009 divsel = msb_divisor_value - 2;
4010 phaseinc = pi_value;
4011 }
4012
4013 /* This should not happen with any sane values */
4014 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4015 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4016 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4017 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4018
4019 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4020 clock,
4021 auxdiv,
4022 divsel,
4023 phasedir,
4024 phaseinc);
4025
4026 /* Program SSCDIVINTPHASE6 */
4027 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4028 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4029 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4030 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4031 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4032 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4033 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4034 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4035
4036 /* Program SSCAUXDIV */
4037 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4038 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4039 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4040 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4041
4042 /* Enable modulator and associated divider */
4043 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4044 temp &= ~SBI_SSCCTL_DISABLE;
4045 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4046
4047 /* Wait for initialization time */
4048 udelay(24);
4049
4050 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4051
4052 mutex_unlock(&dev_priv->sb_lock);
4053 }
4054
4055 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4056 enum pipe pch_transcoder)
4057 {
4058 struct drm_device *dev = crtc->base.dev;
4059 struct drm_i915_private *dev_priv = dev->dev_private;
4060 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4061
4062 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4063 I915_READ(HTOTAL(cpu_transcoder)));
4064 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4065 I915_READ(HBLANK(cpu_transcoder)));
4066 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4067 I915_READ(HSYNC(cpu_transcoder)));
4068
4069 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4070 I915_READ(VTOTAL(cpu_transcoder)));
4071 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4072 I915_READ(VBLANK(cpu_transcoder)));
4073 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4074 I915_READ(VSYNC(cpu_transcoder)));
4075 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4076 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4077 }
4078
4079 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4080 {
4081 struct drm_i915_private *dev_priv = dev->dev_private;
4082 uint32_t temp;
4083
4084 temp = I915_READ(SOUTH_CHICKEN1);
4085 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4086 return;
4087
4088 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4089 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4090
4091 temp &= ~FDI_BC_BIFURCATION_SELECT;
4092 if (enable)
4093 temp |= FDI_BC_BIFURCATION_SELECT;
4094
4095 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4096 I915_WRITE(SOUTH_CHICKEN1, temp);
4097 POSTING_READ(SOUTH_CHICKEN1);
4098 }
4099
4100 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4101 {
4102 struct drm_device *dev = intel_crtc->base.dev;
4103
4104 switch (intel_crtc->pipe) {
4105 case PIPE_A:
4106 break;
4107 case PIPE_B:
4108 if (intel_crtc->config->fdi_lanes > 2)
4109 cpt_set_fdi_bc_bifurcation(dev, false);
4110 else
4111 cpt_set_fdi_bc_bifurcation(dev, true);
4112
4113 break;
4114 case PIPE_C:
4115 cpt_set_fdi_bc_bifurcation(dev, true);
4116
4117 break;
4118 default:
4119 BUG();
4120 }
4121 }
4122
4123 /*
4124 * Enable PCH resources required for PCH ports:
4125 * - PCH PLLs
4126 * - FDI training & RX/TX
4127 * - update transcoder timings
4128 * - DP transcoding bits
4129 * - transcoder
4130 */
4131 static void ironlake_pch_enable(struct drm_crtc *crtc)
4132 {
4133 struct drm_device *dev = crtc->dev;
4134 struct drm_i915_private *dev_priv = dev->dev_private;
4135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4136 int pipe = intel_crtc->pipe;
4137 u32 reg, temp;
4138
4139 assert_pch_transcoder_disabled(dev_priv, pipe);
4140
4141 if (IS_IVYBRIDGE(dev))
4142 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4143
4144 /* Write the TU size bits before fdi link training, so that error
4145 * detection works. */
4146 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4147 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4148
4149 /* For PCH output, training FDI link */
4150 dev_priv->display.fdi_link_train(crtc);
4151
4152 /* We need to program the right clock selection before writing the pixel
4153 * mutliplier into the DPLL. */
4154 if (HAS_PCH_CPT(dev)) {
4155 u32 sel;
4156
4157 temp = I915_READ(PCH_DPLL_SEL);
4158 temp |= TRANS_DPLL_ENABLE(pipe);
4159 sel = TRANS_DPLLB_SEL(pipe);
4160 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4161 temp |= sel;
4162 else
4163 temp &= ~sel;
4164 I915_WRITE(PCH_DPLL_SEL, temp);
4165 }
4166
4167 /* XXX: pch pll's can be enabled any time before we enable the PCH
4168 * transcoder, and we actually should do this to not upset any PCH
4169 * transcoder that already use the clock when we share it.
4170 *
4171 * Note that enable_shared_dpll tries to do the right thing, but
4172 * get_shared_dpll unconditionally resets the pll - we need that to have
4173 * the right LVDS enable sequence. */
4174 intel_enable_shared_dpll(intel_crtc);
4175
4176 /* set transcoder timing, panel must allow it */
4177 assert_panel_unlocked(dev_priv, pipe);
4178 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4179
4180 intel_fdi_normal_train(crtc);
4181
4182 /* For PCH DP, enable TRANS_DP_CTL */
4183 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4184 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4185 reg = TRANS_DP_CTL(pipe);
4186 temp = I915_READ(reg);
4187 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4188 TRANS_DP_SYNC_MASK |
4189 TRANS_DP_BPC_MASK);
4190 temp |= TRANS_DP_OUTPUT_ENABLE;
4191 temp |= bpc << 9; /* same format but at 11:9 */
4192
4193 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4194 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4195 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4196 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4197
4198 switch (intel_trans_dp_port_sel(crtc)) {
4199 case PCH_DP_B:
4200 temp |= TRANS_DP_PORT_SEL_B;
4201 break;
4202 case PCH_DP_C:
4203 temp |= TRANS_DP_PORT_SEL_C;
4204 break;
4205 case PCH_DP_D:
4206 temp |= TRANS_DP_PORT_SEL_D;
4207 break;
4208 default:
4209 BUG();
4210 }
4211
4212 I915_WRITE(reg, temp);
4213 }
4214
4215 ironlake_enable_pch_transcoder(dev_priv, pipe);
4216 }
4217
4218 static void lpt_pch_enable(struct drm_crtc *crtc)
4219 {
4220 struct drm_device *dev = crtc->dev;
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4223 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4224
4225 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4226
4227 lpt_program_iclkip(crtc);
4228
4229 /* Set transcoder timing. */
4230 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4231
4232 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4233 }
4234
4235 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4236 struct intel_crtc_state *crtc_state)
4237 {
4238 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4239 struct intel_shared_dpll *pll;
4240 struct intel_shared_dpll_config *shared_dpll;
4241 enum intel_dpll_id i;
4242 int max = dev_priv->num_shared_dpll;
4243
4244 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4245
4246 if (HAS_PCH_IBX(dev_priv->dev)) {
4247 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4248 i = (enum intel_dpll_id) crtc->pipe;
4249 pll = &dev_priv->shared_dplls[i];
4250
4251 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4252 crtc->base.base.id, pll->name);
4253
4254 WARN_ON(shared_dpll[i].crtc_mask);
4255
4256 goto found;
4257 }
4258
4259 if (IS_BROXTON(dev_priv->dev)) {
4260 /* PLL is attached to port in bxt */
4261 struct intel_encoder *encoder;
4262 struct intel_digital_port *intel_dig_port;
4263
4264 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4265 if (WARN_ON(!encoder))
4266 return NULL;
4267
4268 intel_dig_port = enc_to_dig_port(&encoder->base);
4269 /* 1:1 mapping between ports and PLLs */
4270 i = (enum intel_dpll_id)intel_dig_port->port;
4271 pll = &dev_priv->shared_dplls[i];
4272 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4273 crtc->base.base.id, pll->name);
4274 WARN_ON(shared_dpll[i].crtc_mask);
4275
4276 goto found;
4277 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4278 /* Do not consider SPLL */
4279 max = 2;
4280
4281 for (i = 0; i < max; i++) {
4282 pll = &dev_priv->shared_dplls[i];
4283
4284 /* Only want to check enabled timings first */
4285 if (shared_dpll[i].crtc_mask == 0)
4286 continue;
4287
4288 if (memcmp(&crtc_state->dpll_hw_state,
4289 &shared_dpll[i].hw_state,
4290 sizeof(crtc_state->dpll_hw_state)) == 0) {
4291 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4292 crtc->base.base.id, pll->name,
4293 shared_dpll[i].crtc_mask,
4294 pll->active);
4295 goto found;
4296 }
4297 }
4298
4299 /* Ok no matching timings, maybe there's a free one? */
4300 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4301 pll = &dev_priv->shared_dplls[i];
4302 if (shared_dpll[i].crtc_mask == 0) {
4303 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4304 crtc->base.base.id, pll->name);
4305 goto found;
4306 }
4307 }
4308
4309 return NULL;
4310
4311 found:
4312 if (shared_dpll[i].crtc_mask == 0)
4313 shared_dpll[i].hw_state =
4314 crtc_state->dpll_hw_state;
4315
4316 crtc_state->shared_dpll = i;
4317 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4318 pipe_name(crtc->pipe));
4319
4320 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4321
4322 return pll;
4323 }
4324
4325 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4326 {
4327 struct drm_i915_private *dev_priv = to_i915(state->dev);
4328 struct intel_shared_dpll_config *shared_dpll;
4329 struct intel_shared_dpll *pll;
4330 enum intel_dpll_id i;
4331
4332 if (!to_intel_atomic_state(state)->dpll_set)
4333 return;
4334
4335 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4336 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4337 pll = &dev_priv->shared_dplls[i];
4338 pll->config = shared_dpll[i];
4339 }
4340 }
4341
4342 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4343 {
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 int dslreg = PIPEDSL(pipe);
4346 u32 temp;
4347
4348 temp = I915_READ(dslreg);
4349 udelay(500);
4350 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4351 if (wait_for(I915_READ(dslreg) != temp, 5))
4352 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4353 }
4354 }
4355
4356 static int
4357 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4358 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4359 int src_w, int src_h, int dst_w, int dst_h)
4360 {
4361 struct intel_crtc_scaler_state *scaler_state =
4362 &crtc_state->scaler_state;
4363 struct intel_crtc *intel_crtc =
4364 to_intel_crtc(crtc_state->base.crtc);
4365 int need_scaling;
4366
4367 need_scaling = intel_rotation_90_or_270(rotation) ?
4368 (src_h != dst_w || src_w != dst_h):
4369 (src_w != dst_w || src_h != dst_h);
4370
4371 /*
4372 * if plane is being disabled or scaler is no more required or force detach
4373 * - free scaler binded to this plane/crtc
4374 * - in order to do this, update crtc->scaler_usage
4375 *
4376 * Here scaler state in crtc_state is set free so that
4377 * scaler can be assigned to other user. Actual register
4378 * update to free the scaler is done in plane/panel-fit programming.
4379 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4380 */
4381 if (force_detach || !need_scaling) {
4382 if (*scaler_id >= 0) {
4383 scaler_state->scaler_users &= ~(1 << scaler_user);
4384 scaler_state->scalers[*scaler_id].in_use = 0;
4385
4386 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4387 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4388 intel_crtc->pipe, scaler_user, *scaler_id,
4389 scaler_state->scaler_users);
4390 *scaler_id = -1;
4391 }
4392 return 0;
4393 }
4394
4395 /* range checks */
4396 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4397 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4398
4399 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4400 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4401 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4402 "size is out of scaler range\n",
4403 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4404 return -EINVAL;
4405 }
4406
4407 /* mark this plane as a scaler user in crtc_state */
4408 scaler_state->scaler_users |= (1 << scaler_user);
4409 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4410 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4411 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4412 scaler_state->scaler_users);
4413
4414 return 0;
4415 }
4416
4417 /**
4418 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4419 *
4420 * @state: crtc's scaler state
4421 *
4422 * Return
4423 * 0 - scaler_usage updated successfully
4424 * error - requested scaling cannot be supported or other error condition
4425 */
4426 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4427 {
4428 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4429 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4430
4431 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4432 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4433
4434 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4435 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4436 state->pipe_src_w, state->pipe_src_h,
4437 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4438 }
4439
4440 /**
4441 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4442 *
4443 * @state: crtc's scaler state
4444 * @plane_state: atomic plane state to update
4445 *
4446 * Return
4447 * 0 - scaler_usage updated successfully
4448 * error - requested scaling cannot be supported or other error condition
4449 */
4450 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4451 struct intel_plane_state *plane_state)
4452 {
4453
4454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4455 struct intel_plane *intel_plane =
4456 to_intel_plane(plane_state->base.plane);
4457 struct drm_framebuffer *fb = plane_state->base.fb;
4458 int ret;
4459
4460 bool force_detach = !fb || !plane_state->visible;
4461
4462 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4463 intel_plane->base.base.id, intel_crtc->pipe,
4464 drm_plane_index(&intel_plane->base));
4465
4466 ret = skl_update_scaler(crtc_state, force_detach,
4467 drm_plane_index(&intel_plane->base),
4468 &plane_state->scaler_id,
4469 plane_state->base.rotation,
4470 drm_rect_width(&plane_state->src) >> 16,
4471 drm_rect_height(&plane_state->src) >> 16,
4472 drm_rect_width(&plane_state->dst),
4473 drm_rect_height(&plane_state->dst));
4474
4475 if (ret || plane_state->scaler_id < 0)
4476 return ret;
4477
4478 /* check colorkey */
4479 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4480 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4481 intel_plane->base.base.id);
4482 return -EINVAL;
4483 }
4484
4485 /* Check src format */
4486 switch (fb->pixel_format) {
4487 case DRM_FORMAT_RGB565:
4488 case DRM_FORMAT_XBGR8888:
4489 case DRM_FORMAT_XRGB8888:
4490 case DRM_FORMAT_ABGR8888:
4491 case DRM_FORMAT_ARGB8888:
4492 case DRM_FORMAT_XRGB2101010:
4493 case DRM_FORMAT_XBGR2101010:
4494 case DRM_FORMAT_YUYV:
4495 case DRM_FORMAT_YVYU:
4496 case DRM_FORMAT_UYVY:
4497 case DRM_FORMAT_VYUY:
4498 break;
4499 default:
4500 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4501 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4502 return -EINVAL;
4503 }
4504
4505 return 0;
4506 }
4507
4508 static void skylake_scaler_disable(struct intel_crtc *crtc)
4509 {
4510 int i;
4511
4512 for (i = 0; i < crtc->num_scalers; i++)
4513 skl_detach_scaler(crtc, i);
4514 }
4515
4516 static void skylake_pfit_enable(struct intel_crtc *crtc)
4517 {
4518 struct drm_device *dev = crtc->base.dev;
4519 struct drm_i915_private *dev_priv = dev->dev_private;
4520 int pipe = crtc->pipe;
4521 struct intel_crtc_scaler_state *scaler_state =
4522 &crtc->config->scaler_state;
4523
4524 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4525
4526 if (crtc->config->pch_pfit.enabled) {
4527 int id;
4528
4529 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4530 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4531 return;
4532 }
4533
4534 id = scaler_state->scaler_id;
4535 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4536 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4537 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4538 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4539
4540 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4541 }
4542 }
4543
4544 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4545 {
4546 struct drm_device *dev = crtc->base.dev;
4547 struct drm_i915_private *dev_priv = dev->dev_private;
4548 int pipe = crtc->pipe;
4549
4550 if (crtc->config->pch_pfit.enabled) {
4551 /* Force use of hard-coded filter coefficients
4552 * as some pre-programmed values are broken,
4553 * e.g. x201.
4554 */
4555 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4556 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4557 PF_PIPE_SEL_IVB(pipe));
4558 else
4559 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4560 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4561 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4562 }
4563 }
4564
4565 void hsw_enable_ips(struct intel_crtc *crtc)
4566 {
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569
4570 if (!crtc->config->ips_enabled)
4571 return;
4572
4573 /* We can only enable IPS after we enable a plane and wait for a vblank */
4574 intel_wait_for_vblank(dev, crtc->pipe);
4575
4576 assert_plane_enabled(dev_priv, crtc->plane);
4577 if (IS_BROADWELL(dev)) {
4578 mutex_lock(&dev_priv->rps.hw_lock);
4579 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4580 mutex_unlock(&dev_priv->rps.hw_lock);
4581 /* Quoting Art Runyan: "its not safe to expect any particular
4582 * value in IPS_CTL bit 31 after enabling IPS through the
4583 * mailbox." Moreover, the mailbox may return a bogus state,
4584 * so we need to just enable it and continue on.
4585 */
4586 } else {
4587 I915_WRITE(IPS_CTL, IPS_ENABLE);
4588 /* The bit only becomes 1 in the next vblank, so this wait here
4589 * is essentially intel_wait_for_vblank. If we don't have this
4590 * and don't wait for vblanks until the end of crtc_enable, then
4591 * the HW state readout code will complain that the expected
4592 * IPS_CTL value is not the one we read. */
4593 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4594 DRM_ERROR("Timed out waiting for IPS enable\n");
4595 }
4596 }
4597
4598 void hsw_disable_ips(struct intel_crtc *crtc)
4599 {
4600 struct drm_device *dev = crtc->base.dev;
4601 struct drm_i915_private *dev_priv = dev->dev_private;
4602
4603 if (!crtc->config->ips_enabled)
4604 return;
4605
4606 assert_plane_enabled(dev_priv, crtc->plane);
4607 if (IS_BROADWELL(dev)) {
4608 mutex_lock(&dev_priv->rps.hw_lock);
4609 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4610 mutex_unlock(&dev_priv->rps.hw_lock);
4611 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4612 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4613 DRM_ERROR("Timed out waiting for IPS disable\n");
4614 } else {
4615 I915_WRITE(IPS_CTL, 0);
4616 POSTING_READ(IPS_CTL);
4617 }
4618
4619 /* We need to wait for a vblank before we can disable the plane. */
4620 intel_wait_for_vblank(dev, crtc->pipe);
4621 }
4622
4623 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4624 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4625 {
4626 struct drm_device *dev = crtc->dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 enum pipe pipe = intel_crtc->pipe;
4630 int i;
4631 bool reenable_ips = false;
4632
4633 /* The clocks have to be on to load the palette. */
4634 if (!crtc->state->active)
4635 return;
4636
4637 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4638 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4639 assert_dsi_pll_enabled(dev_priv);
4640 else
4641 assert_pll_enabled(dev_priv, pipe);
4642 }
4643
4644 /* Workaround : Do not read or write the pipe palette/gamma data while
4645 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4646 */
4647 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4648 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4649 GAMMA_MODE_MODE_SPLIT)) {
4650 hsw_disable_ips(intel_crtc);
4651 reenable_ips = true;
4652 }
4653
4654 for (i = 0; i < 256; i++) {
4655 u32 palreg;
4656
4657 if (HAS_GMCH_DISPLAY(dev))
4658 palreg = PALETTE(pipe, i);
4659 else
4660 palreg = LGC_PALETTE(pipe, i);
4661
4662 I915_WRITE(palreg,
4663 (intel_crtc->lut_r[i] << 16) |
4664 (intel_crtc->lut_g[i] << 8) |
4665 intel_crtc->lut_b[i]);
4666 }
4667
4668 if (reenable_ips)
4669 hsw_enable_ips(intel_crtc);
4670 }
4671
4672 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4673 {
4674 if (intel_crtc->overlay) {
4675 struct drm_device *dev = intel_crtc->base.dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677
4678 mutex_lock(&dev->struct_mutex);
4679 dev_priv->mm.interruptible = false;
4680 (void) intel_overlay_switch_off(intel_crtc->overlay);
4681 dev_priv->mm.interruptible = true;
4682 mutex_unlock(&dev->struct_mutex);
4683 }
4684
4685 /* Let userspace switch the overlay on again. In most cases userspace
4686 * has to recompute where to put it anyway.
4687 */
4688 }
4689
4690 /**
4691 * intel_post_enable_primary - Perform operations after enabling primary plane
4692 * @crtc: the CRTC whose primary plane was just enabled
4693 *
4694 * Performs potentially sleeping operations that must be done after the primary
4695 * plane is enabled, such as updating FBC and IPS. Note that this may be
4696 * called due to an explicit primary plane update, or due to an implicit
4697 * re-enable that is caused when a sprite plane is updated to no longer
4698 * completely hide the primary plane.
4699 */
4700 static void
4701 intel_post_enable_primary(struct drm_crtc *crtc)
4702 {
4703 struct drm_device *dev = crtc->dev;
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4706 int pipe = intel_crtc->pipe;
4707
4708 /*
4709 * BDW signals flip done immediately if the plane
4710 * is disabled, even if the plane enable is already
4711 * armed to occur at the next vblank :(
4712 */
4713 if (IS_BROADWELL(dev))
4714 intel_wait_for_vblank(dev, pipe);
4715
4716 /*
4717 * FIXME IPS should be fine as long as one plane is
4718 * enabled, but in practice it seems to have problems
4719 * when going from primary only to sprite only and vice
4720 * versa.
4721 */
4722 hsw_enable_ips(intel_crtc);
4723
4724 /*
4725 * Gen2 reports pipe underruns whenever all planes are disabled.
4726 * So don't enable underrun reporting before at least some planes
4727 * are enabled.
4728 * FIXME: Need to fix the logic to work when we turn off all planes
4729 * but leave the pipe running.
4730 */
4731 if (IS_GEN2(dev))
4732 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4733
4734 /* Underruns don't raise interrupts, so check manually. */
4735 if (HAS_GMCH_DISPLAY(dev))
4736 i9xx_check_fifo_underruns(dev_priv);
4737 }
4738
4739 /**
4740 * intel_pre_disable_primary - Perform operations before disabling primary plane
4741 * @crtc: the CRTC whose primary plane is to be disabled
4742 *
4743 * Performs potentially sleeping operations that must be done before the
4744 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4745 * be called due to an explicit primary plane update, or due to an implicit
4746 * disable that is caused when a sprite plane completely hides the primary
4747 * plane.
4748 */
4749 static void
4750 intel_pre_disable_primary(struct drm_crtc *crtc)
4751 {
4752 struct drm_device *dev = crtc->dev;
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4755 int pipe = intel_crtc->pipe;
4756
4757 /*
4758 * Gen2 reports pipe underruns whenever all planes are disabled.
4759 * So diasble underrun reporting before all the planes get disabled.
4760 * FIXME: Need to fix the logic to work when we turn off all planes
4761 * but leave the pipe running.
4762 */
4763 if (IS_GEN2(dev))
4764 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4765
4766 /*
4767 * Vblank time updates from the shadow to live plane control register
4768 * are blocked if the memory self-refresh mode is active at that
4769 * moment. So to make sure the plane gets truly disabled, disable
4770 * first the self-refresh mode. The self-refresh enable bit in turn
4771 * will be checked/applied by the HW only at the next frame start
4772 * event which is after the vblank start event, so we need to have a
4773 * wait-for-vblank between disabling the plane and the pipe.
4774 */
4775 if (HAS_GMCH_DISPLAY(dev)) {
4776 intel_set_memory_cxsr(dev_priv, false);
4777 dev_priv->wm.vlv.cxsr = false;
4778 intel_wait_for_vblank(dev, pipe);
4779 }
4780
4781 /*
4782 * FIXME IPS should be fine as long as one plane is
4783 * enabled, but in practice it seems to have problems
4784 * when going from primary only to sprite only and vice
4785 * versa.
4786 */
4787 hsw_disable_ips(intel_crtc);
4788 }
4789
4790 static void intel_post_plane_update(struct intel_crtc *crtc)
4791 {
4792 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4793 struct drm_device *dev = crtc->base.dev;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795 struct drm_plane *plane;
4796
4797 if (atomic->wait_vblank)
4798 intel_wait_for_vblank(dev, crtc->pipe);
4799
4800 intel_frontbuffer_flip(dev, atomic->fb_bits);
4801
4802 if (atomic->disable_cxsr)
4803 crtc->wm.cxsr_allowed = true;
4804
4805 if (crtc->atomic.update_wm_post)
4806 intel_update_watermarks(&crtc->base);
4807
4808 if (atomic->update_fbc)
4809 intel_fbc_update(dev_priv);
4810
4811 if (atomic->post_enable_primary)
4812 intel_post_enable_primary(&crtc->base);
4813
4814 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4815 intel_update_sprite_watermarks(plane, &crtc->base,
4816 0, 0, 0, false, false);
4817
4818 memset(atomic, 0, sizeof(*atomic));
4819 }
4820
4821 static void intel_pre_plane_update(struct intel_crtc *crtc)
4822 {
4823 struct drm_device *dev = crtc->base.dev;
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4826 struct drm_plane *p;
4827
4828 /* Track fb's for any planes being disabled */
4829 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4830 struct intel_plane *plane = to_intel_plane(p);
4831
4832 mutex_lock(&dev->struct_mutex);
4833 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4834 plane->frontbuffer_bit);
4835 mutex_unlock(&dev->struct_mutex);
4836 }
4837
4838 if (atomic->wait_for_flips)
4839 intel_crtc_wait_for_pending_flips(&crtc->base);
4840
4841 if (atomic->disable_fbc)
4842 intel_fbc_disable_crtc(crtc);
4843
4844 if (crtc->atomic.disable_ips)
4845 hsw_disable_ips(crtc);
4846
4847 if (atomic->pre_disable_primary)
4848 intel_pre_disable_primary(&crtc->base);
4849
4850 if (atomic->disable_cxsr) {
4851 crtc->wm.cxsr_allowed = false;
4852 intel_set_memory_cxsr(dev_priv, false);
4853 }
4854 }
4855
4856 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4857 {
4858 struct drm_device *dev = crtc->dev;
4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860 struct drm_plane *p;
4861 int pipe = intel_crtc->pipe;
4862
4863 intel_crtc_dpms_overlay_disable(intel_crtc);
4864
4865 drm_for_each_plane_mask(p, dev, plane_mask)
4866 to_intel_plane(p)->disable_plane(p, crtc);
4867
4868 /*
4869 * FIXME: Once we grow proper nuclear flip support out of this we need
4870 * to compute the mask of flip planes precisely. For the time being
4871 * consider this a flip to a NULL plane.
4872 */
4873 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4874 }
4875
4876 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4877 {
4878 struct drm_device *dev = crtc->dev;
4879 struct drm_i915_private *dev_priv = dev->dev_private;
4880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4881 struct intel_encoder *encoder;
4882 int pipe = intel_crtc->pipe;
4883
4884 if (WARN_ON(intel_crtc->active))
4885 return;
4886
4887 if (intel_crtc->config->has_pch_encoder)
4888 intel_prepare_shared_dpll(intel_crtc);
4889
4890 if (intel_crtc->config->has_dp_encoder)
4891 intel_dp_set_m_n(intel_crtc, M1_N1);
4892
4893 intel_set_pipe_timings(intel_crtc);
4894
4895 if (intel_crtc->config->has_pch_encoder) {
4896 intel_cpu_transcoder_set_m_n(intel_crtc,
4897 &intel_crtc->config->fdi_m_n, NULL);
4898 }
4899
4900 ironlake_set_pipeconf(crtc);
4901
4902 intel_crtc->active = true;
4903
4904 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4905 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4906
4907 for_each_encoder_on_crtc(dev, crtc, encoder)
4908 if (encoder->pre_enable)
4909 encoder->pre_enable(encoder);
4910
4911 if (intel_crtc->config->has_pch_encoder) {
4912 /* Note: FDI PLL enabling _must_ be done before we enable the
4913 * cpu pipes, hence this is separate from all the other fdi/pch
4914 * enabling. */
4915 ironlake_fdi_pll_enable(intel_crtc);
4916 } else {
4917 assert_fdi_tx_disabled(dev_priv, pipe);
4918 assert_fdi_rx_disabled(dev_priv, pipe);
4919 }
4920
4921 ironlake_pfit_enable(intel_crtc);
4922
4923 /*
4924 * On ILK+ LUT must be loaded before the pipe is running but with
4925 * clocks enabled
4926 */
4927 intel_crtc_load_lut(crtc);
4928
4929 intel_update_watermarks(crtc);
4930 intel_enable_pipe(intel_crtc);
4931
4932 if (intel_crtc->config->has_pch_encoder)
4933 ironlake_pch_enable(crtc);
4934
4935 assert_vblank_disabled(crtc);
4936 drm_crtc_vblank_on(crtc);
4937
4938 for_each_encoder_on_crtc(dev, crtc, encoder)
4939 encoder->enable(encoder);
4940
4941 if (HAS_PCH_CPT(dev))
4942 cpt_verify_modeset(dev, intel_crtc->pipe);
4943 }
4944
4945 /* IPS only exists on ULT machines and is tied to pipe A. */
4946 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4947 {
4948 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4949 }
4950
4951 static void haswell_crtc_enable(struct drm_crtc *crtc)
4952 {
4953 struct drm_device *dev = crtc->dev;
4954 struct drm_i915_private *dev_priv = dev->dev_private;
4955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4956 struct intel_encoder *encoder;
4957 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4958 struct intel_crtc_state *pipe_config =
4959 to_intel_crtc_state(crtc->state);
4960 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4961
4962 if (WARN_ON(intel_crtc->active))
4963 return;
4964
4965 if (intel_crtc_to_shared_dpll(intel_crtc))
4966 intel_enable_shared_dpll(intel_crtc);
4967
4968 if (intel_crtc->config->has_dp_encoder)
4969 intel_dp_set_m_n(intel_crtc, M1_N1);
4970
4971 intel_set_pipe_timings(intel_crtc);
4972
4973 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4974 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4975 intel_crtc->config->pixel_multiplier - 1);
4976 }
4977
4978 if (intel_crtc->config->has_pch_encoder) {
4979 intel_cpu_transcoder_set_m_n(intel_crtc,
4980 &intel_crtc->config->fdi_m_n, NULL);
4981 }
4982
4983 haswell_set_pipeconf(crtc);
4984
4985 intel_set_pipe_csc(crtc);
4986
4987 intel_crtc->active = true;
4988
4989 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4990 for_each_encoder_on_crtc(dev, crtc, encoder) {
4991 if (encoder->pre_pll_enable)
4992 encoder->pre_pll_enable(encoder);
4993 if (encoder->pre_enable)
4994 encoder->pre_enable(encoder);
4995 }
4996
4997 if (intel_crtc->config->has_pch_encoder) {
4998 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4999 true);
5000 dev_priv->display.fdi_link_train(crtc);
5001 }
5002
5003 if (!is_dsi)
5004 intel_ddi_enable_pipe_clock(intel_crtc);
5005
5006 if (INTEL_INFO(dev)->gen >= 9)
5007 skylake_pfit_enable(intel_crtc);
5008 else
5009 ironlake_pfit_enable(intel_crtc);
5010
5011 /*
5012 * On ILK+ LUT must be loaded before the pipe is running but with
5013 * clocks enabled
5014 */
5015 intel_crtc_load_lut(crtc);
5016
5017 intel_ddi_set_pipe_settings(crtc);
5018 if (!is_dsi)
5019 intel_ddi_enable_transcoder_func(crtc);
5020
5021 intel_update_watermarks(crtc);
5022 intel_enable_pipe(intel_crtc);
5023
5024 if (intel_crtc->config->has_pch_encoder)
5025 lpt_pch_enable(crtc);
5026
5027 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5028 intel_ddi_set_vc_payload_alloc(crtc, true);
5029
5030 assert_vblank_disabled(crtc);
5031 drm_crtc_vblank_on(crtc);
5032
5033 for_each_encoder_on_crtc(dev, crtc, encoder) {
5034 encoder->enable(encoder);
5035 intel_opregion_notify_encoder(encoder, true);
5036 }
5037
5038 /* If we change the relative order between pipe/planes enabling, we need
5039 * to change the workaround. */
5040 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5041 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5042 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5043 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5044 }
5045 }
5046
5047 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5048 {
5049 struct drm_device *dev = crtc->base.dev;
5050 struct drm_i915_private *dev_priv = dev->dev_private;
5051 int pipe = crtc->pipe;
5052
5053 /* To avoid upsetting the power well on haswell only disable the pfit if
5054 * it's in use. The hw state code will make sure we get this right. */
5055 if (force || crtc->config->pch_pfit.enabled) {
5056 I915_WRITE(PF_CTL(pipe), 0);
5057 I915_WRITE(PF_WIN_POS(pipe), 0);
5058 I915_WRITE(PF_WIN_SZ(pipe), 0);
5059 }
5060 }
5061
5062 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5063 {
5064 struct drm_device *dev = crtc->dev;
5065 struct drm_i915_private *dev_priv = dev->dev_private;
5066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5067 struct intel_encoder *encoder;
5068 int pipe = intel_crtc->pipe;
5069 u32 reg, temp;
5070
5071 for_each_encoder_on_crtc(dev, crtc, encoder)
5072 encoder->disable(encoder);
5073
5074 drm_crtc_vblank_off(crtc);
5075 assert_vblank_disabled(crtc);
5076
5077 if (intel_crtc->config->has_pch_encoder)
5078 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5079
5080 intel_disable_pipe(intel_crtc);
5081
5082 ironlake_pfit_disable(intel_crtc, false);
5083
5084 if (intel_crtc->config->has_pch_encoder)
5085 ironlake_fdi_disable(crtc);
5086
5087 for_each_encoder_on_crtc(dev, crtc, encoder)
5088 if (encoder->post_disable)
5089 encoder->post_disable(encoder);
5090
5091 if (intel_crtc->config->has_pch_encoder) {
5092 ironlake_disable_pch_transcoder(dev_priv, pipe);
5093
5094 if (HAS_PCH_CPT(dev)) {
5095 /* disable TRANS_DP_CTL */
5096 reg = TRANS_DP_CTL(pipe);
5097 temp = I915_READ(reg);
5098 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5099 TRANS_DP_PORT_SEL_MASK);
5100 temp |= TRANS_DP_PORT_SEL_NONE;
5101 I915_WRITE(reg, temp);
5102
5103 /* disable DPLL_SEL */
5104 temp = I915_READ(PCH_DPLL_SEL);
5105 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5106 I915_WRITE(PCH_DPLL_SEL, temp);
5107 }
5108
5109 ironlake_fdi_pll_disable(intel_crtc);
5110 }
5111 }
5112
5113 static void haswell_crtc_disable(struct drm_crtc *crtc)
5114 {
5115 struct drm_device *dev = crtc->dev;
5116 struct drm_i915_private *dev_priv = dev->dev_private;
5117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5118 struct intel_encoder *encoder;
5119 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5120 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5121
5122 for_each_encoder_on_crtc(dev, crtc, encoder) {
5123 intel_opregion_notify_encoder(encoder, false);
5124 encoder->disable(encoder);
5125 }
5126
5127 drm_crtc_vblank_off(crtc);
5128 assert_vblank_disabled(crtc);
5129
5130 if (intel_crtc->config->has_pch_encoder)
5131 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5132 false);
5133 intel_disable_pipe(intel_crtc);
5134
5135 if (intel_crtc->config->dp_encoder_is_mst)
5136 intel_ddi_set_vc_payload_alloc(crtc, false);
5137
5138 if (!is_dsi)
5139 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5140
5141 if (INTEL_INFO(dev)->gen >= 9)
5142 skylake_scaler_disable(intel_crtc);
5143 else
5144 ironlake_pfit_disable(intel_crtc, false);
5145
5146 if (!is_dsi)
5147 intel_ddi_disable_pipe_clock(intel_crtc);
5148
5149 if (intel_crtc->config->has_pch_encoder) {
5150 lpt_disable_pch_transcoder(dev_priv);
5151 intel_ddi_fdi_disable(crtc);
5152 }
5153
5154 for_each_encoder_on_crtc(dev, crtc, encoder)
5155 if (encoder->post_disable)
5156 encoder->post_disable(encoder);
5157 }
5158
5159 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5160 {
5161 struct drm_device *dev = crtc->base.dev;
5162 struct drm_i915_private *dev_priv = dev->dev_private;
5163 struct intel_crtc_state *pipe_config = crtc->config;
5164
5165 if (!pipe_config->gmch_pfit.control)
5166 return;
5167
5168 /*
5169 * The panel fitter should only be adjusted whilst the pipe is disabled,
5170 * according to register description and PRM.
5171 */
5172 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5173 assert_pipe_disabled(dev_priv, crtc->pipe);
5174
5175 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5176 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5177
5178 /* Border color in case we don't scale up to the full screen. Black by
5179 * default, change to something else for debugging. */
5180 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5181 }
5182
5183 static enum intel_display_power_domain port_to_power_domain(enum port port)
5184 {
5185 switch (port) {
5186 case PORT_A:
5187 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5188 case PORT_B:
5189 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5190 case PORT_C:
5191 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5192 case PORT_D:
5193 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5194 case PORT_E:
5195 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5196 default:
5197 MISSING_CASE(port);
5198 return POWER_DOMAIN_PORT_OTHER;
5199 }
5200 }
5201
5202 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5203 {
5204 switch (port) {
5205 case PORT_A:
5206 return POWER_DOMAIN_AUX_A;
5207 case PORT_B:
5208 return POWER_DOMAIN_AUX_B;
5209 case PORT_C:
5210 return POWER_DOMAIN_AUX_C;
5211 case PORT_D:
5212 return POWER_DOMAIN_AUX_D;
5213 case PORT_E:
5214 /* FIXME: Check VBT for actual wiring of PORT E */
5215 return POWER_DOMAIN_AUX_D;
5216 default:
5217 MISSING_CASE(port);
5218 return POWER_DOMAIN_AUX_A;
5219 }
5220 }
5221
5222 #define for_each_power_domain(domain, mask) \
5223 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5224 if ((1 << (domain)) & (mask))
5225
5226 enum intel_display_power_domain
5227 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5228 {
5229 struct drm_device *dev = intel_encoder->base.dev;
5230 struct intel_digital_port *intel_dig_port;
5231
5232 switch (intel_encoder->type) {
5233 case INTEL_OUTPUT_UNKNOWN:
5234 /* Only DDI platforms should ever use this output type */
5235 WARN_ON_ONCE(!HAS_DDI(dev));
5236 case INTEL_OUTPUT_DISPLAYPORT:
5237 case INTEL_OUTPUT_HDMI:
5238 case INTEL_OUTPUT_EDP:
5239 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5240 return port_to_power_domain(intel_dig_port->port);
5241 case INTEL_OUTPUT_DP_MST:
5242 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5243 return port_to_power_domain(intel_dig_port->port);
5244 case INTEL_OUTPUT_ANALOG:
5245 return POWER_DOMAIN_PORT_CRT;
5246 case INTEL_OUTPUT_DSI:
5247 return POWER_DOMAIN_PORT_DSI;
5248 default:
5249 return POWER_DOMAIN_PORT_OTHER;
5250 }
5251 }
5252
5253 enum intel_display_power_domain
5254 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5255 {
5256 struct drm_device *dev = intel_encoder->base.dev;
5257 struct intel_digital_port *intel_dig_port;
5258
5259 switch (intel_encoder->type) {
5260 case INTEL_OUTPUT_UNKNOWN:
5261 case INTEL_OUTPUT_HDMI:
5262 /*
5263 * Only DDI platforms should ever use these output types.
5264 * We can get here after the HDMI detect code has already set
5265 * the type of the shared encoder. Since we can't be sure
5266 * what's the status of the given connectors, play safe and
5267 * run the DP detection too.
5268 */
5269 WARN_ON_ONCE(!HAS_DDI(dev));
5270 case INTEL_OUTPUT_DISPLAYPORT:
5271 case INTEL_OUTPUT_EDP:
5272 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5273 return port_to_aux_power_domain(intel_dig_port->port);
5274 case INTEL_OUTPUT_DP_MST:
5275 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5276 return port_to_aux_power_domain(intel_dig_port->port);
5277 default:
5278 MISSING_CASE(intel_encoder->type);
5279 return POWER_DOMAIN_AUX_A;
5280 }
5281 }
5282
5283 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5284 {
5285 struct drm_device *dev = crtc->dev;
5286 struct intel_encoder *intel_encoder;
5287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5288 enum pipe pipe = intel_crtc->pipe;
5289 unsigned long mask;
5290 enum transcoder transcoder;
5291
5292 if (!crtc->state->active)
5293 return 0;
5294
5295 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5296
5297 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5298 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5299 if (intel_crtc->config->pch_pfit.enabled ||
5300 intel_crtc->config->pch_pfit.force_thru)
5301 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5302
5303 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5304 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5305
5306 return mask;
5307 }
5308
5309 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5310 {
5311 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5313 enum intel_display_power_domain domain;
5314 unsigned long domains, new_domains, old_domains;
5315
5316 old_domains = intel_crtc->enabled_power_domains;
5317 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5318
5319 domains = new_domains & ~old_domains;
5320
5321 for_each_power_domain(domain, domains)
5322 intel_display_power_get(dev_priv, domain);
5323
5324 return old_domains & ~new_domains;
5325 }
5326
5327 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5328 unsigned long domains)
5329 {
5330 enum intel_display_power_domain domain;
5331
5332 for_each_power_domain(domain, domains)
5333 intel_display_power_put(dev_priv, domain);
5334 }
5335
5336 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5337 {
5338 struct drm_device *dev = state->dev;
5339 struct drm_i915_private *dev_priv = dev->dev_private;
5340 unsigned long put_domains[I915_MAX_PIPES] = {};
5341 struct drm_crtc_state *crtc_state;
5342 struct drm_crtc *crtc;
5343 int i;
5344
5345 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5346 if (needs_modeset(crtc->state))
5347 put_domains[to_intel_crtc(crtc)->pipe] =
5348 modeset_get_crtc_power_domains(crtc);
5349 }
5350
5351 if (dev_priv->display.modeset_commit_cdclk) {
5352 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5353
5354 if (cdclk != dev_priv->cdclk_freq &&
5355 !WARN_ON(!state->allow_modeset))
5356 dev_priv->display.modeset_commit_cdclk(state);
5357 }
5358
5359 for (i = 0; i < I915_MAX_PIPES; i++)
5360 if (put_domains[i])
5361 modeset_put_power_domains(dev_priv, put_domains[i]);
5362 }
5363
5364 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5365 {
5366 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5367
5368 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5369 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5370 return max_cdclk_freq;
5371 else if (IS_CHERRYVIEW(dev_priv))
5372 return max_cdclk_freq*95/100;
5373 else if (INTEL_INFO(dev_priv)->gen < 4)
5374 return 2*max_cdclk_freq*90/100;
5375 else
5376 return max_cdclk_freq*90/100;
5377 }
5378
5379 static void intel_update_max_cdclk(struct drm_device *dev)
5380 {
5381 struct drm_i915_private *dev_priv = dev->dev_private;
5382
5383 if (IS_SKYLAKE(dev)) {
5384 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5385
5386 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5387 dev_priv->max_cdclk_freq = 675000;
5388 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5389 dev_priv->max_cdclk_freq = 540000;
5390 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5391 dev_priv->max_cdclk_freq = 450000;
5392 else
5393 dev_priv->max_cdclk_freq = 337500;
5394 } else if (IS_BROADWELL(dev)) {
5395 /*
5396 * FIXME with extra cooling we can allow
5397 * 540 MHz for ULX and 675 Mhz for ULT.
5398 * How can we know if extra cooling is
5399 * available? PCI ID, VTB, something else?
5400 */
5401 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5402 dev_priv->max_cdclk_freq = 450000;
5403 else if (IS_BDW_ULX(dev))
5404 dev_priv->max_cdclk_freq = 450000;
5405 else if (IS_BDW_ULT(dev))
5406 dev_priv->max_cdclk_freq = 540000;
5407 else
5408 dev_priv->max_cdclk_freq = 675000;
5409 } else if (IS_CHERRYVIEW(dev)) {
5410 dev_priv->max_cdclk_freq = 320000;
5411 } else if (IS_VALLEYVIEW(dev)) {
5412 dev_priv->max_cdclk_freq = 400000;
5413 } else {
5414 /* otherwise assume cdclk is fixed */
5415 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5416 }
5417
5418 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5419
5420 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5421 dev_priv->max_cdclk_freq);
5422
5423 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5424 dev_priv->max_dotclk_freq);
5425 }
5426
5427 static void intel_update_cdclk(struct drm_device *dev)
5428 {
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5430
5431 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5432 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5433 dev_priv->cdclk_freq);
5434
5435 /*
5436 * Program the gmbus_freq based on the cdclk frequency.
5437 * BSpec erroneously claims we should aim for 4MHz, but
5438 * in fact 1MHz is the correct frequency.
5439 */
5440 if (IS_VALLEYVIEW(dev)) {
5441 /*
5442 * Program the gmbus_freq based on the cdclk frequency.
5443 * BSpec erroneously claims we should aim for 4MHz, but
5444 * in fact 1MHz is the correct frequency.
5445 */
5446 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5447 }
5448
5449 if (dev_priv->max_cdclk_freq == 0)
5450 intel_update_max_cdclk(dev);
5451 }
5452
5453 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5454 {
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456 uint32_t divider;
5457 uint32_t ratio;
5458 uint32_t current_freq;
5459 int ret;
5460
5461 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5462 switch (frequency) {
5463 case 144000:
5464 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5465 ratio = BXT_DE_PLL_RATIO(60);
5466 break;
5467 case 288000:
5468 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5469 ratio = BXT_DE_PLL_RATIO(60);
5470 break;
5471 case 384000:
5472 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5473 ratio = BXT_DE_PLL_RATIO(60);
5474 break;
5475 case 576000:
5476 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5477 ratio = BXT_DE_PLL_RATIO(60);
5478 break;
5479 case 624000:
5480 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5481 ratio = BXT_DE_PLL_RATIO(65);
5482 break;
5483 case 19200:
5484 /*
5485 * Bypass frequency with DE PLL disabled. Init ratio, divider
5486 * to suppress GCC warning.
5487 */
5488 ratio = 0;
5489 divider = 0;
5490 break;
5491 default:
5492 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5493
5494 return;
5495 }
5496
5497 mutex_lock(&dev_priv->rps.hw_lock);
5498 /* Inform power controller of upcoming frequency change */
5499 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5500 0x80000000);
5501 mutex_unlock(&dev_priv->rps.hw_lock);
5502
5503 if (ret) {
5504 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5505 ret, frequency);
5506 return;
5507 }
5508
5509 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5510 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5511 current_freq = current_freq * 500 + 1000;
5512
5513 /*
5514 * DE PLL has to be disabled when
5515 * - setting to 19.2MHz (bypass, PLL isn't used)
5516 * - before setting to 624MHz (PLL needs toggling)
5517 * - before setting to any frequency from 624MHz (PLL needs toggling)
5518 */
5519 if (frequency == 19200 || frequency == 624000 ||
5520 current_freq == 624000) {
5521 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5522 /* Timeout 200us */
5523 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5524 1))
5525 DRM_ERROR("timout waiting for DE PLL unlock\n");
5526 }
5527
5528 if (frequency != 19200) {
5529 uint32_t val;
5530
5531 val = I915_READ(BXT_DE_PLL_CTL);
5532 val &= ~BXT_DE_PLL_RATIO_MASK;
5533 val |= ratio;
5534 I915_WRITE(BXT_DE_PLL_CTL, val);
5535
5536 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5537 /* Timeout 200us */
5538 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5539 DRM_ERROR("timeout waiting for DE PLL lock\n");
5540
5541 val = I915_READ(CDCLK_CTL);
5542 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5543 val |= divider;
5544 /*
5545 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5546 * enable otherwise.
5547 */
5548 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5549 if (frequency >= 500000)
5550 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5551
5552 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5553 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5554 val |= (frequency - 1000) / 500;
5555 I915_WRITE(CDCLK_CTL, val);
5556 }
5557
5558 mutex_lock(&dev_priv->rps.hw_lock);
5559 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5560 DIV_ROUND_UP(frequency, 25000));
5561 mutex_unlock(&dev_priv->rps.hw_lock);
5562
5563 if (ret) {
5564 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5565 ret, frequency);
5566 return;
5567 }
5568
5569 intel_update_cdclk(dev);
5570 }
5571
5572 void broxton_init_cdclk(struct drm_device *dev)
5573 {
5574 struct drm_i915_private *dev_priv = dev->dev_private;
5575 uint32_t val;
5576
5577 /*
5578 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5579 * or else the reset will hang because there is no PCH to respond.
5580 * Move the handshake programming to initialization sequence.
5581 * Previously was left up to BIOS.
5582 */
5583 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5584 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5585 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5586
5587 /* Enable PG1 for cdclk */
5588 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5589
5590 /* check if cd clock is enabled */
5591 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5592 DRM_DEBUG_KMS("Display already initialized\n");
5593 return;
5594 }
5595
5596 /*
5597 * FIXME:
5598 * - The initial CDCLK needs to be read from VBT.
5599 * Need to make this change after VBT has changes for BXT.
5600 * - check if setting the max (or any) cdclk freq is really necessary
5601 * here, it belongs to modeset time
5602 */
5603 broxton_set_cdclk(dev, 624000);
5604
5605 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5606 POSTING_READ(DBUF_CTL);
5607
5608 udelay(10);
5609
5610 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5611 DRM_ERROR("DBuf power enable timeout!\n");
5612 }
5613
5614 void broxton_uninit_cdclk(struct drm_device *dev)
5615 {
5616 struct drm_i915_private *dev_priv = dev->dev_private;
5617
5618 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5619 POSTING_READ(DBUF_CTL);
5620
5621 udelay(10);
5622
5623 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5624 DRM_ERROR("DBuf power disable timeout!\n");
5625
5626 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5627 broxton_set_cdclk(dev, 19200);
5628
5629 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5630 }
5631
5632 static const struct skl_cdclk_entry {
5633 unsigned int freq;
5634 unsigned int vco;
5635 } skl_cdclk_frequencies[] = {
5636 { .freq = 308570, .vco = 8640 },
5637 { .freq = 337500, .vco = 8100 },
5638 { .freq = 432000, .vco = 8640 },
5639 { .freq = 450000, .vco = 8100 },
5640 { .freq = 540000, .vco = 8100 },
5641 { .freq = 617140, .vco = 8640 },
5642 { .freq = 675000, .vco = 8100 },
5643 };
5644
5645 static unsigned int skl_cdclk_decimal(unsigned int freq)
5646 {
5647 return (freq - 1000) / 500;
5648 }
5649
5650 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5651 {
5652 unsigned int i;
5653
5654 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5655 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5656
5657 if (e->freq == freq)
5658 return e->vco;
5659 }
5660
5661 return 8100;
5662 }
5663
5664 static void
5665 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5666 {
5667 unsigned int min_freq;
5668 u32 val;
5669
5670 /* select the minimum CDCLK before enabling DPLL 0 */
5671 val = I915_READ(CDCLK_CTL);
5672 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5673 val |= CDCLK_FREQ_337_308;
5674
5675 if (required_vco == 8640)
5676 min_freq = 308570;
5677 else
5678 min_freq = 337500;
5679
5680 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5681
5682 I915_WRITE(CDCLK_CTL, val);
5683 POSTING_READ(CDCLK_CTL);
5684
5685 /*
5686 * We always enable DPLL0 with the lowest link rate possible, but still
5687 * taking into account the VCO required to operate the eDP panel at the
5688 * desired frequency. The usual DP link rates operate with a VCO of
5689 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5690 * The modeset code is responsible for the selection of the exact link
5691 * rate later on, with the constraint of choosing a frequency that
5692 * works with required_vco.
5693 */
5694 val = I915_READ(DPLL_CTRL1);
5695
5696 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5697 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5698 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5699 if (required_vco == 8640)
5700 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5701 SKL_DPLL0);
5702 else
5703 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5704 SKL_DPLL0);
5705
5706 I915_WRITE(DPLL_CTRL1, val);
5707 POSTING_READ(DPLL_CTRL1);
5708
5709 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5710
5711 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5712 DRM_ERROR("DPLL0 not locked\n");
5713 }
5714
5715 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5716 {
5717 int ret;
5718 u32 val;
5719
5720 /* inform PCU we want to change CDCLK */
5721 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5722 mutex_lock(&dev_priv->rps.hw_lock);
5723 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5724 mutex_unlock(&dev_priv->rps.hw_lock);
5725
5726 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5727 }
5728
5729 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5730 {
5731 unsigned int i;
5732
5733 for (i = 0; i < 15; i++) {
5734 if (skl_cdclk_pcu_ready(dev_priv))
5735 return true;
5736 udelay(10);
5737 }
5738
5739 return false;
5740 }
5741
5742 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5743 {
5744 struct drm_device *dev = dev_priv->dev;
5745 u32 freq_select, pcu_ack;
5746
5747 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5748
5749 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5750 DRM_ERROR("failed to inform PCU about cdclk change\n");
5751 return;
5752 }
5753
5754 /* set CDCLK_CTL */
5755 switch(freq) {
5756 case 450000:
5757 case 432000:
5758 freq_select = CDCLK_FREQ_450_432;
5759 pcu_ack = 1;
5760 break;
5761 case 540000:
5762 freq_select = CDCLK_FREQ_540;
5763 pcu_ack = 2;
5764 break;
5765 case 308570:
5766 case 337500:
5767 default:
5768 freq_select = CDCLK_FREQ_337_308;
5769 pcu_ack = 0;
5770 break;
5771 case 617140:
5772 case 675000:
5773 freq_select = CDCLK_FREQ_675_617;
5774 pcu_ack = 3;
5775 break;
5776 }
5777
5778 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5779 POSTING_READ(CDCLK_CTL);
5780
5781 /* inform PCU of the change */
5782 mutex_lock(&dev_priv->rps.hw_lock);
5783 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5784 mutex_unlock(&dev_priv->rps.hw_lock);
5785
5786 intel_update_cdclk(dev);
5787 }
5788
5789 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5790 {
5791 /* disable DBUF power */
5792 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5793 POSTING_READ(DBUF_CTL);
5794
5795 udelay(10);
5796
5797 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5798 DRM_ERROR("DBuf power disable timeout\n");
5799
5800 /*
5801 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5802 */
5803 if (dev_priv->csr.dmc_payload) {
5804 /* disable DPLL0 */
5805 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5806 ~LCPLL_PLL_ENABLE);
5807 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5808 DRM_ERROR("Couldn't disable DPLL0\n");
5809 }
5810
5811 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5812 }
5813
5814 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5815 {
5816 u32 val;
5817 unsigned int required_vco;
5818
5819 /* enable PCH reset handshake */
5820 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5821 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5822
5823 /* enable PG1 and Misc I/O */
5824 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5825
5826 /* DPLL0 not enabled (happens on early BIOS versions) */
5827 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5828 /* enable DPLL0 */
5829 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5830 skl_dpll0_enable(dev_priv, required_vco);
5831 }
5832
5833 /* set CDCLK to the frequency the BIOS chose */
5834 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5835
5836 /* enable DBUF power */
5837 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5838 POSTING_READ(DBUF_CTL);
5839
5840 udelay(10);
5841
5842 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5843 DRM_ERROR("DBuf power enable timeout\n");
5844 }
5845
5846 /* Adjust CDclk dividers to allow high res or save power if possible */
5847 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5848 {
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850 u32 val, cmd;
5851
5852 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5853 != dev_priv->cdclk_freq);
5854
5855 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5856 cmd = 2;
5857 else if (cdclk == 266667)
5858 cmd = 1;
5859 else
5860 cmd = 0;
5861
5862 mutex_lock(&dev_priv->rps.hw_lock);
5863 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5864 val &= ~DSPFREQGUAR_MASK;
5865 val |= (cmd << DSPFREQGUAR_SHIFT);
5866 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5867 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5868 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5869 50)) {
5870 DRM_ERROR("timed out waiting for CDclk change\n");
5871 }
5872 mutex_unlock(&dev_priv->rps.hw_lock);
5873
5874 mutex_lock(&dev_priv->sb_lock);
5875
5876 if (cdclk == 400000) {
5877 u32 divider;
5878
5879 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5880
5881 /* adjust cdclk divider */
5882 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5883 val &= ~CCK_FREQUENCY_VALUES;
5884 val |= divider;
5885 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5886
5887 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5888 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5889 50))
5890 DRM_ERROR("timed out waiting for CDclk change\n");
5891 }
5892
5893 /* adjust self-refresh exit latency value */
5894 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5895 val &= ~0x7f;
5896
5897 /*
5898 * For high bandwidth configs, we set a higher latency in the bunit
5899 * so that the core display fetch happens in time to avoid underruns.
5900 */
5901 if (cdclk == 400000)
5902 val |= 4500 / 250; /* 4.5 usec */
5903 else
5904 val |= 3000 / 250; /* 3.0 usec */
5905 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5906
5907 mutex_unlock(&dev_priv->sb_lock);
5908
5909 intel_update_cdclk(dev);
5910 }
5911
5912 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5913 {
5914 struct drm_i915_private *dev_priv = dev->dev_private;
5915 u32 val, cmd;
5916
5917 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5918 != dev_priv->cdclk_freq);
5919
5920 switch (cdclk) {
5921 case 333333:
5922 case 320000:
5923 case 266667:
5924 case 200000:
5925 break;
5926 default:
5927 MISSING_CASE(cdclk);
5928 return;
5929 }
5930
5931 /*
5932 * Specs are full of misinformation, but testing on actual
5933 * hardware has shown that we just need to write the desired
5934 * CCK divider into the Punit register.
5935 */
5936 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5937
5938 mutex_lock(&dev_priv->rps.hw_lock);
5939 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5940 val &= ~DSPFREQGUAR_MASK_CHV;
5941 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5942 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5943 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5944 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5945 50)) {
5946 DRM_ERROR("timed out waiting for CDclk change\n");
5947 }
5948 mutex_unlock(&dev_priv->rps.hw_lock);
5949
5950 intel_update_cdclk(dev);
5951 }
5952
5953 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5954 int max_pixclk)
5955 {
5956 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5957 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5958
5959 /*
5960 * Really only a few cases to deal with, as only 4 CDclks are supported:
5961 * 200MHz
5962 * 267MHz
5963 * 320/333MHz (depends on HPLL freq)
5964 * 400MHz (VLV only)
5965 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5966 * of the lower bin and adjust if needed.
5967 *
5968 * We seem to get an unstable or solid color picture at 200MHz.
5969 * Not sure what's wrong. For now use 200MHz only when all pipes
5970 * are off.
5971 */
5972 if (!IS_CHERRYVIEW(dev_priv) &&
5973 max_pixclk > freq_320*limit/100)
5974 return 400000;
5975 else if (max_pixclk > 266667*limit/100)
5976 return freq_320;
5977 else if (max_pixclk > 0)
5978 return 266667;
5979 else
5980 return 200000;
5981 }
5982
5983 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5984 int max_pixclk)
5985 {
5986 /*
5987 * FIXME:
5988 * - remove the guardband, it's not needed on BXT
5989 * - set 19.2MHz bypass frequency if there are no active pipes
5990 */
5991 if (max_pixclk > 576000*9/10)
5992 return 624000;
5993 else if (max_pixclk > 384000*9/10)
5994 return 576000;
5995 else if (max_pixclk > 288000*9/10)
5996 return 384000;
5997 else if (max_pixclk > 144000*9/10)
5998 return 288000;
5999 else
6000 return 144000;
6001 }
6002
6003 /* Compute the max pixel clock for new configuration. Uses atomic state if
6004 * that's non-NULL, look at current state otherwise. */
6005 static int intel_mode_max_pixclk(struct drm_device *dev,
6006 struct drm_atomic_state *state)
6007 {
6008 struct intel_crtc *intel_crtc;
6009 struct intel_crtc_state *crtc_state;
6010 int max_pixclk = 0;
6011
6012 for_each_intel_crtc(dev, intel_crtc) {
6013 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6014 if (IS_ERR(crtc_state))
6015 return PTR_ERR(crtc_state);
6016
6017 if (!crtc_state->base.enable)
6018 continue;
6019
6020 max_pixclk = max(max_pixclk,
6021 crtc_state->base.adjusted_mode.crtc_clock);
6022 }
6023
6024 return max_pixclk;
6025 }
6026
6027 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6028 {
6029 struct drm_device *dev = state->dev;
6030 struct drm_i915_private *dev_priv = dev->dev_private;
6031 int max_pixclk = intel_mode_max_pixclk(dev, state);
6032
6033 if (max_pixclk < 0)
6034 return max_pixclk;
6035
6036 to_intel_atomic_state(state)->cdclk =
6037 valleyview_calc_cdclk(dev_priv, max_pixclk);
6038
6039 return 0;
6040 }
6041
6042 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6043 {
6044 struct drm_device *dev = state->dev;
6045 struct drm_i915_private *dev_priv = dev->dev_private;
6046 int max_pixclk = intel_mode_max_pixclk(dev, state);
6047
6048 if (max_pixclk < 0)
6049 return max_pixclk;
6050
6051 to_intel_atomic_state(state)->cdclk =
6052 broxton_calc_cdclk(dev_priv, max_pixclk);
6053
6054 return 0;
6055 }
6056
6057 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6058 {
6059 unsigned int credits, default_credits;
6060
6061 if (IS_CHERRYVIEW(dev_priv))
6062 default_credits = PFI_CREDIT(12);
6063 else
6064 default_credits = PFI_CREDIT(8);
6065
6066 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6067 /* CHV suggested value is 31 or 63 */
6068 if (IS_CHERRYVIEW(dev_priv))
6069 credits = PFI_CREDIT_63;
6070 else
6071 credits = PFI_CREDIT(15);
6072 } else {
6073 credits = default_credits;
6074 }
6075
6076 /*
6077 * WA - write default credits before re-programming
6078 * FIXME: should we also set the resend bit here?
6079 */
6080 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6081 default_credits);
6082
6083 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6084 credits | PFI_CREDIT_RESEND);
6085
6086 /*
6087 * FIXME is this guaranteed to clear
6088 * immediately or should we poll for it?
6089 */
6090 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6091 }
6092
6093 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6094 {
6095 struct drm_device *dev = old_state->dev;
6096 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098
6099 /*
6100 * FIXME: We can end up here with all power domains off, yet
6101 * with a CDCLK frequency other than the minimum. To account
6102 * for this take the PIPE-A power domain, which covers the HW
6103 * blocks needed for the following programming. This can be
6104 * removed once it's guaranteed that we get here either with
6105 * the minimum CDCLK set, or the required power domains
6106 * enabled.
6107 */
6108 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6109
6110 if (IS_CHERRYVIEW(dev))
6111 cherryview_set_cdclk(dev, req_cdclk);
6112 else
6113 valleyview_set_cdclk(dev, req_cdclk);
6114
6115 vlv_program_pfi_credits(dev_priv);
6116
6117 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6118 }
6119
6120 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6121 {
6122 struct drm_device *dev = crtc->dev;
6123 struct drm_i915_private *dev_priv = to_i915(dev);
6124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6125 struct intel_encoder *encoder;
6126 int pipe = intel_crtc->pipe;
6127 bool is_dsi;
6128
6129 if (WARN_ON(intel_crtc->active))
6130 return;
6131
6132 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6133
6134 if (intel_crtc->config->has_dp_encoder)
6135 intel_dp_set_m_n(intel_crtc, M1_N1);
6136
6137 intel_set_pipe_timings(intel_crtc);
6138
6139 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6140 struct drm_i915_private *dev_priv = dev->dev_private;
6141
6142 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6143 I915_WRITE(CHV_CANVAS(pipe), 0);
6144 }
6145
6146 i9xx_set_pipeconf(intel_crtc);
6147
6148 intel_crtc->active = true;
6149
6150 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6151
6152 for_each_encoder_on_crtc(dev, crtc, encoder)
6153 if (encoder->pre_pll_enable)
6154 encoder->pre_pll_enable(encoder);
6155
6156 if (!is_dsi) {
6157 if (IS_CHERRYVIEW(dev)) {
6158 chv_prepare_pll(intel_crtc, intel_crtc->config);
6159 chv_enable_pll(intel_crtc, intel_crtc->config);
6160 } else {
6161 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6162 vlv_enable_pll(intel_crtc, intel_crtc->config);
6163 }
6164 }
6165
6166 for_each_encoder_on_crtc(dev, crtc, encoder)
6167 if (encoder->pre_enable)
6168 encoder->pre_enable(encoder);
6169
6170 i9xx_pfit_enable(intel_crtc);
6171
6172 intel_crtc_load_lut(crtc);
6173
6174 intel_enable_pipe(intel_crtc);
6175
6176 assert_vblank_disabled(crtc);
6177 drm_crtc_vblank_on(crtc);
6178
6179 for_each_encoder_on_crtc(dev, crtc, encoder)
6180 encoder->enable(encoder);
6181 }
6182
6183 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6184 {
6185 struct drm_device *dev = crtc->base.dev;
6186 struct drm_i915_private *dev_priv = dev->dev_private;
6187
6188 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6189 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6190 }
6191
6192 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6193 {
6194 struct drm_device *dev = crtc->dev;
6195 struct drm_i915_private *dev_priv = to_i915(dev);
6196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6197 struct intel_encoder *encoder;
6198 int pipe = intel_crtc->pipe;
6199
6200 if (WARN_ON(intel_crtc->active))
6201 return;
6202
6203 i9xx_set_pll_dividers(intel_crtc);
6204
6205 if (intel_crtc->config->has_dp_encoder)
6206 intel_dp_set_m_n(intel_crtc, M1_N1);
6207
6208 intel_set_pipe_timings(intel_crtc);
6209
6210 i9xx_set_pipeconf(intel_crtc);
6211
6212 intel_crtc->active = true;
6213
6214 if (!IS_GEN2(dev))
6215 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6216
6217 for_each_encoder_on_crtc(dev, crtc, encoder)
6218 if (encoder->pre_enable)
6219 encoder->pre_enable(encoder);
6220
6221 i9xx_enable_pll(intel_crtc);
6222
6223 i9xx_pfit_enable(intel_crtc);
6224
6225 intel_crtc_load_lut(crtc);
6226
6227 intel_update_watermarks(crtc);
6228 intel_enable_pipe(intel_crtc);
6229
6230 assert_vblank_disabled(crtc);
6231 drm_crtc_vblank_on(crtc);
6232
6233 for_each_encoder_on_crtc(dev, crtc, encoder)
6234 encoder->enable(encoder);
6235 }
6236
6237 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6238 {
6239 struct drm_device *dev = crtc->base.dev;
6240 struct drm_i915_private *dev_priv = dev->dev_private;
6241
6242 if (!crtc->config->gmch_pfit.control)
6243 return;
6244
6245 assert_pipe_disabled(dev_priv, crtc->pipe);
6246
6247 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6248 I915_READ(PFIT_CONTROL));
6249 I915_WRITE(PFIT_CONTROL, 0);
6250 }
6251
6252 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6253 {
6254 struct drm_device *dev = crtc->dev;
6255 struct drm_i915_private *dev_priv = dev->dev_private;
6256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6257 struct intel_encoder *encoder;
6258 int pipe = intel_crtc->pipe;
6259
6260 /*
6261 * On gen2 planes are double buffered but the pipe isn't, so we must
6262 * wait for planes to fully turn off before disabling the pipe.
6263 * We also need to wait on all gmch platforms because of the
6264 * self-refresh mode constraint explained above.
6265 */
6266 intel_wait_for_vblank(dev, pipe);
6267
6268 for_each_encoder_on_crtc(dev, crtc, encoder)
6269 encoder->disable(encoder);
6270
6271 drm_crtc_vblank_off(crtc);
6272 assert_vblank_disabled(crtc);
6273
6274 intel_disable_pipe(intel_crtc);
6275
6276 i9xx_pfit_disable(intel_crtc);
6277
6278 for_each_encoder_on_crtc(dev, crtc, encoder)
6279 if (encoder->post_disable)
6280 encoder->post_disable(encoder);
6281
6282 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6283 if (IS_CHERRYVIEW(dev))
6284 chv_disable_pll(dev_priv, pipe);
6285 else if (IS_VALLEYVIEW(dev))
6286 vlv_disable_pll(dev_priv, pipe);
6287 else
6288 i9xx_disable_pll(intel_crtc);
6289 }
6290
6291 for_each_encoder_on_crtc(dev, crtc, encoder)
6292 if (encoder->post_pll_disable)
6293 encoder->post_pll_disable(encoder);
6294
6295 if (!IS_GEN2(dev))
6296 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6297 }
6298
6299 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6300 {
6301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6302 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6303 enum intel_display_power_domain domain;
6304 unsigned long domains;
6305
6306 if (!intel_crtc->active)
6307 return;
6308
6309 if (to_intel_plane_state(crtc->primary->state)->visible) {
6310 intel_crtc_wait_for_pending_flips(crtc);
6311 intel_pre_disable_primary(crtc);
6312 }
6313
6314 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6315 dev_priv->display.crtc_disable(crtc);
6316 intel_crtc->active = false;
6317 intel_update_watermarks(crtc);
6318 intel_disable_shared_dpll(intel_crtc);
6319
6320 domains = intel_crtc->enabled_power_domains;
6321 for_each_power_domain(domain, domains)
6322 intel_display_power_put(dev_priv, domain);
6323 intel_crtc->enabled_power_domains = 0;
6324 }
6325
6326 /*
6327 * turn all crtc's off, but do not adjust state
6328 * This has to be paired with a call to intel_modeset_setup_hw_state.
6329 */
6330 int intel_display_suspend(struct drm_device *dev)
6331 {
6332 struct drm_mode_config *config = &dev->mode_config;
6333 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6334 struct drm_atomic_state *state;
6335 struct drm_crtc *crtc;
6336 unsigned crtc_mask = 0;
6337 int ret = 0;
6338
6339 if (WARN_ON(!ctx))
6340 return 0;
6341
6342 lockdep_assert_held(&ctx->ww_ctx);
6343 state = drm_atomic_state_alloc(dev);
6344 if (WARN_ON(!state))
6345 return -ENOMEM;
6346
6347 state->acquire_ctx = ctx;
6348 state->allow_modeset = true;
6349
6350 for_each_crtc(dev, crtc) {
6351 struct drm_crtc_state *crtc_state =
6352 drm_atomic_get_crtc_state(state, crtc);
6353
6354 ret = PTR_ERR_OR_ZERO(crtc_state);
6355 if (ret)
6356 goto free;
6357
6358 if (!crtc_state->active)
6359 continue;
6360
6361 crtc_state->active = false;
6362 crtc_mask |= 1 << drm_crtc_index(crtc);
6363 }
6364
6365 if (crtc_mask) {
6366 ret = drm_atomic_commit(state);
6367
6368 if (!ret) {
6369 for_each_crtc(dev, crtc)
6370 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6371 crtc->state->active = true;
6372
6373 return ret;
6374 }
6375 }
6376
6377 free:
6378 if (ret)
6379 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6380 drm_atomic_state_free(state);
6381 return ret;
6382 }
6383
6384 void intel_encoder_destroy(struct drm_encoder *encoder)
6385 {
6386 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6387
6388 drm_encoder_cleanup(encoder);
6389 kfree(intel_encoder);
6390 }
6391
6392 /* Cross check the actual hw state with our own modeset state tracking (and it's
6393 * internal consistency). */
6394 static void intel_connector_check_state(struct intel_connector *connector)
6395 {
6396 struct drm_crtc *crtc = connector->base.state->crtc;
6397
6398 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6399 connector->base.base.id,
6400 connector->base.name);
6401
6402 if (connector->get_hw_state(connector)) {
6403 struct intel_encoder *encoder = connector->encoder;
6404 struct drm_connector_state *conn_state = connector->base.state;
6405
6406 I915_STATE_WARN(!crtc,
6407 "connector enabled without attached crtc\n");
6408
6409 if (!crtc)
6410 return;
6411
6412 I915_STATE_WARN(!crtc->state->active,
6413 "connector is active, but attached crtc isn't\n");
6414
6415 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6416 return;
6417
6418 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6419 "atomic encoder doesn't match attached encoder\n");
6420
6421 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6422 "attached encoder crtc differs from connector crtc\n");
6423 } else {
6424 I915_STATE_WARN(crtc && crtc->state->active,
6425 "attached crtc is active, but connector isn't\n");
6426 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6427 "best encoder set without crtc!\n");
6428 }
6429 }
6430
6431 int intel_connector_init(struct intel_connector *connector)
6432 {
6433 struct drm_connector_state *connector_state;
6434
6435 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6436 if (!connector_state)
6437 return -ENOMEM;
6438
6439 connector->base.state = connector_state;
6440 return 0;
6441 }
6442
6443 struct intel_connector *intel_connector_alloc(void)
6444 {
6445 struct intel_connector *connector;
6446
6447 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6448 if (!connector)
6449 return NULL;
6450
6451 if (intel_connector_init(connector) < 0) {
6452 kfree(connector);
6453 return NULL;
6454 }
6455
6456 return connector;
6457 }
6458
6459 /* Simple connector->get_hw_state implementation for encoders that support only
6460 * one connector and no cloning and hence the encoder state determines the state
6461 * of the connector. */
6462 bool intel_connector_get_hw_state(struct intel_connector *connector)
6463 {
6464 enum pipe pipe = 0;
6465 struct intel_encoder *encoder = connector->encoder;
6466
6467 return encoder->get_hw_state(encoder, &pipe);
6468 }
6469
6470 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6471 {
6472 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6473 return crtc_state->fdi_lanes;
6474
6475 return 0;
6476 }
6477
6478 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6479 struct intel_crtc_state *pipe_config)
6480 {
6481 struct drm_atomic_state *state = pipe_config->base.state;
6482 struct intel_crtc *other_crtc;
6483 struct intel_crtc_state *other_crtc_state;
6484
6485 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6486 pipe_name(pipe), pipe_config->fdi_lanes);
6487 if (pipe_config->fdi_lanes > 4) {
6488 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6489 pipe_name(pipe), pipe_config->fdi_lanes);
6490 return -EINVAL;
6491 }
6492
6493 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6494 if (pipe_config->fdi_lanes > 2) {
6495 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6496 pipe_config->fdi_lanes);
6497 return -EINVAL;
6498 } else {
6499 return 0;
6500 }
6501 }
6502
6503 if (INTEL_INFO(dev)->num_pipes == 2)
6504 return 0;
6505
6506 /* Ivybridge 3 pipe is really complicated */
6507 switch (pipe) {
6508 case PIPE_A:
6509 return 0;
6510 case PIPE_B:
6511 if (pipe_config->fdi_lanes <= 2)
6512 return 0;
6513
6514 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6515 other_crtc_state =
6516 intel_atomic_get_crtc_state(state, other_crtc);
6517 if (IS_ERR(other_crtc_state))
6518 return PTR_ERR(other_crtc_state);
6519
6520 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6521 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6522 pipe_name(pipe), pipe_config->fdi_lanes);
6523 return -EINVAL;
6524 }
6525 return 0;
6526 case PIPE_C:
6527 if (pipe_config->fdi_lanes > 2) {
6528 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6529 pipe_name(pipe), pipe_config->fdi_lanes);
6530 return -EINVAL;
6531 }
6532
6533 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6534 other_crtc_state =
6535 intel_atomic_get_crtc_state(state, other_crtc);
6536 if (IS_ERR(other_crtc_state))
6537 return PTR_ERR(other_crtc_state);
6538
6539 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6540 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6541 return -EINVAL;
6542 }
6543 return 0;
6544 default:
6545 BUG();
6546 }
6547 }
6548
6549 #define RETRY 1
6550 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6551 struct intel_crtc_state *pipe_config)
6552 {
6553 struct drm_device *dev = intel_crtc->base.dev;
6554 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6555 int lane, link_bw, fdi_dotclock, ret;
6556 bool needs_recompute = false;
6557
6558 retry:
6559 /* FDI is a binary signal running at ~2.7GHz, encoding
6560 * each output octet as 10 bits. The actual frequency
6561 * is stored as a divider into a 100MHz clock, and the
6562 * mode pixel clock is stored in units of 1KHz.
6563 * Hence the bw of each lane in terms of the mode signal
6564 * is:
6565 */
6566 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6567
6568 fdi_dotclock = adjusted_mode->crtc_clock;
6569
6570 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6571 pipe_config->pipe_bpp);
6572
6573 pipe_config->fdi_lanes = lane;
6574
6575 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6576 link_bw, &pipe_config->fdi_m_n);
6577
6578 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6579 intel_crtc->pipe, pipe_config);
6580 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6581 pipe_config->pipe_bpp -= 2*3;
6582 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6583 pipe_config->pipe_bpp);
6584 needs_recompute = true;
6585 pipe_config->bw_constrained = true;
6586
6587 goto retry;
6588 }
6589
6590 if (needs_recompute)
6591 return RETRY;
6592
6593 return ret;
6594 }
6595
6596 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6597 struct intel_crtc_state *pipe_config)
6598 {
6599 if (pipe_config->pipe_bpp > 24)
6600 return false;
6601
6602 /* HSW can handle pixel rate up to cdclk? */
6603 if (IS_HASWELL(dev_priv->dev))
6604 return true;
6605
6606 /*
6607 * We compare against max which means we must take
6608 * the increased cdclk requirement into account when
6609 * calculating the new cdclk.
6610 *
6611 * Should measure whether using a lower cdclk w/o IPS
6612 */
6613 return ilk_pipe_pixel_rate(pipe_config) <=
6614 dev_priv->max_cdclk_freq * 95 / 100;
6615 }
6616
6617 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6618 struct intel_crtc_state *pipe_config)
6619 {
6620 struct drm_device *dev = crtc->base.dev;
6621 struct drm_i915_private *dev_priv = dev->dev_private;
6622
6623 pipe_config->ips_enabled = i915.enable_ips &&
6624 hsw_crtc_supports_ips(crtc) &&
6625 pipe_config_supports_ips(dev_priv, pipe_config);
6626 }
6627
6628 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6629 struct intel_crtc_state *pipe_config)
6630 {
6631 struct drm_device *dev = crtc->base.dev;
6632 struct drm_i915_private *dev_priv = dev->dev_private;
6633 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6634
6635 /* FIXME should check pixel clock limits on all platforms */
6636 if (INTEL_INFO(dev)->gen < 4) {
6637 int clock_limit = dev_priv->max_cdclk_freq;
6638
6639 /*
6640 * Enable pixel doubling when the dot clock
6641 * is > 90% of the (display) core speed.
6642 *
6643 * GDG double wide on either pipe,
6644 * otherwise pipe A only.
6645 */
6646 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6647 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6648 clock_limit *= 2;
6649 pipe_config->double_wide = true;
6650 }
6651
6652 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6653 return -EINVAL;
6654 }
6655
6656 /*
6657 * Pipe horizontal size must be even in:
6658 * - DVO ganged mode
6659 * - LVDS dual channel mode
6660 * - Double wide pipe
6661 */
6662 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6663 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6664 pipe_config->pipe_src_w &= ~1;
6665
6666 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6667 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6668 */
6669 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6670 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6671 return -EINVAL;
6672
6673 if (HAS_IPS(dev))
6674 hsw_compute_ips_config(crtc, pipe_config);
6675
6676 if (pipe_config->has_pch_encoder)
6677 return ironlake_fdi_compute_config(crtc, pipe_config);
6678
6679 return 0;
6680 }
6681
6682 static int skylake_get_display_clock_speed(struct drm_device *dev)
6683 {
6684 struct drm_i915_private *dev_priv = to_i915(dev);
6685 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6686 uint32_t cdctl = I915_READ(CDCLK_CTL);
6687 uint32_t linkrate;
6688
6689 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6690 return 24000; /* 24MHz is the cd freq with NSSC ref */
6691
6692 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6693 return 540000;
6694
6695 linkrate = (I915_READ(DPLL_CTRL1) &
6696 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6697
6698 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6699 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6700 /* vco 8640 */
6701 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6702 case CDCLK_FREQ_450_432:
6703 return 432000;
6704 case CDCLK_FREQ_337_308:
6705 return 308570;
6706 case CDCLK_FREQ_675_617:
6707 return 617140;
6708 default:
6709 WARN(1, "Unknown cd freq selection\n");
6710 }
6711 } else {
6712 /* vco 8100 */
6713 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6714 case CDCLK_FREQ_450_432:
6715 return 450000;
6716 case CDCLK_FREQ_337_308:
6717 return 337500;
6718 case CDCLK_FREQ_675_617:
6719 return 675000;
6720 default:
6721 WARN(1, "Unknown cd freq selection\n");
6722 }
6723 }
6724
6725 /* error case, do as if DPLL0 isn't enabled */
6726 return 24000;
6727 }
6728
6729 static int broxton_get_display_clock_speed(struct drm_device *dev)
6730 {
6731 struct drm_i915_private *dev_priv = to_i915(dev);
6732 uint32_t cdctl = I915_READ(CDCLK_CTL);
6733 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6734 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6735 int cdclk;
6736
6737 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6738 return 19200;
6739
6740 cdclk = 19200 * pll_ratio / 2;
6741
6742 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6743 case BXT_CDCLK_CD2X_DIV_SEL_1:
6744 return cdclk; /* 576MHz or 624MHz */
6745 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6746 return cdclk * 2 / 3; /* 384MHz */
6747 case BXT_CDCLK_CD2X_DIV_SEL_2:
6748 return cdclk / 2; /* 288MHz */
6749 case BXT_CDCLK_CD2X_DIV_SEL_4:
6750 return cdclk / 4; /* 144MHz */
6751 }
6752
6753 /* error case, do as if DE PLL isn't enabled */
6754 return 19200;
6755 }
6756
6757 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6758 {
6759 struct drm_i915_private *dev_priv = dev->dev_private;
6760 uint32_t lcpll = I915_READ(LCPLL_CTL);
6761 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6762
6763 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6764 return 800000;
6765 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6766 return 450000;
6767 else if (freq == LCPLL_CLK_FREQ_450)
6768 return 450000;
6769 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6770 return 540000;
6771 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6772 return 337500;
6773 else
6774 return 675000;
6775 }
6776
6777 static int haswell_get_display_clock_speed(struct drm_device *dev)
6778 {
6779 struct drm_i915_private *dev_priv = dev->dev_private;
6780 uint32_t lcpll = I915_READ(LCPLL_CTL);
6781 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6782
6783 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6784 return 800000;
6785 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6786 return 450000;
6787 else if (freq == LCPLL_CLK_FREQ_450)
6788 return 450000;
6789 else if (IS_HSW_ULT(dev))
6790 return 337500;
6791 else
6792 return 540000;
6793 }
6794
6795 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6796 {
6797 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6798 CCK_DISPLAY_CLOCK_CONTROL);
6799 }
6800
6801 static int ilk_get_display_clock_speed(struct drm_device *dev)
6802 {
6803 return 450000;
6804 }
6805
6806 static int i945_get_display_clock_speed(struct drm_device *dev)
6807 {
6808 return 400000;
6809 }
6810
6811 static int i915_get_display_clock_speed(struct drm_device *dev)
6812 {
6813 return 333333;
6814 }
6815
6816 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6817 {
6818 return 200000;
6819 }
6820
6821 static int pnv_get_display_clock_speed(struct drm_device *dev)
6822 {
6823 u16 gcfgc = 0;
6824
6825 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6826
6827 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6828 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6829 return 266667;
6830 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6831 return 333333;
6832 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6833 return 444444;
6834 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6835 return 200000;
6836 default:
6837 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6838 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6839 return 133333;
6840 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6841 return 166667;
6842 }
6843 }
6844
6845 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6846 {
6847 u16 gcfgc = 0;
6848
6849 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6850
6851 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6852 return 133333;
6853 else {
6854 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6855 case GC_DISPLAY_CLOCK_333_MHZ:
6856 return 333333;
6857 default:
6858 case GC_DISPLAY_CLOCK_190_200_MHZ:
6859 return 190000;
6860 }
6861 }
6862 }
6863
6864 static int i865_get_display_clock_speed(struct drm_device *dev)
6865 {
6866 return 266667;
6867 }
6868
6869 static int i85x_get_display_clock_speed(struct drm_device *dev)
6870 {
6871 u16 hpllcc = 0;
6872
6873 /*
6874 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6875 * encoding is different :(
6876 * FIXME is this the right way to detect 852GM/852GMV?
6877 */
6878 if (dev->pdev->revision == 0x1)
6879 return 133333;
6880
6881 pci_bus_read_config_word(dev->pdev->bus,
6882 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6883
6884 /* Assume that the hardware is in the high speed state. This
6885 * should be the default.
6886 */
6887 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6888 case GC_CLOCK_133_200:
6889 case GC_CLOCK_133_200_2:
6890 case GC_CLOCK_100_200:
6891 return 200000;
6892 case GC_CLOCK_166_250:
6893 return 250000;
6894 case GC_CLOCK_100_133:
6895 return 133333;
6896 case GC_CLOCK_133_266:
6897 case GC_CLOCK_133_266_2:
6898 case GC_CLOCK_166_266:
6899 return 266667;
6900 }
6901
6902 /* Shouldn't happen */
6903 return 0;
6904 }
6905
6906 static int i830_get_display_clock_speed(struct drm_device *dev)
6907 {
6908 return 133333;
6909 }
6910
6911 static unsigned int intel_hpll_vco(struct drm_device *dev)
6912 {
6913 struct drm_i915_private *dev_priv = dev->dev_private;
6914 static const unsigned int blb_vco[8] = {
6915 [0] = 3200000,
6916 [1] = 4000000,
6917 [2] = 5333333,
6918 [3] = 4800000,
6919 [4] = 6400000,
6920 };
6921 static const unsigned int pnv_vco[8] = {
6922 [0] = 3200000,
6923 [1] = 4000000,
6924 [2] = 5333333,
6925 [3] = 4800000,
6926 [4] = 2666667,
6927 };
6928 static const unsigned int cl_vco[8] = {
6929 [0] = 3200000,
6930 [1] = 4000000,
6931 [2] = 5333333,
6932 [3] = 6400000,
6933 [4] = 3333333,
6934 [5] = 3566667,
6935 [6] = 4266667,
6936 };
6937 static const unsigned int elk_vco[8] = {
6938 [0] = 3200000,
6939 [1] = 4000000,
6940 [2] = 5333333,
6941 [3] = 4800000,
6942 };
6943 static const unsigned int ctg_vco[8] = {
6944 [0] = 3200000,
6945 [1] = 4000000,
6946 [2] = 5333333,
6947 [3] = 6400000,
6948 [4] = 2666667,
6949 [5] = 4266667,
6950 };
6951 const unsigned int *vco_table;
6952 unsigned int vco;
6953 uint8_t tmp = 0;
6954
6955 /* FIXME other chipsets? */
6956 if (IS_GM45(dev))
6957 vco_table = ctg_vco;
6958 else if (IS_G4X(dev))
6959 vco_table = elk_vco;
6960 else if (IS_CRESTLINE(dev))
6961 vco_table = cl_vco;
6962 else if (IS_PINEVIEW(dev))
6963 vco_table = pnv_vco;
6964 else if (IS_G33(dev))
6965 vco_table = blb_vco;
6966 else
6967 return 0;
6968
6969 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6970
6971 vco = vco_table[tmp & 0x7];
6972 if (vco == 0)
6973 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6974 else
6975 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6976
6977 return vco;
6978 }
6979
6980 static int gm45_get_display_clock_speed(struct drm_device *dev)
6981 {
6982 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6983 uint16_t tmp = 0;
6984
6985 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6986
6987 cdclk_sel = (tmp >> 12) & 0x1;
6988
6989 switch (vco) {
6990 case 2666667:
6991 case 4000000:
6992 case 5333333:
6993 return cdclk_sel ? 333333 : 222222;
6994 case 3200000:
6995 return cdclk_sel ? 320000 : 228571;
6996 default:
6997 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6998 return 222222;
6999 }
7000 }
7001
7002 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7003 {
7004 static const uint8_t div_3200[] = { 16, 10, 8 };
7005 static const uint8_t div_4000[] = { 20, 12, 10 };
7006 static const uint8_t div_5333[] = { 24, 16, 14 };
7007 const uint8_t *div_table;
7008 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7009 uint16_t tmp = 0;
7010
7011 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7012
7013 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7014
7015 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7016 goto fail;
7017
7018 switch (vco) {
7019 case 3200000:
7020 div_table = div_3200;
7021 break;
7022 case 4000000:
7023 div_table = div_4000;
7024 break;
7025 case 5333333:
7026 div_table = div_5333;
7027 break;
7028 default:
7029 goto fail;
7030 }
7031
7032 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7033
7034 fail:
7035 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7036 return 200000;
7037 }
7038
7039 static int g33_get_display_clock_speed(struct drm_device *dev)
7040 {
7041 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7042 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7043 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7044 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7045 const uint8_t *div_table;
7046 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7047 uint16_t tmp = 0;
7048
7049 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7050
7051 cdclk_sel = (tmp >> 4) & 0x7;
7052
7053 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7054 goto fail;
7055
7056 switch (vco) {
7057 case 3200000:
7058 div_table = div_3200;
7059 break;
7060 case 4000000:
7061 div_table = div_4000;
7062 break;
7063 case 4800000:
7064 div_table = div_4800;
7065 break;
7066 case 5333333:
7067 div_table = div_5333;
7068 break;
7069 default:
7070 goto fail;
7071 }
7072
7073 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7074
7075 fail:
7076 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7077 return 190476;
7078 }
7079
7080 static void
7081 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7082 {
7083 while (*num > DATA_LINK_M_N_MASK ||
7084 *den > DATA_LINK_M_N_MASK) {
7085 *num >>= 1;
7086 *den >>= 1;
7087 }
7088 }
7089
7090 static void compute_m_n(unsigned int m, unsigned int n,
7091 uint32_t *ret_m, uint32_t *ret_n)
7092 {
7093 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7094 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7095 intel_reduce_m_n_ratio(ret_m, ret_n);
7096 }
7097
7098 void
7099 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7100 int pixel_clock, int link_clock,
7101 struct intel_link_m_n *m_n)
7102 {
7103 m_n->tu = 64;
7104
7105 compute_m_n(bits_per_pixel * pixel_clock,
7106 link_clock * nlanes * 8,
7107 &m_n->gmch_m, &m_n->gmch_n);
7108
7109 compute_m_n(pixel_clock, link_clock,
7110 &m_n->link_m, &m_n->link_n);
7111 }
7112
7113 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7114 {
7115 if (i915.panel_use_ssc >= 0)
7116 return i915.panel_use_ssc != 0;
7117 return dev_priv->vbt.lvds_use_ssc
7118 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7119 }
7120
7121 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7122 int num_connectors)
7123 {
7124 struct drm_device *dev = crtc_state->base.crtc->dev;
7125 struct drm_i915_private *dev_priv = dev->dev_private;
7126 int refclk;
7127
7128 WARN_ON(!crtc_state->base.state);
7129
7130 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7131 refclk = 100000;
7132 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7133 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7134 refclk = dev_priv->vbt.lvds_ssc_freq;
7135 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7136 } else if (!IS_GEN2(dev)) {
7137 refclk = 96000;
7138 } else {
7139 refclk = 48000;
7140 }
7141
7142 return refclk;
7143 }
7144
7145 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7146 {
7147 return (1 << dpll->n) << 16 | dpll->m2;
7148 }
7149
7150 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7151 {
7152 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7153 }
7154
7155 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7156 struct intel_crtc_state *crtc_state,
7157 intel_clock_t *reduced_clock)
7158 {
7159 struct drm_device *dev = crtc->base.dev;
7160 u32 fp, fp2 = 0;
7161
7162 if (IS_PINEVIEW(dev)) {
7163 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7164 if (reduced_clock)
7165 fp2 = pnv_dpll_compute_fp(reduced_clock);
7166 } else {
7167 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7168 if (reduced_clock)
7169 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7170 }
7171
7172 crtc_state->dpll_hw_state.fp0 = fp;
7173
7174 crtc->lowfreq_avail = false;
7175 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7176 reduced_clock) {
7177 crtc_state->dpll_hw_state.fp1 = fp2;
7178 crtc->lowfreq_avail = true;
7179 } else {
7180 crtc_state->dpll_hw_state.fp1 = fp;
7181 }
7182 }
7183
7184 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7185 pipe)
7186 {
7187 u32 reg_val;
7188
7189 /*
7190 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7191 * and set it to a reasonable value instead.
7192 */
7193 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7194 reg_val &= 0xffffff00;
7195 reg_val |= 0x00000030;
7196 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7197
7198 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7199 reg_val &= 0x8cffffff;
7200 reg_val = 0x8c000000;
7201 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7202
7203 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7204 reg_val &= 0xffffff00;
7205 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7206
7207 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7208 reg_val &= 0x00ffffff;
7209 reg_val |= 0xb0000000;
7210 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7211 }
7212
7213 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7214 struct intel_link_m_n *m_n)
7215 {
7216 struct drm_device *dev = crtc->base.dev;
7217 struct drm_i915_private *dev_priv = dev->dev_private;
7218 int pipe = crtc->pipe;
7219
7220 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7221 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7222 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7223 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7224 }
7225
7226 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7227 struct intel_link_m_n *m_n,
7228 struct intel_link_m_n *m2_n2)
7229 {
7230 struct drm_device *dev = crtc->base.dev;
7231 struct drm_i915_private *dev_priv = dev->dev_private;
7232 int pipe = crtc->pipe;
7233 enum transcoder transcoder = crtc->config->cpu_transcoder;
7234
7235 if (INTEL_INFO(dev)->gen >= 5) {
7236 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7237 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7238 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7239 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7240 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7241 * for gen < 8) and if DRRS is supported (to make sure the
7242 * registers are not unnecessarily accessed).
7243 */
7244 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7245 crtc->config->has_drrs) {
7246 I915_WRITE(PIPE_DATA_M2(transcoder),
7247 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7248 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7249 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7250 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7251 }
7252 } else {
7253 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7254 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7255 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7256 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7257 }
7258 }
7259
7260 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7261 {
7262 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7263
7264 if (m_n == M1_N1) {
7265 dp_m_n = &crtc->config->dp_m_n;
7266 dp_m2_n2 = &crtc->config->dp_m2_n2;
7267 } else if (m_n == M2_N2) {
7268
7269 /*
7270 * M2_N2 registers are not supported. Hence m2_n2 divider value
7271 * needs to be programmed into M1_N1.
7272 */
7273 dp_m_n = &crtc->config->dp_m2_n2;
7274 } else {
7275 DRM_ERROR("Unsupported divider value\n");
7276 return;
7277 }
7278
7279 if (crtc->config->has_pch_encoder)
7280 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7281 else
7282 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7283 }
7284
7285 static void vlv_compute_dpll(struct intel_crtc *crtc,
7286 struct intel_crtc_state *pipe_config)
7287 {
7288 u32 dpll, dpll_md;
7289
7290 /*
7291 * Enable DPIO clock input. We should never disable the reference
7292 * clock for pipe B, since VGA hotplug / manual detection depends
7293 * on it.
7294 */
7295 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7296 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7297 /* We should never disable this, set it here for state tracking */
7298 if (crtc->pipe == PIPE_B)
7299 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7300 dpll |= DPLL_VCO_ENABLE;
7301 pipe_config->dpll_hw_state.dpll = dpll;
7302
7303 dpll_md = (pipe_config->pixel_multiplier - 1)
7304 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7305 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7306 }
7307
7308 static void vlv_prepare_pll(struct intel_crtc *crtc,
7309 const struct intel_crtc_state *pipe_config)
7310 {
7311 struct drm_device *dev = crtc->base.dev;
7312 struct drm_i915_private *dev_priv = dev->dev_private;
7313 int pipe = crtc->pipe;
7314 u32 mdiv;
7315 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7316 u32 coreclk, reg_val;
7317
7318 mutex_lock(&dev_priv->sb_lock);
7319
7320 bestn = pipe_config->dpll.n;
7321 bestm1 = pipe_config->dpll.m1;
7322 bestm2 = pipe_config->dpll.m2;
7323 bestp1 = pipe_config->dpll.p1;
7324 bestp2 = pipe_config->dpll.p2;
7325
7326 /* See eDP HDMI DPIO driver vbios notes doc */
7327
7328 /* PLL B needs special handling */
7329 if (pipe == PIPE_B)
7330 vlv_pllb_recal_opamp(dev_priv, pipe);
7331
7332 /* Set up Tx target for periodic Rcomp update */
7333 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7334
7335 /* Disable target IRef on PLL */
7336 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7337 reg_val &= 0x00ffffff;
7338 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7339
7340 /* Disable fast lock */
7341 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7342
7343 /* Set idtafcrecal before PLL is enabled */
7344 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7345 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7346 mdiv |= ((bestn << DPIO_N_SHIFT));
7347 mdiv |= (1 << DPIO_K_SHIFT);
7348
7349 /*
7350 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7351 * but we don't support that).
7352 * Note: don't use the DAC post divider as it seems unstable.
7353 */
7354 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7356
7357 mdiv |= DPIO_ENABLE_CALIBRATION;
7358 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7359
7360 /* Set HBR and RBR LPF coefficients */
7361 if (pipe_config->port_clock == 162000 ||
7362 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7363 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7364 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7365 0x009f0003);
7366 else
7367 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7368 0x00d0000f);
7369
7370 if (pipe_config->has_dp_encoder) {
7371 /* Use SSC source */
7372 if (pipe == PIPE_A)
7373 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7374 0x0df40000);
7375 else
7376 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7377 0x0df70000);
7378 } else { /* HDMI or VGA */
7379 /* Use bend source */
7380 if (pipe == PIPE_A)
7381 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7382 0x0df70000);
7383 else
7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7385 0x0df40000);
7386 }
7387
7388 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7389 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7391 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7392 coreclk |= 0x01000000;
7393 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7394
7395 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7396 mutex_unlock(&dev_priv->sb_lock);
7397 }
7398
7399 static void chv_compute_dpll(struct intel_crtc *crtc,
7400 struct intel_crtc_state *pipe_config)
7401 {
7402 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7403 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7404 DPLL_VCO_ENABLE;
7405 if (crtc->pipe != PIPE_A)
7406 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7407
7408 pipe_config->dpll_hw_state.dpll_md =
7409 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7410 }
7411
7412 static void chv_prepare_pll(struct intel_crtc *crtc,
7413 const struct intel_crtc_state *pipe_config)
7414 {
7415 struct drm_device *dev = crtc->base.dev;
7416 struct drm_i915_private *dev_priv = dev->dev_private;
7417 int pipe = crtc->pipe;
7418 int dpll_reg = DPLL(crtc->pipe);
7419 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7420 u32 loopfilter, tribuf_calcntr;
7421 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7422 u32 dpio_val;
7423 int vco;
7424
7425 bestn = pipe_config->dpll.n;
7426 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7427 bestm1 = pipe_config->dpll.m1;
7428 bestm2 = pipe_config->dpll.m2 >> 22;
7429 bestp1 = pipe_config->dpll.p1;
7430 bestp2 = pipe_config->dpll.p2;
7431 vco = pipe_config->dpll.vco;
7432 dpio_val = 0;
7433 loopfilter = 0;
7434
7435 /*
7436 * Enable Refclk and SSC
7437 */
7438 I915_WRITE(dpll_reg,
7439 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7440
7441 mutex_lock(&dev_priv->sb_lock);
7442
7443 /* p1 and p2 divider */
7444 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7445 5 << DPIO_CHV_S1_DIV_SHIFT |
7446 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7447 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7448 1 << DPIO_CHV_K_DIV_SHIFT);
7449
7450 /* Feedback post-divider - m2 */
7451 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7452
7453 /* Feedback refclk divider - n and m1 */
7454 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7455 DPIO_CHV_M1_DIV_BY_2 |
7456 1 << DPIO_CHV_N_DIV_SHIFT);
7457
7458 /* M2 fraction division */
7459 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7460
7461 /* M2 fraction division enable */
7462 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7463 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7464 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7465 if (bestm2_frac)
7466 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7467 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7468
7469 /* Program digital lock detect threshold */
7470 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7471 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7472 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7473 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7474 if (!bestm2_frac)
7475 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7476 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7477
7478 /* Loop filter */
7479 if (vco == 5400000) {
7480 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7481 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7482 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7483 tribuf_calcntr = 0x9;
7484 } else if (vco <= 6200000) {
7485 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7486 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7487 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7488 tribuf_calcntr = 0x9;
7489 } else if (vco <= 6480000) {
7490 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7491 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7492 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7493 tribuf_calcntr = 0x8;
7494 } else {
7495 /* Not supported. Apply the same limits as in the max case */
7496 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7497 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7498 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7499 tribuf_calcntr = 0;
7500 }
7501 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7502
7503 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7504 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7505 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7506 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7507
7508 /* AFC Recal */
7509 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7510 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7511 DPIO_AFC_RECAL);
7512
7513 mutex_unlock(&dev_priv->sb_lock);
7514 }
7515
7516 /**
7517 * vlv_force_pll_on - forcibly enable just the PLL
7518 * @dev_priv: i915 private structure
7519 * @pipe: pipe PLL to enable
7520 * @dpll: PLL configuration
7521 *
7522 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7523 * in cases where we need the PLL enabled even when @pipe is not going to
7524 * be enabled.
7525 */
7526 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7527 const struct dpll *dpll)
7528 {
7529 struct intel_crtc *crtc =
7530 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7531 struct intel_crtc_state pipe_config = {
7532 .base.crtc = &crtc->base,
7533 .pixel_multiplier = 1,
7534 .dpll = *dpll,
7535 };
7536
7537 if (IS_CHERRYVIEW(dev)) {
7538 chv_compute_dpll(crtc, &pipe_config);
7539 chv_prepare_pll(crtc, &pipe_config);
7540 chv_enable_pll(crtc, &pipe_config);
7541 } else {
7542 vlv_compute_dpll(crtc, &pipe_config);
7543 vlv_prepare_pll(crtc, &pipe_config);
7544 vlv_enable_pll(crtc, &pipe_config);
7545 }
7546 }
7547
7548 /**
7549 * vlv_force_pll_off - forcibly disable just the PLL
7550 * @dev_priv: i915 private structure
7551 * @pipe: pipe PLL to disable
7552 *
7553 * Disable the PLL for @pipe. To be used in cases where we need
7554 * the PLL enabled even when @pipe is not going to be enabled.
7555 */
7556 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7557 {
7558 if (IS_CHERRYVIEW(dev))
7559 chv_disable_pll(to_i915(dev), pipe);
7560 else
7561 vlv_disable_pll(to_i915(dev), pipe);
7562 }
7563
7564 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7565 struct intel_crtc_state *crtc_state,
7566 intel_clock_t *reduced_clock,
7567 int num_connectors)
7568 {
7569 struct drm_device *dev = crtc->base.dev;
7570 struct drm_i915_private *dev_priv = dev->dev_private;
7571 u32 dpll;
7572 bool is_sdvo;
7573 struct dpll *clock = &crtc_state->dpll;
7574
7575 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7576
7577 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7578 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7579
7580 dpll = DPLL_VGA_MODE_DIS;
7581
7582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7583 dpll |= DPLLB_MODE_LVDS;
7584 else
7585 dpll |= DPLLB_MODE_DAC_SERIAL;
7586
7587 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7588 dpll |= (crtc_state->pixel_multiplier - 1)
7589 << SDVO_MULTIPLIER_SHIFT_HIRES;
7590 }
7591
7592 if (is_sdvo)
7593 dpll |= DPLL_SDVO_HIGH_SPEED;
7594
7595 if (crtc_state->has_dp_encoder)
7596 dpll |= DPLL_SDVO_HIGH_SPEED;
7597
7598 /* compute bitmask from p1 value */
7599 if (IS_PINEVIEW(dev))
7600 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7601 else {
7602 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7603 if (IS_G4X(dev) && reduced_clock)
7604 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7605 }
7606 switch (clock->p2) {
7607 case 5:
7608 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7609 break;
7610 case 7:
7611 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7612 break;
7613 case 10:
7614 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7615 break;
7616 case 14:
7617 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7618 break;
7619 }
7620 if (INTEL_INFO(dev)->gen >= 4)
7621 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7622
7623 if (crtc_state->sdvo_tv_clock)
7624 dpll |= PLL_REF_INPUT_TVCLKINBC;
7625 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7626 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7627 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7628 else
7629 dpll |= PLL_REF_INPUT_DREFCLK;
7630
7631 dpll |= DPLL_VCO_ENABLE;
7632 crtc_state->dpll_hw_state.dpll = dpll;
7633
7634 if (INTEL_INFO(dev)->gen >= 4) {
7635 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7636 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7637 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7638 }
7639 }
7640
7641 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7642 struct intel_crtc_state *crtc_state,
7643 intel_clock_t *reduced_clock,
7644 int num_connectors)
7645 {
7646 struct drm_device *dev = crtc->base.dev;
7647 struct drm_i915_private *dev_priv = dev->dev_private;
7648 u32 dpll;
7649 struct dpll *clock = &crtc_state->dpll;
7650
7651 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7652
7653 dpll = DPLL_VGA_MODE_DIS;
7654
7655 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7656 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7657 } else {
7658 if (clock->p1 == 2)
7659 dpll |= PLL_P1_DIVIDE_BY_TWO;
7660 else
7661 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7662 if (clock->p2 == 4)
7663 dpll |= PLL_P2_DIVIDE_BY_4;
7664 }
7665
7666 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7667 dpll |= DPLL_DVO_2X_MODE;
7668
7669 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7670 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7671 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7672 else
7673 dpll |= PLL_REF_INPUT_DREFCLK;
7674
7675 dpll |= DPLL_VCO_ENABLE;
7676 crtc_state->dpll_hw_state.dpll = dpll;
7677 }
7678
7679 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7680 {
7681 struct drm_device *dev = intel_crtc->base.dev;
7682 struct drm_i915_private *dev_priv = dev->dev_private;
7683 enum pipe pipe = intel_crtc->pipe;
7684 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7685 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7686 uint32_t crtc_vtotal, crtc_vblank_end;
7687 int vsyncshift = 0;
7688
7689 /* We need to be careful not to changed the adjusted mode, for otherwise
7690 * the hw state checker will get angry at the mismatch. */
7691 crtc_vtotal = adjusted_mode->crtc_vtotal;
7692 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7693
7694 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7695 /* the chip adds 2 halflines automatically */
7696 crtc_vtotal -= 1;
7697 crtc_vblank_end -= 1;
7698
7699 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7700 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7701 else
7702 vsyncshift = adjusted_mode->crtc_hsync_start -
7703 adjusted_mode->crtc_htotal / 2;
7704 if (vsyncshift < 0)
7705 vsyncshift += adjusted_mode->crtc_htotal;
7706 }
7707
7708 if (INTEL_INFO(dev)->gen > 3)
7709 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7710
7711 I915_WRITE(HTOTAL(cpu_transcoder),
7712 (adjusted_mode->crtc_hdisplay - 1) |
7713 ((adjusted_mode->crtc_htotal - 1) << 16));
7714 I915_WRITE(HBLANK(cpu_transcoder),
7715 (adjusted_mode->crtc_hblank_start - 1) |
7716 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7717 I915_WRITE(HSYNC(cpu_transcoder),
7718 (adjusted_mode->crtc_hsync_start - 1) |
7719 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7720
7721 I915_WRITE(VTOTAL(cpu_transcoder),
7722 (adjusted_mode->crtc_vdisplay - 1) |
7723 ((crtc_vtotal - 1) << 16));
7724 I915_WRITE(VBLANK(cpu_transcoder),
7725 (adjusted_mode->crtc_vblank_start - 1) |
7726 ((crtc_vblank_end - 1) << 16));
7727 I915_WRITE(VSYNC(cpu_transcoder),
7728 (adjusted_mode->crtc_vsync_start - 1) |
7729 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7730
7731 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7732 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7733 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7734 * bits. */
7735 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7736 (pipe == PIPE_B || pipe == PIPE_C))
7737 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7738
7739 /* pipesrc controls the size that is scaled from, which should
7740 * always be the user's requested size.
7741 */
7742 I915_WRITE(PIPESRC(pipe),
7743 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7744 (intel_crtc->config->pipe_src_h - 1));
7745 }
7746
7747 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7748 struct intel_crtc_state *pipe_config)
7749 {
7750 struct drm_device *dev = crtc->base.dev;
7751 struct drm_i915_private *dev_priv = dev->dev_private;
7752 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7753 uint32_t tmp;
7754
7755 tmp = I915_READ(HTOTAL(cpu_transcoder));
7756 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7757 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7758 tmp = I915_READ(HBLANK(cpu_transcoder));
7759 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7760 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7761 tmp = I915_READ(HSYNC(cpu_transcoder));
7762 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7763 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7764
7765 tmp = I915_READ(VTOTAL(cpu_transcoder));
7766 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7767 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7768 tmp = I915_READ(VBLANK(cpu_transcoder));
7769 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7770 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7771 tmp = I915_READ(VSYNC(cpu_transcoder));
7772 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7773 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7774
7775 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7776 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7777 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7778 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7779 }
7780
7781 tmp = I915_READ(PIPESRC(crtc->pipe));
7782 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7783 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7784
7785 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7786 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7787 }
7788
7789 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7790 struct intel_crtc_state *pipe_config)
7791 {
7792 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7793 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7794 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7795 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7796
7797 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7798 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7799 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7800 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7801
7802 mode->flags = pipe_config->base.adjusted_mode.flags;
7803 mode->type = DRM_MODE_TYPE_DRIVER;
7804
7805 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7806 mode->flags |= pipe_config->base.adjusted_mode.flags;
7807
7808 mode->hsync = drm_mode_hsync(mode);
7809 mode->vrefresh = drm_mode_vrefresh(mode);
7810 drm_mode_set_name(mode);
7811 }
7812
7813 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7814 {
7815 struct drm_device *dev = intel_crtc->base.dev;
7816 struct drm_i915_private *dev_priv = dev->dev_private;
7817 uint32_t pipeconf;
7818
7819 pipeconf = 0;
7820
7821 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7822 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7823 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7824
7825 if (intel_crtc->config->double_wide)
7826 pipeconf |= PIPECONF_DOUBLE_WIDE;
7827
7828 /* only g4x and later have fancy bpc/dither controls */
7829 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7830 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7831 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7832 pipeconf |= PIPECONF_DITHER_EN |
7833 PIPECONF_DITHER_TYPE_SP;
7834
7835 switch (intel_crtc->config->pipe_bpp) {
7836 case 18:
7837 pipeconf |= PIPECONF_6BPC;
7838 break;
7839 case 24:
7840 pipeconf |= PIPECONF_8BPC;
7841 break;
7842 case 30:
7843 pipeconf |= PIPECONF_10BPC;
7844 break;
7845 default:
7846 /* Case prevented by intel_choose_pipe_bpp_dither. */
7847 BUG();
7848 }
7849 }
7850
7851 if (HAS_PIPE_CXSR(dev)) {
7852 if (intel_crtc->lowfreq_avail) {
7853 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7854 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7855 } else {
7856 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7857 }
7858 }
7859
7860 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7861 if (INTEL_INFO(dev)->gen < 4 ||
7862 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7863 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7864 else
7865 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7866 } else
7867 pipeconf |= PIPECONF_PROGRESSIVE;
7868
7869 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7870 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7871
7872 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7873 POSTING_READ(PIPECONF(intel_crtc->pipe));
7874 }
7875
7876 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7877 struct intel_crtc_state *crtc_state)
7878 {
7879 struct drm_device *dev = crtc->base.dev;
7880 struct drm_i915_private *dev_priv = dev->dev_private;
7881 int refclk, num_connectors = 0;
7882 intel_clock_t clock;
7883 bool ok;
7884 bool is_dsi = false;
7885 struct intel_encoder *encoder;
7886 const intel_limit_t *limit;
7887 struct drm_atomic_state *state = crtc_state->base.state;
7888 struct drm_connector *connector;
7889 struct drm_connector_state *connector_state;
7890 int i;
7891
7892 memset(&crtc_state->dpll_hw_state, 0,
7893 sizeof(crtc_state->dpll_hw_state));
7894
7895 for_each_connector_in_state(state, connector, connector_state, i) {
7896 if (connector_state->crtc != &crtc->base)
7897 continue;
7898
7899 encoder = to_intel_encoder(connector_state->best_encoder);
7900
7901 switch (encoder->type) {
7902 case INTEL_OUTPUT_DSI:
7903 is_dsi = true;
7904 break;
7905 default:
7906 break;
7907 }
7908
7909 num_connectors++;
7910 }
7911
7912 if (is_dsi)
7913 return 0;
7914
7915 if (!crtc_state->clock_set) {
7916 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7917
7918 /*
7919 * Returns a set of divisors for the desired target clock with
7920 * the given refclk, or FALSE. The returned values represent
7921 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7922 * 2) / p1 / p2.
7923 */
7924 limit = intel_limit(crtc_state, refclk);
7925 ok = dev_priv->display.find_dpll(limit, crtc_state,
7926 crtc_state->port_clock,
7927 refclk, NULL, &clock);
7928 if (!ok) {
7929 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7930 return -EINVAL;
7931 }
7932
7933 /* Compat-code for transition, will disappear. */
7934 crtc_state->dpll.n = clock.n;
7935 crtc_state->dpll.m1 = clock.m1;
7936 crtc_state->dpll.m2 = clock.m2;
7937 crtc_state->dpll.p1 = clock.p1;
7938 crtc_state->dpll.p2 = clock.p2;
7939 }
7940
7941 if (IS_GEN2(dev)) {
7942 i8xx_compute_dpll(crtc, crtc_state, NULL,
7943 num_connectors);
7944 } else if (IS_CHERRYVIEW(dev)) {
7945 chv_compute_dpll(crtc, crtc_state);
7946 } else if (IS_VALLEYVIEW(dev)) {
7947 vlv_compute_dpll(crtc, crtc_state);
7948 } else {
7949 i9xx_compute_dpll(crtc, crtc_state, NULL,
7950 num_connectors);
7951 }
7952
7953 return 0;
7954 }
7955
7956 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7957 struct intel_crtc_state *pipe_config)
7958 {
7959 struct drm_device *dev = crtc->base.dev;
7960 struct drm_i915_private *dev_priv = dev->dev_private;
7961 uint32_t tmp;
7962
7963 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7964 return;
7965
7966 tmp = I915_READ(PFIT_CONTROL);
7967 if (!(tmp & PFIT_ENABLE))
7968 return;
7969
7970 /* Check whether the pfit is attached to our pipe. */
7971 if (INTEL_INFO(dev)->gen < 4) {
7972 if (crtc->pipe != PIPE_B)
7973 return;
7974 } else {
7975 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7976 return;
7977 }
7978
7979 pipe_config->gmch_pfit.control = tmp;
7980 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7981 if (INTEL_INFO(dev)->gen < 5)
7982 pipe_config->gmch_pfit.lvds_border_bits =
7983 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7984 }
7985
7986 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7987 struct intel_crtc_state *pipe_config)
7988 {
7989 struct drm_device *dev = crtc->base.dev;
7990 struct drm_i915_private *dev_priv = dev->dev_private;
7991 int pipe = pipe_config->cpu_transcoder;
7992 intel_clock_t clock;
7993 u32 mdiv;
7994 int refclk = 100000;
7995
7996 /* In case of MIPI DPLL will not even be used */
7997 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7998 return;
7999
8000 mutex_lock(&dev_priv->sb_lock);
8001 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8002 mutex_unlock(&dev_priv->sb_lock);
8003
8004 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8005 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8006 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8007 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8008 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8009
8010 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8011 }
8012
8013 static void
8014 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8015 struct intel_initial_plane_config *plane_config)
8016 {
8017 struct drm_device *dev = crtc->base.dev;
8018 struct drm_i915_private *dev_priv = dev->dev_private;
8019 u32 val, base, offset;
8020 int pipe = crtc->pipe, plane = crtc->plane;
8021 int fourcc, pixel_format;
8022 unsigned int aligned_height;
8023 struct drm_framebuffer *fb;
8024 struct intel_framebuffer *intel_fb;
8025
8026 val = I915_READ(DSPCNTR(plane));
8027 if (!(val & DISPLAY_PLANE_ENABLE))
8028 return;
8029
8030 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8031 if (!intel_fb) {
8032 DRM_DEBUG_KMS("failed to alloc fb\n");
8033 return;
8034 }
8035
8036 fb = &intel_fb->base;
8037
8038 if (INTEL_INFO(dev)->gen >= 4) {
8039 if (val & DISPPLANE_TILED) {
8040 plane_config->tiling = I915_TILING_X;
8041 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8042 }
8043 }
8044
8045 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8046 fourcc = i9xx_format_to_fourcc(pixel_format);
8047 fb->pixel_format = fourcc;
8048 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8049
8050 if (INTEL_INFO(dev)->gen >= 4) {
8051 if (plane_config->tiling)
8052 offset = I915_READ(DSPTILEOFF(plane));
8053 else
8054 offset = I915_READ(DSPLINOFF(plane));
8055 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8056 } else {
8057 base = I915_READ(DSPADDR(plane));
8058 }
8059 plane_config->base = base;
8060
8061 val = I915_READ(PIPESRC(pipe));
8062 fb->width = ((val >> 16) & 0xfff) + 1;
8063 fb->height = ((val >> 0) & 0xfff) + 1;
8064
8065 val = I915_READ(DSPSTRIDE(pipe));
8066 fb->pitches[0] = val & 0xffffffc0;
8067
8068 aligned_height = intel_fb_align_height(dev, fb->height,
8069 fb->pixel_format,
8070 fb->modifier[0]);
8071
8072 plane_config->size = fb->pitches[0] * aligned_height;
8073
8074 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8075 pipe_name(pipe), plane, fb->width, fb->height,
8076 fb->bits_per_pixel, base, fb->pitches[0],
8077 plane_config->size);
8078
8079 plane_config->fb = intel_fb;
8080 }
8081
8082 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8083 struct intel_crtc_state *pipe_config)
8084 {
8085 struct drm_device *dev = crtc->base.dev;
8086 struct drm_i915_private *dev_priv = dev->dev_private;
8087 int pipe = pipe_config->cpu_transcoder;
8088 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8089 intel_clock_t clock;
8090 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8091 int refclk = 100000;
8092
8093 mutex_lock(&dev_priv->sb_lock);
8094 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8095 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8096 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8097 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8098 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8099 mutex_unlock(&dev_priv->sb_lock);
8100
8101 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8102 clock.m2 = (pll_dw0 & 0xff) << 22;
8103 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8104 clock.m2 |= pll_dw2 & 0x3fffff;
8105 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8106 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8107 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8108
8109 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8110 }
8111
8112 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8113 struct intel_crtc_state *pipe_config)
8114 {
8115 struct drm_device *dev = crtc->base.dev;
8116 struct drm_i915_private *dev_priv = dev->dev_private;
8117 uint32_t tmp;
8118
8119 if (!intel_display_power_is_enabled(dev_priv,
8120 POWER_DOMAIN_PIPE(crtc->pipe)))
8121 return false;
8122
8123 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8124 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8125
8126 tmp = I915_READ(PIPECONF(crtc->pipe));
8127 if (!(tmp & PIPECONF_ENABLE))
8128 return false;
8129
8130 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8131 switch (tmp & PIPECONF_BPC_MASK) {
8132 case PIPECONF_6BPC:
8133 pipe_config->pipe_bpp = 18;
8134 break;
8135 case PIPECONF_8BPC:
8136 pipe_config->pipe_bpp = 24;
8137 break;
8138 case PIPECONF_10BPC:
8139 pipe_config->pipe_bpp = 30;
8140 break;
8141 default:
8142 break;
8143 }
8144 }
8145
8146 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8147 pipe_config->limited_color_range = true;
8148
8149 if (INTEL_INFO(dev)->gen < 4)
8150 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8151
8152 intel_get_pipe_timings(crtc, pipe_config);
8153
8154 i9xx_get_pfit_config(crtc, pipe_config);
8155
8156 if (INTEL_INFO(dev)->gen >= 4) {
8157 tmp = I915_READ(DPLL_MD(crtc->pipe));
8158 pipe_config->pixel_multiplier =
8159 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8160 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8161 pipe_config->dpll_hw_state.dpll_md = tmp;
8162 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8163 tmp = I915_READ(DPLL(crtc->pipe));
8164 pipe_config->pixel_multiplier =
8165 ((tmp & SDVO_MULTIPLIER_MASK)
8166 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8167 } else {
8168 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8169 * port and will be fixed up in the encoder->get_config
8170 * function. */
8171 pipe_config->pixel_multiplier = 1;
8172 }
8173 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8174 if (!IS_VALLEYVIEW(dev)) {
8175 /*
8176 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8177 * on 830. Filter it out here so that we don't
8178 * report errors due to that.
8179 */
8180 if (IS_I830(dev))
8181 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8182
8183 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8184 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8185 } else {
8186 /* Mask out read-only status bits. */
8187 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8188 DPLL_PORTC_READY_MASK |
8189 DPLL_PORTB_READY_MASK);
8190 }
8191
8192 if (IS_CHERRYVIEW(dev))
8193 chv_crtc_clock_get(crtc, pipe_config);
8194 else if (IS_VALLEYVIEW(dev))
8195 vlv_crtc_clock_get(crtc, pipe_config);
8196 else
8197 i9xx_crtc_clock_get(crtc, pipe_config);
8198
8199 /*
8200 * Normally the dotclock is filled in by the encoder .get_config()
8201 * but in case the pipe is enabled w/o any ports we need a sane
8202 * default.
8203 */
8204 pipe_config->base.adjusted_mode.crtc_clock =
8205 pipe_config->port_clock / pipe_config->pixel_multiplier;
8206
8207 return true;
8208 }
8209
8210 static void ironlake_init_pch_refclk(struct drm_device *dev)
8211 {
8212 struct drm_i915_private *dev_priv = dev->dev_private;
8213 struct intel_encoder *encoder;
8214 u32 val, final;
8215 bool has_lvds = false;
8216 bool has_cpu_edp = false;
8217 bool has_panel = false;
8218 bool has_ck505 = false;
8219 bool can_ssc = false;
8220
8221 /* We need to take the global config into account */
8222 for_each_intel_encoder(dev, encoder) {
8223 switch (encoder->type) {
8224 case INTEL_OUTPUT_LVDS:
8225 has_panel = true;
8226 has_lvds = true;
8227 break;
8228 case INTEL_OUTPUT_EDP:
8229 has_panel = true;
8230 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8231 has_cpu_edp = true;
8232 break;
8233 default:
8234 break;
8235 }
8236 }
8237
8238 if (HAS_PCH_IBX(dev)) {
8239 has_ck505 = dev_priv->vbt.display_clock_mode;
8240 can_ssc = has_ck505;
8241 } else {
8242 has_ck505 = false;
8243 can_ssc = true;
8244 }
8245
8246 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8247 has_panel, has_lvds, has_ck505);
8248
8249 /* Ironlake: try to setup display ref clock before DPLL
8250 * enabling. This is only under driver's control after
8251 * PCH B stepping, previous chipset stepping should be
8252 * ignoring this setting.
8253 */
8254 val = I915_READ(PCH_DREF_CONTROL);
8255
8256 /* As we must carefully and slowly disable/enable each source in turn,
8257 * compute the final state we want first and check if we need to
8258 * make any changes at all.
8259 */
8260 final = val;
8261 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8262 if (has_ck505)
8263 final |= DREF_NONSPREAD_CK505_ENABLE;
8264 else
8265 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8266
8267 final &= ~DREF_SSC_SOURCE_MASK;
8268 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8269 final &= ~DREF_SSC1_ENABLE;
8270
8271 if (has_panel) {
8272 final |= DREF_SSC_SOURCE_ENABLE;
8273
8274 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8275 final |= DREF_SSC1_ENABLE;
8276
8277 if (has_cpu_edp) {
8278 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8279 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8280 else
8281 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8282 } else
8283 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8284 } else {
8285 final |= DREF_SSC_SOURCE_DISABLE;
8286 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8287 }
8288
8289 if (final == val)
8290 return;
8291
8292 /* Always enable nonspread source */
8293 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8294
8295 if (has_ck505)
8296 val |= DREF_NONSPREAD_CK505_ENABLE;
8297 else
8298 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8299
8300 if (has_panel) {
8301 val &= ~DREF_SSC_SOURCE_MASK;
8302 val |= DREF_SSC_SOURCE_ENABLE;
8303
8304 /* SSC must be turned on before enabling the CPU output */
8305 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8306 DRM_DEBUG_KMS("Using SSC on panel\n");
8307 val |= DREF_SSC1_ENABLE;
8308 } else
8309 val &= ~DREF_SSC1_ENABLE;
8310
8311 /* Get SSC going before enabling the outputs */
8312 I915_WRITE(PCH_DREF_CONTROL, val);
8313 POSTING_READ(PCH_DREF_CONTROL);
8314 udelay(200);
8315
8316 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8317
8318 /* Enable CPU source on CPU attached eDP */
8319 if (has_cpu_edp) {
8320 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8321 DRM_DEBUG_KMS("Using SSC on eDP\n");
8322 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8323 } else
8324 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8325 } else
8326 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8327
8328 I915_WRITE(PCH_DREF_CONTROL, val);
8329 POSTING_READ(PCH_DREF_CONTROL);
8330 udelay(200);
8331 } else {
8332 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8333
8334 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8335
8336 /* Turn off CPU output */
8337 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8338
8339 I915_WRITE(PCH_DREF_CONTROL, val);
8340 POSTING_READ(PCH_DREF_CONTROL);
8341 udelay(200);
8342
8343 /* Turn off the SSC source */
8344 val &= ~DREF_SSC_SOURCE_MASK;
8345 val |= DREF_SSC_SOURCE_DISABLE;
8346
8347 /* Turn off SSC1 */
8348 val &= ~DREF_SSC1_ENABLE;
8349
8350 I915_WRITE(PCH_DREF_CONTROL, val);
8351 POSTING_READ(PCH_DREF_CONTROL);
8352 udelay(200);
8353 }
8354
8355 BUG_ON(val != final);
8356 }
8357
8358 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8359 {
8360 uint32_t tmp;
8361
8362 tmp = I915_READ(SOUTH_CHICKEN2);
8363 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8364 I915_WRITE(SOUTH_CHICKEN2, tmp);
8365
8366 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8367 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8368 DRM_ERROR("FDI mPHY reset assert timeout\n");
8369
8370 tmp = I915_READ(SOUTH_CHICKEN2);
8371 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8372 I915_WRITE(SOUTH_CHICKEN2, tmp);
8373
8374 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8375 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8376 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8377 }
8378
8379 /* WaMPhyProgramming:hsw */
8380 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8381 {
8382 uint32_t tmp;
8383
8384 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8385 tmp &= ~(0xFF << 24);
8386 tmp |= (0x12 << 24);
8387 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8388
8389 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8390 tmp |= (1 << 11);
8391 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8392
8393 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8394 tmp |= (1 << 11);
8395 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8396
8397 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8398 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8399 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8400
8401 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8402 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8403 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8404
8405 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8406 tmp &= ~(7 << 13);
8407 tmp |= (5 << 13);
8408 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8409
8410 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8411 tmp &= ~(7 << 13);
8412 tmp |= (5 << 13);
8413 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8414
8415 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8416 tmp &= ~0xFF;
8417 tmp |= 0x1C;
8418 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8419
8420 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8421 tmp &= ~0xFF;
8422 tmp |= 0x1C;
8423 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8424
8425 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8426 tmp &= ~(0xFF << 16);
8427 tmp |= (0x1C << 16);
8428 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8429
8430 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8431 tmp &= ~(0xFF << 16);
8432 tmp |= (0x1C << 16);
8433 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8434
8435 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8436 tmp |= (1 << 27);
8437 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8438
8439 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8440 tmp |= (1 << 27);
8441 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8442
8443 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8444 tmp &= ~(0xF << 28);
8445 tmp |= (4 << 28);
8446 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8447
8448 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8449 tmp &= ~(0xF << 28);
8450 tmp |= (4 << 28);
8451 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8452 }
8453
8454 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8455 * Programming" based on the parameters passed:
8456 * - Sequence to enable CLKOUT_DP
8457 * - Sequence to enable CLKOUT_DP without spread
8458 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8459 */
8460 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8461 bool with_fdi)
8462 {
8463 struct drm_i915_private *dev_priv = dev->dev_private;
8464 uint32_t reg, tmp;
8465
8466 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8467 with_spread = true;
8468 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8469 with_fdi = false;
8470
8471 mutex_lock(&dev_priv->sb_lock);
8472
8473 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8474 tmp &= ~SBI_SSCCTL_DISABLE;
8475 tmp |= SBI_SSCCTL_PATHALT;
8476 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8477
8478 udelay(24);
8479
8480 if (with_spread) {
8481 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8482 tmp &= ~SBI_SSCCTL_PATHALT;
8483 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8484
8485 if (with_fdi) {
8486 lpt_reset_fdi_mphy(dev_priv);
8487 lpt_program_fdi_mphy(dev_priv);
8488 }
8489 }
8490
8491 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8492 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8493 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8494 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8495
8496 mutex_unlock(&dev_priv->sb_lock);
8497 }
8498
8499 /* Sequence to disable CLKOUT_DP */
8500 static void lpt_disable_clkout_dp(struct drm_device *dev)
8501 {
8502 struct drm_i915_private *dev_priv = dev->dev_private;
8503 uint32_t reg, tmp;
8504
8505 mutex_lock(&dev_priv->sb_lock);
8506
8507 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8508 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8509 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8510 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8511
8512 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8513 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8514 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8515 tmp |= SBI_SSCCTL_PATHALT;
8516 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8517 udelay(32);
8518 }
8519 tmp |= SBI_SSCCTL_DISABLE;
8520 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8521 }
8522
8523 mutex_unlock(&dev_priv->sb_lock);
8524 }
8525
8526 static void lpt_init_pch_refclk(struct drm_device *dev)
8527 {
8528 struct intel_encoder *encoder;
8529 bool has_vga = false;
8530
8531 for_each_intel_encoder(dev, encoder) {
8532 switch (encoder->type) {
8533 case INTEL_OUTPUT_ANALOG:
8534 has_vga = true;
8535 break;
8536 default:
8537 break;
8538 }
8539 }
8540
8541 if (has_vga)
8542 lpt_enable_clkout_dp(dev, true, true);
8543 else
8544 lpt_disable_clkout_dp(dev);
8545 }
8546
8547 /*
8548 * Initialize reference clocks when the driver loads
8549 */
8550 void intel_init_pch_refclk(struct drm_device *dev)
8551 {
8552 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8553 ironlake_init_pch_refclk(dev);
8554 else if (HAS_PCH_LPT(dev))
8555 lpt_init_pch_refclk(dev);
8556 }
8557
8558 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8559 {
8560 struct drm_device *dev = crtc_state->base.crtc->dev;
8561 struct drm_i915_private *dev_priv = dev->dev_private;
8562 struct drm_atomic_state *state = crtc_state->base.state;
8563 struct drm_connector *connector;
8564 struct drm_connector_state *connector_state;
8565 struct intel_encoder *encoder;
8566 int num_connectors = 0, i;
8567 bool is_lvds = false;
8568
8569 for_each_connector_in_state(state, connector, connector_state, i) {
8570 if (connector_state->crtc != crtc_state->base.crtc)
8571 continue;
8572
8573 encoder = to_intel_encoder(connector_state->best_encoder);
8574
8575 switch (encoder->type) {
8576 case INTEL_OUTPUT_LVDS:
8577 is_lvds = true;
8578 break;
8579 default:
8580 break;
8581 }
8582 num_connectors++;
8583 }
8584
8585 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8586 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8587 dev_priv->vbt.lvds_ssc_freq);
8588 return dev_priv->vbt.lvds_ssc_freq;
8589 }
8590
8591 return 120000;
8592 }
8593
8594 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8595 {
8596 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8598 int pipe = intel_crtc->pipe;
8599 uint32_t val;
8600
8601 val = 0;
8602
8603 switch (intel_crtc->config->pipe_bpp) {
8604 case 18:
8605 val |= PIPECONF_6BPC;
8606 break;
8607 case 24:
8608 val |= PIPECONF_8BPC;
8609 break;
8610 case 30:
8611 val |= PIPECONF_10BPC;
8612 break;
8613 case 36:
8614 val |= PIPECONF_12BPC;
8615 break;
8616 default:
8617 /* Case prevented by intel_choose_pipe_bpp_dither. */
8618 BUG();
8619 }
8620
8621 if (intel_crtc->config->dither)
8622 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8623
8624 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8625 val |= PIPECONF_INTERLACED_ILK;
8626 else
8627 val |= PIPECONF_PROGRESSIVE;
8628
8629 if (intel_crtc->config->limited_color_range)
8630 val |= PIPECONF_COLOR_RANGE_SELECT;
8631
8632 I915_WRITE(PIPECONF(pipe), val);
8633 POSTING_READ(PIPECONF(pipe));
8634 }
8635
8636 /*
8637 * Set up the pipe CSC unit.
8638 *
8639 * Currently only full range RGB to limited range RGB conversion
8640 * is supported, but eventually this should handle various
8641 * RGB<->YCbCr scenarios as well.
8642 */
8643 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8644 {
8645 struct drm_device *dev = crtc->dev;
8646 struct drm_i915_private *dev_priv = dev->dev_private;
8647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8648 int pipe = intel_crtc->pipe;
8649 uint16_t coeff = 0x7800; /* 1.0 */
8650
8651 /*
8652 * TODO: Check what kind of values actually come out of the pipe
8653 * with these coeff/postoff values and adjust to get the best
8654 * accuracy. Perhaps we even need to take the bpc value into
8655 * consideration.
8656 */
8657
8658 if (intel_crtc->config->limited_color_range)
8659 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8660
8661 /*
8662 * GY/GU and RY/RU should be the other way around according
8663 * to BSpec, but reality doesn't agree. Just set them up in
8664 * a way that results in the correct picture.
8665 */
8666 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8667 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8668
8669 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8670 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8671
8672 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8673 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8674
8675 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8676 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8677 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8678
8679 if (INTEL_INFO(dev)->gen > 6) {
8680 uint16_t postoff = 0;
8681
8682 if (intel_crtc->config->limited_color_range)
8683 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8684
8685 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8686 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8687 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8688
8689 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8690 } else {
8691 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8692
8693 if (intel_crtc->config->limited_color_range)
8694 mode |= CSC_BLACK_SCREEN_OFFSET;
8695
8696 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8697 }
8698 }
8699
8700 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8701 {
8702 struct drm_device *dev = crtc->dev;
8703 struct drm_i915_private *dev_priv = dev->dev_private;
8704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8705 enum pipe pipe = intel_crtc->pipe;
8706 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8707 uint32_t val;
8708
8709 val = 0;
8710
8711 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8712 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8713
8714 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8715 val |= PIPECONF_INTERLACED_ILK;
8716 else
8717 val |= PIPECONF_PROGRESSIVE;
8718
8719 I915_WRITE(PIPECONF(cpu_transcoder), val);
8720 POSTING_READ(PIPECONF(cpu_transcoder));
8721
8722 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8723 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8724
8725 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8726 val = 0;
8727
8728 switch (intel_crtc->config->pipe_bpp) {
8729 case 18:
8730 val |= PIPEMISC_DITHER_6_BPC;
8731 break;
8732 case 24:
8733 val |= PIPEMISC_DITHER_8_BPC;
8734 break;
8735 case 30:
8736 val |= PIPEMISC_DITHER_10_BPC;
8737 break;
8738 case 36:
8739 val |= PIPEMISC_DITHER_12_BPC;
8740 break;
8741 default:
8742 /* Case prevented by pipe_config_set_bpp. */
8743 BUG();
8744 }
8745
8746 if (intel_crtc->config->dither)
8747 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8748
8749 I915_WRITE(PIPEMISC(pipe), val);
8750 }
8751 }
8752
8753 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8754 struct intel_crtc_state *crtc_state,
8755 intel_clock_t *clock,
8756 bool *has_reduced_clock,
8757 intel_clock_t *reduced_clock)
8758 {
8759 struct drm_device *dev = crtc->dev;
8760 struct drm_i915_private *dev_priv = dev->dev_private;
8761 int refclk;
8762 const intel_limit_t *limit;
8763 bool ret;
8764
8765 refclk = ironlake_get_refclk(crtc_state);
8766
8767 /*
8768 * Returns a set of divisors for the desired target clock with the given
8769 * refclk, or FALSE. The returned values represent the clock equation:
8770 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8771 */
8772 limit = intel_limit(crtc_state, refclk);
8773 ret = dev_priv->display.find_dpll(limit, crtc_state,
8774 crtc_state->port_clock,
8775 refclk, NULL, clock);
8776 if (!ret)
8777 return false;
8778
8779 return true;
8780 }
8781
8782 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8783 {
8784 /*
8785 * Account for spread spectrum to avoid
8786 * oversubscribing the link. Max center spread
8787 * is 2.5%; use 5% for safety's sake.
8788 */
8789 u32 bps = target_clock * bpp * 21 / 20;
8790 return DIV_ROUND_UP(bps, link_bw * 8);
8791 }
8792
8793 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8794 {
8795 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8796 }
8797
8798 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8799 struct intel_crtc_state *crtc_state,
8800 u32 *fp,
8801 intel_clock_t *reduced_clock, u32 *fp2)
8802 {
8803 struct drm_crtc *crtc = &intel_crtc->base;
8804 struct drm_device *dev = crtc->dev;
8805 struct drm_i915_private *dev_priv = dev->dev_private;
8806 struct drm_atomic_state *state = crtc_state->base.state;
8807 struct drm_connector *connector;
8808 struct drm_connector_state *connector_state;
8809 struct intel_encoder *encoder;
8810 uint32_t dpll;
8811 int factor, num_connectors = 0, i;
8812 bool is_lvds = false, is_sdvo = false;
8813
8814 for_each_connector_in_state(state, connector, connector_state, i) {
8815 if (connector_state->crtc != crtc_state->base.crtc)
8816 continue;
8817
8818 encoder = to_intel_encoder(connector_state->best_encoder);
8819
8820 switch (encoder->type) {
8821 case INTEL_OUTPUT_LVDS:
8822 is_lvds = true;
8823 break;
8824 case INTEL_OUTPUT_SDVO:
8825 case INTEL_OUTPUT_HDMI:
8826 is_sdvo = true;
8827 break;
8828 default:
8829 break;
8830 }
8831
8832 num_connectors++;
8833 }
8834
8835 /* Enable autotuning of the PLL clock (if permissible) */
8836 factor = 21;
8837 if (is_lvds) {
8838 if ((intel_panel_use_ssc(dev_priv) &&
8839 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8840 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8841 factor = 25;
8842 } else if (crtc_state->sdvo_tv_clock)
8843 factor = 20;
8844
8845 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8846 *fp |= FP_CB_TUNE;
8847
8848 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8849 *fp2 |= FP_CB_TUNE;
8850
8851 dpll = 0;
8852
8853 if (is_lvds)
8854 dpll |= DPLLB_MODE_LVDS;
8855 else
8856 dpll |= DPLLB_MODE_DAC_SERIAL;
8857
8858 dpll |= (crtc_state->pixel_multiplier - 1)
8859 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8860
8861 if (is_sdvo)
8862 dpll |= DPLL_SDVO_HIGH_SPEED;
8863 if (crtc_state->has_dp_encoder)
8864 dpll |= DPLL_SDVO_HIGH_SPEED;
8865
8866 /* compute bitmask from p1 value */
8867 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8868 /* also FPA1 */
8869 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8870
8871 switch (crtc_state->dpll.p2) {
8872 case 5:
8873 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8874 break;
8875 case 7:
8876 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8877 break;
8878 case 10:
8879 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8880 break;
8881 case 14:
8882 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8883 break;
8884 }
8885
8886 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8887 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8888 else
8889 dpll |= PLL_REF_INPUT_DREFCLK;
8890
8891 return dpll | DPLL_VCO_ENABLE;
8892 }
8893
8894 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8895 struct intel_crtc_state *crtc_state)
8896 {
8897 struct drm_device *dev = crtc->base.dev;
8898 intel_clock_t clock, reduced_clock;
8899 u32 dpll = 0, fp = 0, fp2 = 0;
8900 bool ok, has_reduced_clock = false;
8901 bool is_lvds = false;
8902 struct intel_shared_dpll *pll;
8903
8904 memset(&crtc_state->dpll_hw_state, 0,
8905 sizeof(crtc_state->dpll_hw_state));
8906
8907 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8908
8909 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8910 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8911
8912 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8913 &has_reduced_clock, &reduced_clock);
8914 if (!ok && !crtc_state->clock_set) {
8915 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8916 return -EINVAL;
8917 }
8918 /* Compat-code for transition, will disappear. */
8919 if (!crtc_state->clock_set) {
8920 crtc_state->dpll.n = clock.n;
8921 crtc_state->dpll.m1 = clock.m1;
8922 crtc_state->dpll.m2 = clock.m2;
8923 crtc_state->dpll.p1 = clock.p1;
8924 crtc_state->dpll.p2 = clock.p2;
8925 }
8926
8927 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8928 if (crtc_state->has_pch_encoder) {
8929 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8930 if (has_reduced_clock)
8931 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8932
8933 dpll = ironlake_compute_dpll(crtc, crtc_state,
8934 &fp, &reduced_clock,
8935 has_reduced_clock ? &fp2 : NULL);
8936
8937 crtc_state->dpll_hw_state.dpll = dpll;
8938 crtc_state->dpll_hw_state.fp0 = fp;
8939 if (has_reduced_clock)
8940 crtc_state->dpll_hw_state.fp1 = fp2;
8941 else
8942 crtc_state->dpll_hw_state.fp1 = fp;
8943
8944 pll = intel_get_shared_dpll(crtc, crtc_state);
8945 if (pll == NULL) {
8946 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8947 pipe_name(crtc->pipe));
8948 return -EINVAL;
8949 }
8950 }
8951
8952 if (is_lvds && has_reduced_clock)
8953 crtc->lowfreq_avail = true;
8954 else
8955 crtc->lowfreq_avail = false;
8956
8957 return 0;
8958 }
8959
8960 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8961 struct intel_link_m_n *m_n)
8962 {
8963 struct drm_device *dev = crtc->base.dev;
8964 struct drm_i915_private *dev_priv = dev->dev_private;
8965 enum pipe pipe = crtc->pipe;
8966
8967 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8968 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8969 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8970 & ~TU_SIZE_MASK;
8971 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8972 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8973 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8974 }
8975
8976 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8977 enum transcoder transcoder,
8978 struct intel_link_m_n *m_n,
8979 struct intel_link_m_n *m2_n2)
8980 {
8981 struct drm_device *dev = crtc->base.dev;
8982 struct drm_i915_private *dev_priv = dev->dev_private;
8983 enum pipe pipe = crtc->pipe;
8984
8985 if (INTEL_INFO(dev)->gen >= 5) {
8986 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8987 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8988 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8989 & ~TU_SIZE_MASK;
8990 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8991 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8992 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8993 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8994 * gen < 8) and if DRRS is supported (to make sure the
8995 * registers are not unnecessarily read).
8996 */
8997 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8998 crtc->config->has_drrs) {
8999 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9000 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9001 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9002 & ~TU_SIZE_MASK;
9003 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9004 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9005 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9006 }
9007 } else {
9008 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9009 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9010 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9011 & ~TU_SIZE_MASK;
9012 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9013 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9014 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9015 }
9016 }
9017
9018 void intel_dp_get_m_n(struct intel_crtc *crtc,
9019 struct intel_crtc_state *pipe_config)
9020 {
9021 if (pipe_config->has_pch_encoder)
9022 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9023 else
9024 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9025 &pipe_config->dp_m_n,
9026 &pipe_config->dp_m2_n2);
9027 }
9028
9029 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9030 struct intel_crtc_state *pipe_config)
9031 {
9032 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9033 &pipe_config->fdi_m_n, NULL);
9034 }
9035
9036 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9037 struct intel_crtc_state *pipe_config)
9038 {
9039 struct drm_device *dev = crtc->base.dev;
9040 struct drm_i915_private *dev_priv = dev->dev_private;
9041 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9042 uint32_t ps_ctrl = 0;
9043 int id = -1;
9044 int i;
9045
9046 /* find scaler attached to this pipe */
9047 for (i = 0; i < crtc->num_scalers; i++) {
9048 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9049 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9050 id = i;
9051 pipe_config->pch_pfit.enabled = true;
9052 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9053 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9054 break;
9055 }
9056 }
9057
9058 scaler_state->scaler_id = id;
9059 if (id >= 0) {
9060 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9061 } else {
9062 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9063 }
9064 }
9065
9066 static void
9067 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9068 struct intel_initial_plane_config *plane_config)
9069 {
9070 struct drm_device *dev = crtc->base.dev;
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9072 u32 val, base, offset, stride_mult, tiling;
9073 int pipe = crtc->pipe;
9074 int fourcc, pixel_format;
9075 unsigned int aligned_height;
9076 struct drm_framebuffer *fb;
9077 struct intel_framebuffer *intel_fb;
9078
9079 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9080 if (!intel_fb) {
9081 DRM_DEBUG_KMS("failed to alloc fb\n");
9082 return;
9083 }
9084
9085 fb = &intel_fb->base;
9086
9087 val = I915_READ(PLANE_CTL(pipe, 0));
9088 if (!(val & PLANE_CTL_ENABLE))
9089 goto error;
9090
9091 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9092 fourcc = skl_format_to_fourcc(pixel_format,
9093 val & PLANE_CTL_ORDER_RGBX,
9094 val & PLANE_CTL_ALPHA_MASK);
9095 fb->pixel_format = fourcc;
9096 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9097
9098 tiling = val & PLANE_CTL_TILED_MASK;
9099 switch (tiling) {
9100 case PLANE_CTL_TILED_LINEAR:
9101 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9102 break;
9103 case PLANE_CTL_TILED_X:
9104 plane_config->tiling = I915_TILING_X;
9105 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9106 break;
9107 case PLANE_CTL_TILED_Y:
9108 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9109 break;
9110 case PLANE_CTL_TILED_YF:
9111 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9112 break;
9113 default:
9114 MISSING_CASE(tiling);
9115 goto error;
9116 }
9117
9118 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9119 plane_config->base = base;
9120
9121 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9122
9123 val = I915_READ(PLANE_SIZE(pipe, 0));
9124 fb->height = ((val >> 16) & 0xfff) + 1;
9125 fb->width = ((val >> 0) & 0x1fff) + 1;
9126
9127 val = I915_READ(PLANE_STRIDE(pipe, 0));
9128 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9129 fb->pixel_format);
9130 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9131
9132 aligned_height = intel_fb_align_height(dev, fb->height,
9133 fb->pixel_format,
9134 fb->modifier[0]);
9135
9136 plane_config->size = fb->pitches[0] * aligned_height;
9137
9138 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9139 pipe_name(pipe), fb->width, fb->height,
9140 fb->bits_per_pixel, base, fb->pitches[0],
9141 plane_config->size);
9142
9143 plane_config->fb = intel_fb;
9144 return;
9145
9146 error:
9147 kfree(fb);
9148 }
9149
9150 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9151 struct intel_crtc_state *pipe_config)
9152 {
9153 struct drm_device *dev = crtc->base.dev;
9154 struct drm_i915_private *dev_priv = dev->dev_private;
9155 uint32_t tmp;
9156
9157 tmp = I915_READ(PF_CTL(crtc->pipe));
9158
9159 if (tmp & PF_ENABLE) {
9160 pipe_config->pch_pfit.enabled = true;
9161 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9162 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9163
9164 /* We currently do not free assignements of panel fitters on
9165 * ivb/hsw (since we don't use the higher upscaling modes which
9166 * differentiates them) so just WARN about this case for now. */
9167 if (IS_GEN7(dev)) {
9168 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9169 PF_PIPE_SEL_IVB(crtc->pipe));
9170 }
9171 }
9172 }
9173
9174 static void
9175 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9176 struct intel_initial_plane_config *plane_config)
9177 {
9178 struct drm_device *dev = crtc->base.dev;
9179 struct drm_i915_private *dev_priv = dev->dev_private;
9180 u32 val, base, offset;
9181 int pipe = crtc->pipe;
9182 int fourcc, pixel_format;
9183 unsigned int aligned_height;
9184 struct drm_framebuffer *fb;
9185 struct intel_framebuffer *intel_fb;
9186
9187 val = I915_READ(DSPCNTR(pipe));
9188 if (!(val & DISPLAY_PLANE_ENABLE))
9189 return;
9190
9191 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9192 if (!intel_fb) {
9193 DRM_DEBUG_KMS("failed to alloc fb\n");
9194 return;
9195 }
9196
9197 fb = &intel_fb->base;
9198
9199 if (INTEL_INFO(dev)->gen >= 4) {
9200 if (val & DISPPLANE_TILED) {
9201 plane_config->tiling = I915_TILING_X;
9202 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9203 }
9204 }
9205
9206 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9207 fourcc = i9xx_format_to_fourcc(pixel_format);
9208 fb->pixel_format = fourcc;
9209 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9210
9211 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9212 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9213 offset = I915_READ(DSPOFFSET(pipe));
9214 } else {
9215 if (plane_config->tiling)
9216 offset = I915_READ(DSPTILEOFF(pipe));
9217 else
9218 offset = I915_READ(DSPLINOFF(pipe));
9219 }
9220 plane_config->base = base;
9221
9222 val = I915_READ(PIPESRC(pipe));
9223 fb->width = ((val >> 16) & 0xfff) + 1;
9224 fb->height = ((val >> 0) & 0xfff) + 1;
9225
9226 val = I915_READ(DSPSTRIDE(pipe));
9227 fb->pitches[0] = val & 0xffffffc0;
9228
9229 aligned_height = intel_fb_align_height(dev, fb->height,
9230 fb->pixel_format,
9231 fb->modifier[0]);
9232
9233 plane_config->size = fb->pitches[0] * aligned_height;
9234
9235 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9236 pipe_name(pipe), fb->width, fb->height,
9237 fb->bits_per_pixel, base, fb->pitches[0],
9238 plane_config->size);
9239
9240 plane_config->fb = intel_fb;
9241 }
9242
9243 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9244 struct intel_crtc_state *pipe_config)
9245 {
9246 struct drm_device *dev = crtc->base.dev;
9247 struct drm_i915_private *dev_priv = dev->dev_private;
9248 uint32_t tmp;
9249
9250 if (!intel_display_power_is_enabled(dev_priv,
9251 POWER_DOMAIN_PIPE(crtc->pipe)))
9252 return false;
9253
9254 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9255 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9256
9257 tmp = I915_READ(PIPECONF(crtc->pipe));
9258 if (!(tmp & PIPECONF_ENABLE))
9259 return false;
9260
9261 switch (tmp & PIPECONF_BPC_MASK) {
9262 case PIPECONF_6BPC:
9263 pipe_config->pipe_bpp = 18;
9264 break;
9265 case PIPECONF_8BPC:
9266 pipe_config->pipe_bpp = 24;
9267 break;
9268 case PIPECONF_10BPC:
9269 pipe_config->pipe_bpp = 30;
9270 break;
9271 case PIPECONF_12BPC:
9272 pipe_config->pipe_bpp = 36;
9273 break;
9274 default:
9275 break;
9276 }
9277
9278 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9279 pipe_config->limited_color_range = true;
9280
9281 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9282 struct intel_shared_dpll *pll;
9283
9284 pipe_config->has_pch_encoder = true;
9285
9286 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9287 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9288 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9289
9290 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9291
9292 if (HAS_PCH_IBX(dev_priv->dev)) {
9293 pipe_config->shared_dpll =
9294 (enum intel_dpll_id) crtc->pipe;
9295 } else {
9296 tmp = I915_READ(PCH_DPLL_SEL);
9297 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9298 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9299 else
9300 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9301 }
9302
9303 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9304
9305 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9306 &pipe_config->dpll_hw_state));
9307
9308 tmp = pipe_config->dpll_hw_state.dpll;
9309 pipe_config->pixel_multiplier =
9310 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9311 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9312
9313 ironlake_pch_clock_get(crtc, pipe_config);
9314 } else {
9315 pipe_config->pixel_multiplier = 1;
9316 }
9317
9318 intel_get_pipe_timings(crtc, pipe_config);
9319
9320 ironlake_get_pfit_config(crtc, pipe_config);
9321
9322 return true;
9323 }
9324
9325 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9326 {
9327 struct drm_device *dev = dev_priv->dev;
9328 struct intel_crtc *crtc;
9329
9330 for_each_intel_crtc(dev, crtc)
9331 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9332 pipe_name(crtc->pipe));
9333
9334 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9335 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9336 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9337 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9338 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9339 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9340 "CPU PWM1 enabled\n");
9341 if (IS_HASWELL(dev))
9342 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9343 "CPU PWM2 enabled\n");
9344 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9345 "PCH PWM1 enabled\n");
9346 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9347 "Utility pin enabled\n");
9348 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9349
9350 /*
9351 * In theory we can still leave IRQs enabled, as long as only the HPD
9352 * interrupts remain enabled. We used to check for that, but since it's
9353 * gen-specific and since we only disable LCPLL after we fully disable
9354 * the interrupts, the check below should be enough.
9355 */
9356 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9357 }
9358
9359 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9360 {
9361 struct drm_device *dev = dev_priv->dev;
9362
9363 if (IS_HASWELL(dev))
9364 return I915_READ(D_COMP_HSW);
9365 else
9366 return I915_READ(D_COMP_BDW);
9367 }
9368
9369 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9370 {
9371 struct drm_device *dev = dev_priv->dev;
9372
9373 if (IS_HASWELL(dev)) {
9374 mutex_lock(&dev_priv->rps.hw_lock);
9375 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9376 val))
9377 DRM_ERROR("Failed to write to D_COMP\n");
9378 mutex_unlock(&dev_priv->rps.hw_lock);
9379 } else {
9380 I915_WRITE(D_COMP_BDW, val);
9381 POSTING_READ(D_COMP_BDW);
9382 }
9383 }
9384
9385 /*
9386 * This function implements pieces of two sequences from BSpec:
9387 * - Sequence for display software to disable LCPLL
9388 * - Sequence for display software to allow package C8+
9389 * The steps implemented here are just the steps that actually touch the LCPLL
9390 * register. Callers should take care of disabling all the display engine
9391 * functions, doing the mode unset, fixing interrupts, etc.
9392 */
9393 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9394 bool switch_to_fclk, bool allow_power_down)
9395 {
9396 uint32_t val;
9397
9398 assert_can_disable_lcpll(dev_priv);
9399
9400 val = I915_READ(LCPLL_CTL);
9401
9402 if (switch_to_fclk) {
9403 val |= LCPLL_CD_SOURCE_FCLK;
9404 I915_WRITE(LCPLL_CTL, val);
9405
9406 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9407 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9408 DRM_ERROR("Switching to FCLK failed\n");
9409
9410 val = I915_READ(LCPLL_CTL);
9411 }
9412
9413 val |= LCPLL_PLL_DISABLE;
9414 I915_WRITE(LCPLL_CTL, val);
9415 POSTING_READ(LCPLL_CTL);
9416
9417 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9418 DRM_ERROR("LCPLL still locked\n");
9419
9420 val = hsw_read_dcomp(dev_priv);
9421 val |= D_COMP_COMP_DISABLE;
9422 hsw_write_dcomp(dev_priv, val);
9423 ndelay(100);
9424
9425 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9426 1))
9427 DRM_ERROR("D_COMP RCOMP still in progress\n");
9428
9429 if (allow_power_down) {
9430 val = I915_READ(LCPLL_CTL);
9431 val |= LCPLL_POWER_DOWN_ALLOW;
9432 I915_WRITE(LCPLL_CTL, val);
9433 POSTING_READ(LCPLL_CTL);
9434 }
9435 }
9436
9437 /*
9438 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9439 * source.
9440 */
9441 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9442 {
9443 uint32_t val;
9444
9445 val = I915_READ(LCPLL_CTL);
9446
9447 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9448 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9449 return;
9450
9451 /*
9452 * Make sure we're not on PC8 state before disabling PC8, otherwise
9453 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9454 */
9455 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9456
9457 if (val & LCPLL_POWER_DOWN_ALLOW) {
9458 val &= ~LCPLL_POWER_DOWN_ALLOW;
9459 I915_WRITE(LCPLL_CTL, val);
9460 POSTING_READ(LCPLL_CTL);
9461 }
9462
9463 val = hsw_read_dcomp(dev_priv);
9464 val |= D_COMP_COMP_FORCE;
9465 val &= ~D_COMP_COMP_DISABLE;
9466 hsw_write_dcomp(dev_priv, val);
9467
9468 val = I915_READ(LCPLL_CTL);
9469 val &= ~LCPLL_PLL_DISABLE;
9470 I915_WRITE(LCPLL_CTL, val);
9471
9472 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9473 DRM_ERROR("LCPLL not locked yet\n");
9474
9475 if (val & LCPLL_CD_SOURCE_FCLK) {
9476 val = I915_READ(LCPLL_CTL);
9477 val &= ~LCPLL_CD_SOURCE_FCLK;
9478 I915_WRITE(LCPLL_CTL, val);
9479
9480 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9481 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9482 DRM_ERROR("Switching back to LCPLL failed\n");
9483 }
9484
9485 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9486 intel_update_cdclk(dev_priv->dev);
9487 }
9488
9489 /*
9490 * Package states C8 and deeper are really deep PC states that can only be
9491 * reached when all the devices on the system allow it, so even if the graphics
9492 * device allows PC8+, it doesn't mean the system will actually get to these
9493 * states. Our driver only allows PC8+ when going into runtime PM.
9494 *
9495 * The requirements for PC8+ are that all the outputs are disabled, the power
9496 * well is disabled and most interrupts are disabled, and these are also
9497 * requirements for runtime PM. When these conditions are met, we manually do
9498 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9499 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9500 * hang the machine.
9501 *
9502 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9503 * the state of some registers, so when we come back from PC8+ we need to
9504 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9505 * need to take care of the registers kept by RC6. Notice that this happens even
9506 * if we don't put the device in PCI D3 state (which is what currently happens
9507 * because of the runtime PM support).
9508 *
9509 * For more, read "Display Sequences for Package C8" on the hardware
9510 * documentation.
9511 */
9512 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9513 {
9514 struct drm_device *dev = dev_priv->dev;
9515 uint32_t val;
9516
9517 DRM_DEBUG_KMS("Enabling package C8+\n");
9518
9519 if (HAS_PCH_LPT_LP(dev)) {
9520 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9521 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9522 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9523 }
9524
9525 lpt_disable_clkout_dp(dev);
9526 hsw_disable_lcpll(dev_priv, true, true);
9527 }
9528
9529 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9530 {
9531 struct drm_device *dev = dev_priv->dev;
9532 uint32_t val;
9533
9534 DRM_DEBUG_KMS("Disabling package C8+\n");
9535
9536 hsw_restore_lcpll(dev_priv);
9537 lpt_init_pch_refclk(dev);
9538
9539 if (HAS_PCH_LPT_LP(dev)) {
9540 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9541 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9542 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9543 }
9544
9545 intel_prepare_ddi(dev);
9546 }
9547
9548 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9549 {
9550 struct drm_device *dev = old_state->dev;
9551 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9552
9553 broxton_set_cdclk(dev, req_cdclk);
9554 }
9555
9556 /* compute the max rate for new configuration */
9557 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9558 {
9559 struct intel_crtc *intel_crtc;
9560 struct intel_crtc_state *crtc_state;
9561 int max_pixel_rate = 0;
9562
9563 for_each_intel_crtc(state->dev, intel_crtc) {
9564 int pixel_rate;
9565
9566 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9567 if (IS_ERR(crtc_state))
9568 return PTR_ERR(crtc_state);
9569
9570 if (!crtc_state->base.enable)
9571 continue;
9572
9573 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9574
9575 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9576 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9577 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9578
9579 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9580 }
9581
9582 return max_pixel_rate;
9583 }
9584
9585 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9586 {
9587 struct drm_i915_private *dev_priv = dev->dev_private;
9588 uint32_t val, data;
9589 int ret;
9590
9591 if (WARN((I915_READ(LCPLL_CTL) &
9592 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9593 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9594 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9595 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9596 "trying to change cdclk frequency with cdclk not enabled\n"))
9597 return;
9598
9599 mutex_lock(&dev_priv->rps.hw_lock);
9600 ret = sandybridge_pcode_write(dev_priv,
9601 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9602 mutex_unlock(&dev_priv->rps.hw_lock);
9603 if (ret) {
9604 DRM_ERROR("failed to inform pcode about cdclk change\n");
9605 return;
9606 }
9607
9608 val = I915_READ(LCPLL_CTL);
9609 val |= LCPLL_CD_SOURCE_FCLK;
9610 I915_WRITE(LCPLL_CTL, val);
9611
9612 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9613 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9614 DRM_ERROR("Switching to FCLK failed\n");
9615
9616 val = I915_READ(LCPLL_CTL);
9617 val &= ~LCPLL_CLK_FREQ_MASK;
9618
9619 switch (cdclk) {
9620 case 450000:
9621 val |= LCPLL_CLK_FREQ_450;
9622 data = 0;
9623 break;
9624 case 540000:
9625 val |= LCPLL_CLK_FREQ_54O_BDW;
9626 data = 1;
9627 break;
9628 case 337500:
9629 val |= LCPLL_CLK_FREQ_337_5_BDW;
9630 data = 2;
9631 break;
9632 case 675000:
9633 val |= LCPLL_CLK_FREQ_675_BDW;
9634 data = 3;
9635 break;
9636 default:
9637 WARN(1, "invalid cdclk frequency\n");
9638 return;
9639 }
9640
9641 I915_WRITE(LCPLL_CTL, val);
9642
9643 val = I915_READ(LCPLL_CTL);
9644 val &= ~LCPLL_CD_SOURCE_FCLK;
9645 I915_WRITE(LCPLL_CTL, val);
9646
9647 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9648 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9649 DRM_ERROR("Switching back to LCPLL failed\n");
9650
9651 mutex_lock(&dev_priv->rps.hw_lock);
9652 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9653 mutex_unlock(&dev_priv->rps.hw_lock);
9654
9655 intel_update_cdclk(dev);
9656
9657 WARN(cdclk != dev_priv->cdclk_freq,
9658 "cdclk requested %d kHz but got %d kHz\n",
9659 cdclk, dev_priv->cdclk_freq);
9660 }
9661
9662 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9663 {
9664 struct drm_i915_private *dev_priv = to_i915(state->dev);
9665 int max_pixclk = ilk_max_pixel_rate(state);
9666 int cdclk;
9667
9668 /*
9669 * FIXME should also account for plane ratio
9670 * once 64bpp pixel formats are supported.
9671 */
9672 if (max_pixclk > 540000)
9673 cdclk = 675000;
9674 else if (max_pixclk > 450000)
9675 cdclk = 540000;
9676 else if (max_pixclk > 337500)
9677 cdclk = 450000;
9678 else
9679 cdclk = 337500;
9680
9681 /*
9682 * FIXME move the cdclk caclulation to
9683 * compute_config() so we can fail gracegully.
9684 */
9685 if (cdclk > dev_priv->max_cdclk_freq) {
9686 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9687 cdclk, dev_priv->max_cdclk_freq);
9688 cdclk = dev_priv->max_cdclk_freq;
9689 }
9690
9691 to_intel_atomic_state(state)->cdclk = cdclk;
9692
9693 return 0;
9694 }
9695
9696 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9697 {
9698 struct drm_device *dev = old_state->dev;
9699 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9700
9701 broadwell_set_cdclk(dev, req_cdclk);
9702 }
9703
9704 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9705 struct intel_crtc_state *crtc_state)
9706 {
9707 if (!intel_ddi_pll_select(crtc, crtc_state))
9708 return -EINVAL;
9709
9710 crtc->lowfreq_avail = false;
9711
9712 return 0;
9713 }
9714
9715 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9716 enum port port,
9717 struct intel_crtc_state *pipe_config)
9718 {
9719 switch (port) {
9720 case PORT_A:
9721 pipe_config->ddi_pll_sel = SKL_DPLL0;
9722 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9723 break;
9724 case PORT_B:
9725 pipe_config->ddi_pll_sel = SKL_DPLL1;
9726 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9727 break;
9728 case PORT_C:
9729 pipe_config->ddi_pll_sel = SKL_DPLL2;
9730 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9731 break;
9732 default:
9733 DRM_ERROR("Incorrect port type\n");
9734 }
9735 }
9736
9737 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9738 enum port port,
9739 struct intel_crtc_state *pipe_config)
9740 {
9741 u32 temp, dpll_ctl1;
9742
9743 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9744 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9745
9746 switch (pipe_config->ddi_pll_sel) {
9747 case SKL_DPLL0:
9748 /*
9749 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9750 * of the shared DPLL framework and thus needs to be read out
9751 * separately
9752 */
9753 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9754 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9755 break;
9756 case SKL_DPLL1:
9757 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9758 break;
9759 case SKL_DPLL2:
9760 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9761 break;
9762 case SKL_DPLL3:
9763 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9764 break;
9765 }
9766 }
9767
9768 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9769 enum port port,
9770 struct intel_crtc_state *pipe_config)
9771 {
9772 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9773
9774 switch (pipe_config->ddi_pll_sel) {
9775 case PORT_CLK_SEL_WRPLL1:
9776 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9777 break;
9778 case PORT_CLK_SEL_WRPLL2:
9779 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9780 break;
9781 case PORT_CLK_SEL_SPLL:
9782 pipe_config->shared_dpll = DPLL_ID_SPLL;
9783 }
9784 }
9785
9786 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9787 struct intel_crtc_state *pipe_config)
9788 {
9789 struct drm_device *dev = crtc->base.dev;
9790 struct drm_i915_private *dev_priv = dev->dev_private;
9791 struct intel_shared_dpll *pll;
9792 enum port port;
9793 uint32_t tmp;
9794
9795 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9796
9797 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9798
9799 if (IS_SKYLAKE(dev))
9800 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9801 else if (IS_BROXTON(dev))
9802 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9803 else
9804 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9805
9806 if (pipe_config->shared_dpll >= 0) {
9807 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9808
9809 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9810 &pipe_config->dpll_hw_state));
9811 }
9812
9813 /*
9814 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9815 * DDI E. So just check whether this pipe is wired to DDI E and whether
9816 * the PCH transcoder is on.
9817 */
9818 if (INTEL_INFO(dev)->gen < 9 &&
9819 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9820 pipe_config->has_pch_encoder = true;
9821
9822 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9823 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9824 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9825
9826 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9827 }
9828 }
9829
9830 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9831 struct intel_crtc_state *pipe_config)
9832 {
9833 struct drm_device *dev = crtc->base.dev;
9834 struct drm_i915_private *dev_priv = dev->dev_private;
9835 enum intel_display_power_domain pfit_domain;
9836 uint32_t tmp;
9837
9838 if (!intel_display_power_is_enabled(dev_priv,
9839 POWER_DOMAIN_PIPE(crtc->pipe)))
9840 return false;
9841
9842 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9843 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9844
9845 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9846 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9847 enum pipe trans_edp_pipe;
9848 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9849 default:
9850 WARN(1, "unknown pipe linked to edp transcoder\n");
9851 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9852 case TRANS_DDI_EDP_INPUT_A_ON:
9853 trans_edp_pipe = PIPE_A;
9854 break;
9855 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9856 trans_edp_pipe = PIPE_B;
9857 break;
9858 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9859 trans_edp_pipe = PIPE_C;
9860 break;
9861 }
9862
9863 if (trans_edp_pipe == crtc->pipe)
9864 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9865 }
9866
9867 if (!intel_display_power_is_enabled(dev_priv,
9868 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9869 return false;
9870
9871 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9872 if (!(tmp & PIPECONF_ENABLE))
9873 return false;
9874
9875 haswell_get_ddi_port_state(crtc, pipe_config);
9876
9877 intel_get_pipe_timings(crtc, pipe_config);
9878
9879 if (INTEL_INFO(dev)->gen >= 9) {
9880 skl_init_scalers(dev, crtc, pipe_config);
9881 }
9882
9883 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9884
9885 if (INTEL_INFO(dev)->gen >= 9) {
9886 pipe_config->scaler_state.scaler_id = -1;
9887 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9888 }
9889
9890 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9891 if (INTEL_INFO(dev)->gen >= 9)
9892 skylake_get_pfit_config(crtc, pipe_config);
9893 else
9894 ironlake_get_pfit_config(crtc, pipe_config);
9895 }
9896
9897 if (IS_HASWELL(dev))
9898 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9899 (I915_READ(IPS_CTL) & IPS_ENABLE);
9900
9901 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9902 pipe_config->pixel_multiplier =
9903 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9904 } else {
9905 pipe_config->pixel_multiplier = 1;
9906 }
9907
9908 return true;
9909 }
9910
9911 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9912 {
9913 struct drm_device *dev = crtc->dev;
9914 struct drm_i915_private *dev_priv = dev->dev_private;
9915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9916 uint32_t cntl = 0, size = 0;
9917
9918 if (base) {
9919 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9920 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9921 unsigned int stride = roundup_pow_of_two(width) * 4;
9922
9923 switch (stride) {
9924 default:
9925 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9926 width, stride);
9927 stride = 256;
9928 /* fallthrough */
9929 case 256:
9930 case 512:
9931 case 1024:
9932 case 2048:
9933 break;
9934 }
9935
9936 cntl |= CURSOR_ENABLE |
9937 CURSOR_GAMMA_ENABLE |
9938 CURSOR_FORMAT_ARGB |
9939 CURSOR_STRIDE(stride);
9940
9941 size = (height << 12) | width;
9942 }
9943
9944 if (intel_crtc->cursor_cntl != 0 &&
9945 (intel_crtc->cursor_base != base ||
9946 intel_crtc->cursor_size != size ||
9947 intel_crtc->cursor_cntl != cntl)) {
9948 /* On these chipsets we can only modify the base/size/stride
9949 * whilst the cursor is disabled.
9950 */
9951 I915_WRITE(CURCNTR(PIPE_A), 0);
9952 POSTING_READ(CURCNTR(PIPE_A));
9953 intel_crtc->cursor_cntl = 0;
9954 }
9955
9956 if (intel_crtc->cursor_base != base) {
9957 I915_WRITE(CURBASE(PIPE_A), base);
9958 intel_crtc->cursor_base = base;
9959 }
9960
9961 if (intel_crtc->cursor_size != size) {
9962 I915_WRITE(CURSIZE, size);
9963 intel_crtc->cursor_size = size;
9964 }
9965
9966 if (intel_crtc->cursor_cntl != cntl) {
9967 I915_WRITE(CURCNTR(PIPE_A), cntl);
9968 POSTING_READ(CURCNTR(PIPE_A));
9969 intel_crtc->cursor_cntl = cntl;
9970 }
9971 }
9972
9973 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9974 {
9975 struct drm_device *dev = crtc->dev;
9976 struct drm_i915_private *dev_priv = dev->dev_private;
9977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9978 int pipe = intel_crtc->pipe;
9979 uint32_t cntl;
9980
9981 cntl = 0;
9982 if (base) {
9983 cntl = MCURSOR_GAMMA_ENABLE;
9984 switch (intel_crtc->base.cursor->state->crtc_w) {
9985 case 64:
9986 cntl |= CURSOR_MODE_64_ARGB_AX;
9987 break;
9988 case 128:
9989 cntl |= CURSOR_MODE_128_ARGB_AX;
9990 break;
9991 case 256:
9992 cntl |= CURSOR_MODE_256_ARGB_AX;
9993 break;
9994 default:
9995 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9996 return;
9997 }
9998 cntl |= pipe << 28; /* Connect to correct pipe */
9999
10000 if (HAS_DDI(dev))
10001 cntl |= CURSOR_PIPE_CSC_ENABLE;
10002 }
10003
10004 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10005 cntl |= CURSOR_ROTATE_180;
10006
10007 if (intel_crtc->cursor_cntl != cntl) {
10008 I915_WRITE(CURCNTR(pipe), cntl);
10009 POSTING_READ(CURCNTR(pipe));
10010 intel_crtc->cursor_cntl = cntl;
10011 }
10012
10013 /* and commit changes on next vblank */
10014 I915_WRITE(CURBASE(pipe), base);
10015 POSTING_READ(CURBASE(pipe));
10016
10017 intel_crtc->cursor_base = base;
10018 }
10019
10020 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10021 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10022 bool on)
10023 {
10024 struct drm_device *dev = crtc->dev;
10025 struct drm_i915_private *dev_priv = dev->dev_private;
10026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10027 int pipe = intel_crtc->pipe;
10028 struct drm_plane_state *cursor_state = crtc->cursor->state;
10029 int x = cursor_state->crtc_x;
10030 int y = cursor_state->crtc_y;
10031 u32 base = 0, pos = 0;
10032
10033 if (on)
10034 base = intel_crtc->cursor_addr;
10035
10036 if (x >= intel_crtc->config->pipe_src_w)
10037 base = 0;
10038
10039 if (y >= intel_crtc->config->pipe_src_h)
10040 base = 0;
10041
10042 if (x < 0) {
10043 if (x + cursor_state->crtc_w <= 0)
10044 base = 0;
10045
10046 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10047 x = -x;
10048 }
10049 pos |= x << CURSOR_X_SHIFT;
10050
10051 if (y < 0) {
10052 if (y + cursor_state->crtc_h <= 0)
10053 base = 0;
10054
10055 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10056 y = -y;
10057 }
10058 pos |= y << CURSOR_Y_SHIFT;
10059
10060 if (base == 0 && intel_crtc->cursor_base == 0)
10061 return;
10062
10063 I915_WRITE(CURPOS(pipe), pos);
10064
10065 /* ILK+ do this automagically */
10066 if (HAS_GMCH_DISPLAY(dev) &&
10067 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10068 base += (cursor_state->crtc_h *
10069 cursor_state->crtc_w - 1) * 4;
10070 }
10071
10072 if (IS_845G(dev) || IS_I865G(dev))
10073 i845_update_cursor(crtc, base);
10074 else
10075 i9xx_update_cursor(crtc, base);
10076 }
10077
10078 static bool cursor_size_ok(struct drm_device *dev,
10079 uint32_t width, uint32_t height)
10080 {
10081 if (width == 0 || height == 0)
10082 return false;
10083
10084 /*
10085 * 845g/865g are special in that they are only limited by
10086 * the width of their cursors, the height is arbitrary up to
10087 * the precision of the register. Everything else requires
10088 * square cursors, limited to a few power-of-two sizes.
10089 */
10090 if (IS_845G(dev) || IS_I865G(dev)) {
10091 if ((width & 63) != 0)
10092 return false;
10093
10094 if (width > (IS_845G(dev) ? 64 : 512))
10095 return false;
10096
10097 if (height > 1023)
10098 return false;
10099 } else {
10100 switch (width | height) {
10101 case 256:
10102 case 128:
10103 if (IS_GEN2(dev))
10104 return false;
10105 case 64:
10106 break;
10107 default:
10108 return false;
10109 }
10110 }
10111
10112 return true;
10113 }
10114
10115 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10116 u16 *blue, uint32_t start, uint32_t size)
10117 {
10118 int end = (start + size > 256) ? 256 : start + size, i;
10119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10120
10121 for (i = start; i < end; i++) {
10122 intel_crtc->lut_r[i] = red[i] >> 8;
10123 intel_crtc->lut_g[i] = green[i] >> 8;
10124 intel_crtc->lut_b[i] = blue[i] >> 8;
10125 }
10126
10127 intel_crtc_load_lut(crtc);
10128 }
10129
10130 /* VESA 640x480x72Hz mode to set on the pipe */
10131 static struct drm_display_mode load_detect_mode = {
10132 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10133 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10134 };
10135
10136 struct drm_framebuffer *
10137 __intel_framebuffer_create(struct drm_device *dev,
10138 struct drm_mode_fb_cmd2 *mode_cmd,
10139 struct drm_i915_gem_object *obj)
10140 {
10141 struct intel_framebuffer *intel_fb;
10142 int ret;
10143
10144 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10145 if (!intel_fb) {
10146 drm_gem_object_unreference(&obj->base);
10147 return ERR_PTR(-ENOMEM);
10148 }
10149
10150 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10151 if (ret)
10152 goto err;
10153
10154 return &intel_fb->base;
10155 err:
10156 drm_gem_object_unreference(&obj->base);
10157 kfree(intel_fb);
10158
10159 return ERR_PTR(ret);
10160 }
10161
10162 static struct drm_framebuffer *
10163 intel_framebuffer_create(struct drm_device *dev,
10164 struct drm_mode_fb_cmd2 *mode_cmd,
10165 struct drm_i915_gem_object *obj)
10166 {
10167 struct drm_framebuffer *fb;
10168 int ret;
10169
10170 ret = i915_mutex_lock_interruptible(dev);
10171 if (ret)
10172 return ERR_PTR(ret);
10173 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10174 mutex_unlock(&dev->struct_mutex);
10175
10176 return fb;
10177 }
10178
10179 static u32
10180 intel_framebuffer_pitch_for_width(int width, int bpp)
10181 {
10182 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10183 return ALIGN(pitch, 64);
10184 }
10185
10186 static u32
10187 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10188 {
10189 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10190 return PAGE_ALIGN(pitch * mode->vdisplay);
10191 }
10192
10193 static struct drm_framebuffer *
10194 intel_framebuffer_create_for_mode(struct drm_device *dev,
10195 struct drm_display_mode *mode,
10196 int depth, int bpp)
10197 {
10198 struct drm_i915_gem_object *obj;
10199 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10200
10201 obj = i915_gem_alloc_object(dev,
10202 intel_framebuffer_size_for_mode(mode, bpp));
10203 if (obj == NULL)
10204 return ERR_PTR(-ENOMEM);
10205
10206 mode_cmd.width = mode->hdisplay;
10207 mode_cmd.height = mode->vdisplay;
10208 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10209 bpp);
10210 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10211
10212 return intel_framebuffer_create(dev, &mode_cmd, obj);
10213 }
10214
10215 static struct drm_framebuffer *
10216 mode_fits_in_fbdev(struct drm_device *dev,
10217 struct drm_display_mode *mode)
10218 {
10219 #ifdef CONFIG_DRM_FBDEV_EMULATION
10220 struct drm_i915_private *dev_priv = dev->dev_private;
10221 struct drm_i915_gem_object *obj;
10222 struct drm_framebuffer *fb;
10223
10224 if (!dev_priv->fbdev)
10225 return NULL;
10226
10227 if (!dev_priv->fbdev->fb)
10228 return NULL;
10229
10230 obj = dev_priv->fbdev->fb->obj;
10231 BUG_ON(!obj);
10232
10233 fb = &dev_priv->fbdev->fb->base;
10234 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10235 fb->bits_per_pixel))
10236 return NULL;
10237
10238 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10239 return NULL;
10240
10241 return fb;
10242 #else
10243 return NULL;
10244 #endif
10245 }
10246
10247 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10248 struct drm_crtc *crtc,
10249 struct drm_display_mode *mode,
10250 struct drm_framebuffer *fb,
10251 int x, int y)
10252 {
10253 struct drm_plane_state *plane_state;
10254 int hdisplay, vdisplay;
10255 int ret;
10256
10257 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10258 if (IS_ERR(plane_state))
10259 return PTR_ERR(plane_state);
10260
10261 if (mode)
10262 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10263 else
10264 hdisplay = vdisplay = 0;
10265
10266 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10267 if (ret)
10268 return ret;
10269 drm_atomic_set_fb_for_plane(plane_state, fb);
10270 plane_state->crtc_x = 0;
10271 plane_state->crtc_y = 0;
10272 plane_state->crtc_w = hdisplay;
10273 plane_state->crtc_h = vdisplay;
10274 plane_state->src_x = x << 16;
10275 plane_state->src_y = y << 16;
10276 plane_state->src_w = hdisplay << 16;
10277 plane_state->src_h = vdisplay << 16;
10278
10279 return 0;
10280 }
10281
10282 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10283 struct drm_display_mode *mode,
10284 struct intel_load_detect_pipe *old,
10285 struct drm_modeset_acquire_ctx *ctx)
10286 {
10287 struct intel_crtc *intel_crtc;
10288 struct intel_encoder *intel_encoder =
10289 intel_attached_encoder(connector);
10290 struct drm_crtc *possible_crtc;
10291 struct drm_encoder *encoder = &intel_encoder->base;
10292 struct drm_crtc *crtc = NULL;
10293 struct drm_device *dev = encoder->dev;
10294 struct drm_framebuffer *fb;
10295 struct drm_mode_config *config = &dev->mode_config;
10296 struct drm_atomic_state *state = NULL;
10297 struct drm_connector_state *connector_state;
10298 struct intel_crtc_state *crtc_state;
10299 int ret, i = -1;
10300
10301 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10302 connector->base.id, connector->name,
10303 encoder->base.id, encoder->name);
10304
10305 retry:
10306 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10307 if (ret)
10308 goto fail;
10309
10310 /*
10311 * Algorithm gets a little messy:
10312 *
10313 * - if the connector already has an assigned crtc, use it (but make
10314 * sure it's on first)
10315 *
10316 * - try to find the first unused crtc that can drive this connector,
10317 * and use that if we find one
10318 */
10319
10320 /* See if we already have a CRTC for this connector */
10321 if (encoder->crtc) {
10322 crtc = encoder->crtc;
10323
10324 ret = drm_modeset_lock(&crtc->mutex, ctx);
10325 if (ret)
10326 goto fail;
10327 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10328 if (ret)
10329 goto fail;
10330
10331 old->dpms_mode = connector->dpms;
10332 old->load_detect_temp = false;
10333
10334 /* Make sure the crtc and connector are running */
10335 if (connector->dpms != DRM_MODE_DPMS_ON)
10336 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10337
10338 return true;
10339 }
10340
10341 /* Find an unused one (if possible) */
10342 for_each_crtc(dev, possible_crtc) {
10343 i++;
10344 if (!(encoder->possible_crtcs & (1 << i)))
10345 continue;
10346 if (possible_crtc->state->enable)
10347 continue;
10348
10349 crtc = possible_crtc;
10350 break;
10351 }
10352
10353 /*
10354 * If we didn't find an unused CRTC, don't use any.
10355 */
10356 if (!crtc) {
10357 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10358 goto fail;
10359 }
10360
10361 ret = drm_modeset_lock(&crtc->mutex, ctx);
10362 if (ret)
10363 goto fail;
10364 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10365 if (ret)
10366 goto fail;
10367
10368 intel_crtc = to_intel_crtc(crtc);
10369 old->dpms_mode = connector->dpms;
10370 old->load_detect_temp = true;
10371 old->release_fb = NULL;
10372
10373 state = drm_atomic_state_alloc(dev);
10374 if (!state)
10375 return false;
10376
10377 state->acquire_ctx = ctx;
10378
10379 connector_state = drm_atomic_get_connector_state(state, connector);
10380 if (IS_ERR(connector_state)) {
10381 ret = PTR_ERR(connector_state);
10382 goto fail;
10383 }
10384
10385 connector_state->crtc = crtc;
10386 connector_state->best_encoder = &intel_encoder->base;
10387
10388 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10389 if (IS_ERR(crtc_state)) {
10390 ret = PTR_ERR(crtc_state);
10391 goto fail;
10392 }
10393
10394 crtc_state->base.active = crtc_state->base.enable = true;
10395
10396 if (!mode)
10397 mode = &load_detect_mode;
10398
10399 /* We need a framebuffer large enough to accommodate all accesses
10400 * that the plane may generate whilst we perform load detection.
10401 * We can not rely on the fbcon either being present (we get called
10402 * during its initialisation to detect all boot displays, or it may
10403 * not even exist) or that it is large enough to satisfy the
10404 * requested mode.
10405 */
10406 fb = mode_fits_in_fbdev(dev, mode);
10407 if (fb == NULL) {
10408 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10409 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10410 old->release_fb = fb;
10411 } else
10412 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10413 if (IS_ERR(fb)) {
10414 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10415 goto fail;
10416 }
10417
10418 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10419 if (ret)
10420 goto fail;
10421
10422 drm_mode_copy(&crtc_state->base.mode, mode);
10423
10424 if (drm_atomic_commit(state)) {
10425 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10426 if (old->release_fb)
10427 old->release_fb->funcs->destroy(old->release_fb);
10428 goto fail;
10429 }
10430 crtc->primary->crtc = crtc;
10431
10432 /* let the connector get through one full cycle before testing */
10433 intel_wait_for_vblank(dev, intel_crtc->pipe);
10434 return true;
10435
10436 fail:
10437 drm_atomic_state_free(state);
10438 state = NULL;
10439
10440 if (ret == -EDEADLK) {
10441 drm_modeset_backoff(ctx);
10442 goto retry;
10443 }
10444
10445 return false;
10446 }
10447
10448 void intel_release_load_detect_pipe(struct drm_connector *connector,
10449 struct intel_load_detect_pipe *old,
10450 struct drm_modeset_acquire_ctx *ctx)
10451 {
10452 struct drm_device *dev = connector->dev;
10453 struct intel_encoder *intel_encoder =
10454 intel_attached_encoder(connector);
10455 struct drm_encoder *encoder = &intel_encoder->base;
10456 struct drm_crtc *crtc = encoder->crtc;
10457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10458 struct drm_atomic_state *state;
10459 struct drm_connector_state *connector_state;
10460 struct intel_crtc_state *crtc_state;
10461 int ret;
10462
10463 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10464 connector->base.id, connector->name,
10465 encoder->base.id, encoder->name);
10466
10467 if (old->load_detect_temp) {
10468 state = drm_atomic_state_alloc(dev);
10469 if (!state)
10470 goto fail;
10471
10472 state->acquire_ctx = ctx;
10473
10474 connector_state = drm_atomic_get_connector_state(state, connector);
10475 if (IS_ERR(connector_state))
10476 goto fail;
10477
10478 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10479 if (IS_ERR(crtc_state))
10480 goto fail;
10481
10482 connector_state->best_encoder = NULL;
10483 connector_state->crtc = NULL;
10484
10485 crtc_state->base.enable = crtc_state->base.active = false;
10486
10487 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10488 0, 0);
10489 if (ret)
10490 goto fail;
10491
10492 ret = drm_atomic_commit(state);
10493 if (ret)
10494 goto fail;
10495
10496 if (old->release_fb) {
10497 drm_framebuffer_unregister_private(old->release_fb);
10498 drm_framebuffer_unreference(old->release_fb);
10499 }
10500
10501 return;
10502 }
10503
10504 /* Switch crtc and encoder back off if necessary */
10505 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10506 connector->funcs->dpms(connector, old->dpms_mode);
10507
10508 return;
10509 fail:
10510 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10511 drm_atomic_state_free(state);
10512 }
10513
10514 static int i9xx_pll_refclk(struct drm_device *dev,
10515 const struct intel_crtc_state *pipe_config)
10516 {
10517 struct drm_i915_private *dev_priv = dev->dev_private;
10518 u32 dpll = pipe_config->dpll_hw_state.dpll;
10519
10520 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10521 return dev_priv->vbt.lvds_ssc_freq;
10522 else if (HAS_PCH_SPLIT(dev))
10523 return 120000;
10524 else if (!IS_GEN2(dev))
10525 return 96000;
10526 else
10527 return 48000;
10528 }
10529
10530 /* Returns the clock of the currently programmed mode of the given pipe. */
10531 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10532 struct intel_crtc_state *pipe_config)
10533 {
10534 struct drm_device *dev = crtc->base.dev;
10535 struct drm_i915_private *dev_priv = dev->dev_private;
10536 int pipe = pipe_config->cpu_transcoder;
10537 u32 dpll = pipe_config->dpll_hw_state.dpll;
10538 u32 fp;
10539 intel_clock_t clock;
10540 int port_clock;
10541 int refclk = i9xx_pll_refclk(dev, pipe_config);
10542
10543 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10544 fp = pipe_config->dpll_hw_state.fp0;
10545 else
10546 fp = pipe_config->dpll_hw_state.fp1;
10547
10548 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10549 if (IS_PINEVIEW(dev)) {
10550 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10551 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10552 } else {
10553 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10554 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10555 }
10556
10557 if (!IS_GEN2(dev)) {
10558 if (IS_PINEVIEW(dev))
10559 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10560 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10561 else
10562 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10563 DPLL_FPA01_P1_POST_DIV_SHIFT);
10564
10565 switch (dpll & DPLL_MODE_MASK) {
10566 case DPLLB_MODE_DAC_SERIAL:
10567 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10568 5 : 10;
10569 break;
10570 case DPLLB_MODE_LVDS:
10571 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10572 7 : 14;
10573 break;
10574 default:
10575 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10576 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10577 return;
10578 }
10579
10580 if (IS_PINEVIEW(dev))
10581 port_clock = pnv_calc_dpll_params(refclk, &clock);
10582 else
10583 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10584 } else {
10585 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10586 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10587
10588 if (is_lvds) {
10589 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10590 DPLL_FPA01_P1_POST_DIV_SHIFT);
10591
10592 if (lvds & LVDS_CLKB_POWER_UP)
10593 clock.p2 = 7;
10594 else
10595 clock.p2 = 14;
10596 } else {
10597 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10598 clock.p1 = 2;
10599 else {
10600 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10601 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10602 }
10603 if (dpll & PLL_P2_DIVIDE_BY_4)
10604 clock.p2 = 4;
10605 else
10606 clock.p2 = 2;
10607 }
10608
10609 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10610 }
10611
10612 /*
10613 * This value includes pixel_multiplier. We will use
10614 * port_clock to compute adjusted_mode.crtc_clock in the
10615 * encoder's get_config() function.
10616 */
10617 pipe_config->port_clock = port_clock;
10618 }
10619
10620 int intel_dotclock_calculate(int link_freq,
10621 const struct intel_link_m_n *m_n)
10622 {
10623 /*
10624 * The calculation for the data clock is:
10625 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10626 * But we want to avoid losing precison if possible, so:
10627 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10628 *
10629 * and the link clock is simpler:
10630 * link_clock = (m * link_clock) / n
10631 */
10632
10633 if (!m_n->link_n)
10634 return 0;
10635
10636 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10637 }
10638
10639 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10640 struct intel_crtc_state *pipe_config)
10641 {
10642 struct drm_device *dev = crtc->base.dev;
10643
10644 /* read out port_clock from the DPLL */
10645 i9xx_crtc_clock_get(crtc, pipe_config);
10646
10647 /*
10648 * This value does not include pixel_multiplier.
10649 * We will check that port_clock and adjusted_mode.crtc_clock
10650 * agree once we know their relationship in the encoder's
10651 * get_config() function.
10652 */
10653 pipe_config->base.adjusted_mode.crtc_clock =
10654 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10655 &pipe_config->fdi_m_n);
10656 }
10657
10658 /** Returns the currently programmed mode of the given pipe. */
10659 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10660 struct drm_crtc *crtc)
10661 {
10662 struct drm_i915_private *dev_priv = dev->dev_private;
10663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10664 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10665 struct drm_display_mode *mode;
10666 struct intel_crtc_state pipe_config;
10667 int htot = I915_READ(HTOTAL(cpu_transcoder));
10668 int hsync = I915_READ(HSYNC(cpu_transcoder));
10669 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10670 int vsync = I915_READ(VSYNC(cpu_transcoder));
10671 enum pipe pipe = intel_crtc->pipe;
10672
10673 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10674 if (!mode)
10675 return NULL;
10676
10677 /*
10678 * Construct a pipe_config sufficient for getting the clock info
10679 * back out of crtc_clock_get.
10680 *
10681 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10682 * to use a real value here instead.
10683 */
10684 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10685 pipe_config.pixel_multiplier = 1;
10686 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10687 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10688 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10689 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10690
10691 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10692 mode->hdisplay = (htot & 0xffff) + 1;
10693 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10694 mode->hsync_start = (hsync & 0xffff) + 1;
10695 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10696 mode->vdisplay = (vtot & 0xffff) + 1;
10697 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10698 mode->vsync_start = (vsync & 0xffff) + 1;
10699 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10700
10701 drm_mode_set_name(mode);
10702
10703 return mode;
10704 }
10705
10706 void intel_mark_busy(struct drm_device *dev)
10707 {
10708 struct drm_i915_private *dev_priv = dev->dev_private;
10709
10710 if (dev_priv->mm.busy)
10711 return;
10712
10713 intel_runtime_pm_get(dev_priv);
10714 i915_update_gfx_val(dev_priv);
10715 if (INTEL_INFO(dev)->gen >= 6)
10716 gen6_rps_busy(dev_priv);
10717 dev_priv->mm.busy = true;
10718 }
10719
10720 void intel_mark_idle(struct drm_device *dev)
10721 {
10722 struct drm_i915_private *dev_priv = dev->dev_private;
10723
10724 if (!dev_priv->mm.busy)
10725 return;
10726
10727 dev_priv->mm.busy = false;
10728
10729 if (INTEL_INFO(dev)->gen >= 6)
10730 gen6_rps_idle(dev->dev_private);
10731
10732 intel_runtime_pm_put(dev_priv);
10733 }
10734
10735 static void intel_crtc_destroy(struct drm_crtc *crtc)
10736 {
10737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10738 struct drm_device *dev = crtc->dev;
10739 struct intel_unpin_work *work;
10740
10741 spin_lock_irq(&dev->event_lock);
10742 work = intel_crtc->unpin_work;
10743 intel_crtc->unpin_work = NULL;
10744 spin_unlock_irq(&dev->event_lock);
10745
10746 if (work) {
10747 cancel_work_sync(&work->work);
10748 kfree(work);
10749 }
10750
10751 drm_crtc_cleanup(crtc);
10752
10753 kfree(intel_crtc);
10754 }
10755
10756 static void intel_unpin_work_fn(struct work_struct *__work)
10757 {
10758 struct intel_unpin_work *work =
10759 container_of(__work, struct intel_unpin_work, work);
10760 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10761 struct drm_device *dev = crtc->base.dev;
10762 struct drm_plane *primary = crtc->base.primary;
10763
10764 mutex_lock(&dev->struct_mutex);
10765 intel_unpin_fb_obj(work->old_fb, primary->state);
10766 drm_gem_object_unreference(&work->pending_flip_obj->base);
10767
10768 if (work->flip_queued_req)
10769 i915_gem_request_assign(&work->flip_queued_req, NULL);
10770 mutex_unlock(&dev->struct_mutex);
10771
10772 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10773 drm_framebuffer_unreference(work->old_fb);
10774
10775 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10776 atomic_dec(&crtc->unpin_work_count);
10777
10778 kfree(work);
10779 }
10780
10781 static void do_intel_finish_page_flip(struct drm_device *dev,
10782 struct drm_crtc *crtc)
10783 {
10784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10785 struct intel_unpin_work *work;
10786 unsigned long flags;
10787
10788 /* Ignore early vblank irqs */
10789 if (intel_crtc == NULL)
10790 return;
10791
10792 /*
10793 * This is called both by irq handlers and the reset code (to complete
10794 * lost pageflips) so needs the full irqsave spinlocks.
10795 */
10796 spin_lock_irqsave(&dev->event_lock, flags);
10797 work = intel_crtc->unpin_work;
10798
10799 /* Ensure we don't miss a work->pending update ... */
10800 smp_rmb();
10801
10802 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10803 spin_unlock_irqrestore(&dev->event_lock, flags);
10804 return;
10805 }
10806
10807 page_flip_completed(intel_crtc);
10808
10809 spin_unlock_irqrestore(&dev->event_lock, flags);
10810 }
10811
10812 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10813 {
10814 struct drm_i915_private *dev_priv = dev->dev_private;
10815 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10816
10817 do_intel_finish_page_flip(dev, crtc);
10818 }
10819
10820 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10821 {
10822 struct drm_i915_private *dev_priv = dev->dev_private;
10823 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10824
10825 do_intel_finish_page_flip(dev, crtc);
10826 }
10827
10828 /* Is 'a' after or equal to 'b'? */
10829 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10830 {
10831 return !((a - b) & 0x80000000);
10832 }
10833
10834 static bool page_flip_finished(struct intel_crtc *crtc)
10835 {
10836 struct drm_device *dev = crtc->base.dev;
10837 struct drm_i915_private *dev_priv = dev->dev_private;
10838
10839 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10840 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10841 return true;
10842
10843 /*
10844 * The relevant registers doen't exist on pre-ctg.
10845 * As the flip done interrupt doesn't trigger for mmio
10846 * flips on gmch platforms, a flip count check isn't
10847 * really needed there. But since ctg has the registers,
10848 * include it in the check anyway.
10849 */
10850 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10851 return true;
10852
10853 /*
10854 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10855 * used the same base address. In that case the mmio flip might
10856 * have completed, but the CS hasn't even executed the flip yet.
10857 *
10858 * A flip count check isn't enough as the CS might have updated
10859 * the base address just after start of vblank, but before we
10860 * managed to process the interrupt. This means we'd complete the
10861 * CS flip too soon.
10862 *
10863 * Combining both checks should get us a good enough result. It may
10864 * still happen that the CS flip has been executed, but has not
10865 * yet actually completed. But in case the base address is the same
10866 * anyway, we don't really care.
10867 */
10868 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10869 crtc->unpin_work->gtt_offset &&
10870 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10871 crtc->unpin_work->flip_count);
10872 }
10873
10874 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10875 {
10876 struct drm_i915_private *dev_priv = dev->dev_private;
10877 struct intel_crtc *intel_crtc =
10878 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10879 unsigned long flags;
10880
10881
10882 /*
10883 * This is called both by irq handlers and the reset code (to complete
10884 * lost pageflips) so needs the full irqsave spinlocks.
10885 *
10886 * NB: An MMIO update of the plane base pointer will also
10887 * generate a page-flip completion irq, i.e. every modeset
10888 * is also accompanied by a spurious intel_prepare_page_flip().
10889 */
10890 spin_lock_irqsave(&dev->event_lock, flags);
10891 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10892 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10893 spin_unlock_irqrestore(&dev->event_lock, flags);
10894 }
10895
10896 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10897 {
10898 /* Ensure that the work item is consistent when activating it ... */
10899 smp_wmb();
10900 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10901 /* and that it is marked active as soon as the irq could fire. */
10902 smp_wmb();
10903 }
10904
10905 static int intel_gen2_queue_flip(struct drm_device *dev,
10906 struct drm_crtc *crtc,
10907 struct drm_framebuffer *fb,
10908 struct drm_i915_gem_object *obj,
10909 struct drm_i915_gem_request *req,
10910 uint32_t flags)
10911 {
10912 struct intel_engine_cs *ring = req->ring;
10913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10914 u32 flip_mask;
10915 int ret;
10916
10917 ret = intel_ring_begin(req, 6);
10918 if (ret)
10919 return ret;
10920
10921 /* Can't queue multiple flips, so wait for the previous
10922 * one to finish before executing the next.
10923 */
10924 if (intel_crtc->plane)
10925 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10926 else
10927 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10928 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10929 intel_ring_emit(ring, MI_NOOP);
10930 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10931 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10932 intel_ring_emit(ring, fb->pitches[0]);
10933 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10934 intel_ring_emit(ring, 0); /* aux display base address, unused */
10935
10936 intel_mark_page_flip_active(intel_crtc->unpin_work);
10937 return 0;
10938 }
10939
10940 static int intel_gen3_queue_flip(struct drm_device *dev,
10941 struct drm_crtc *crtc,
10942 struct drm_framebuffer *fb,
10943 struct drm_i915_gem_object *obj,
10944 struct drm_i915_gem_request *req,
10945 uint32_t flags)
10946 {
10947 struct intel_engine_cs *ring = req->ring;
10948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10949 u32 flip_mask;
10950 int ret;
10951
10952 ret = intel_ring_begin(req, 6);
10953 if (ret)
10954 return ret;
10955
10956 if (intel_crtc->plane)
10957 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10958 else
10959 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10960 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10961 intel_ring_emit(ring, MI_NOOP);
10962 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10963 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10964 intel_ring_emit(ring, fb->pitches[0]);
10965 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10966 intel_ring_emit(ring, MI_NOOP);
10967
10968 intel_mark_page_flip_active(intel_crtc->unpin_work);
10969 return 0;
10970 }
10971
10972 static int intel_gen4_queue_flip(struct drm_device *dev,
10973 struct drm_crtc *crtc,
10974 struct drm_framebuffer *fb,
10975 struct drm_i915_gem_object *obj,
10976 struct drm_i915_gem_request *req,
10977 uint32_t flags)
10978 {
10979 struct intel_engine_cs *ring = req->ring;
10980 struct drm_i915_private *dev_priv = dev->dev_private;
10981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10982 uint32_t pf, pipesrc;
10983 int ret;
10984
10985 ret = intel_ring_begin(req, 4);
10986 if (ret)
10987 return ret;
10988
10989 /* i965+ uses the linear or tiled offsets from the
10990 * Display Registers (which do not change across a page-flip)
10991 * so we need only reprogram the base address.
10992 */
10993 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10994 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10995 intel_ring_emit(ring, fb->pitches[0]);
10996 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10997 obj->tiling_mode);
10998
10999 /* XXX Enabling the panel-fitter across page-flip is so far
11000 * untested on non-native modes, so ignore it for now.
11001 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11002 */
11003 pf = 0;
11004 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11005 intel_ring_emit(ring, pf | pipesrc);
11006
11007 intel_mark_page_flip_active(intel_crtc->unpin_work);
11008 return 0;
11009 }
11010
11011 static int intel_gen6_queue_flip(struct drm_device *dev,
11012 struct drm_crtc *crtc,
11013 struct drm_framebuffer *fb,
11014 struct drm_i915_gem_object *obj,
11015 struct drm_i915_gem_request *req,
11016 uint32_t flags)
11017 {
11018 struct intel_engine_cs *ring = req->ring;
11019 struct drm_i915_private *dev_priv = dev->dev_private;
11020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11021 uint32_t pf, pipesrc;
11022 int ret;
11023
11024 ret = intel_ring_begin(req, 4);
11025 if (ret)
11026 return ret;
11027
11028 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11029 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11030 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11031 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11032
11033 /* Contrary to the suggestions in the documentation,
11034 * "Enable Panel Fitter" does not seem to be required when page
11035 * flipping with a non-native mode, and worse causes a normal
11036 * modeset to fail.
11037 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11038 */
11039 pf = 0;
11040 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11041 intel_ring_emit(ring, pf | pipesrc);
11042
11043 intel_mark_page_flip_active(intel_crtc->unpin_work);
11044 return 0;
11045 }
11046
11047 static int intel_gen7_queue_flip(struct drm_device *dev,
11048 struct drm_crtc *crtc,
11049 struct drm_framebuffer *fb,
11050 struct drm_i915_gem_object *obj,
11051 struct drm_i915_gem_request *req,
11052 uint32_t flags)
11053 {
11054 struct intel_engine_cs *ring = req->ring;
11055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11056 uint32_t plane_bit = 0;
11057 int len, ret;
11058
11059 switch (intel_crtc->plane) {
11060 case PLANE_A:
11061 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11062 break;
11063 case PLANE_B:
11064 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11065 break;
11066 case PLANE_C:
11067 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11068 break;
11069 default:
11070 WARN_ONCE(1, "unknown plane in flip command\n");
11071 return -ENODEV;
11072 }
11073
11074 len = 4;
11075 if (ring->id == RCS) {
11076 len += 6;
11077 /*
11078 * On Gen 8, SRM is now taking an extra dword to accommodate
11079 * 48bits addresses, and we need a NOOP for the batch size to
11080 * stay even.
11081 */
11082 if (IS_GEN8(dev))
11083 len += 2;
11084 }
11085
11086 /*
11087 * BSpec MI_DISPLAY_FLIP for IVB:
11088 * "The full packet must be contained within the same cache line."
11089 *
11090 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11091 * cacheline, if we ever start emitting more commands before
11092 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11093 * then do the cacheline alignment, and finally emit the
11094 * MI_DISPLAY_FLIP.
11095 */
11096 ret = intel_ring_cacheline_align(req);
11097 if (ret)
11098 return ret;
11099
11100 ret = intel_ring_begin(req, len);
11101 if (ret)
11102 return ret;
11103
11104 /* Unmask the flip-done completion message. Note that the bspec says that
11105 * we should do this for both the BCS and RCS, and that we must not unmask
11106 * more than one flip event at any time (or ensure that one flip message
11107 * can be sent by waiting for flip-done prior to queueing new flips).
11108 * Experimentation says that BCS works despite DERRMR masking all
11109 * flip-done completion events and that unmasking all planes at once
11110 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11111 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11112 */
11113 if (ring->id == RCS) {
11114 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11115 intel_ring_emit(ring, DERRMR);
11116 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11117 DERRMR_PIPEB_PRI_FLIP_DONE |
11118 DERRMR_PIPEC_PRI_FLIP_DONE));
11119 if (IS_GEN8(dev))
11120 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11121 MI_SRM_LRM_GLOBAL_GTT);
11122 else
11123 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11124 MI_SRM_LRM_GLOBAL_GTT);
11125 intel_ring_emit(ring, DERRMR);
11126 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11127 if (IS_GEN8(dev)) {
11128 intel_ring_emit(ring, 0);
11129 intel_ring_emit(ring, MI_NOOP);
11130 }
11131 }
11132
11133 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11134 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11135 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11136 intel_ring_emit(ring, (MI_NOOP));
11137
11138 intel_mark_page_flip_active(intel_crtc->unpin_work);
11139 return 0;
11140 }
11141
11142 static bool use_mmio_flip(struct intel_engine_cs *ring,
11143 struct drm_i915_gem_object *obj)
11144 {
11145 /*
11146 * This is not being used for older platforms, because
11147 * non-availability of flip done interrupt forces us to use
11148 * CS flips. Older platforms derive flip done using some clever
11149 * tricks involving the flip_pending status bits and vblank irqs.
11150 * So using MMIO flips there would disrupt this mechanism.
11151 */
11152
11153 if (ring == NULL)
11154 return true;
11155
11156 if (INTEL_INFO(ring->dev)->gen < 5)
11157 return false;
11158
11159 if (i915.use_mmio_flip < 0)
11160 return false;
11161 else if (i915.use_mmio_flip > 0)
11162 return true;
11163 else if (i915.enable_execlists)
11164 return true;
11165 else
11166 return ring != i915_gem_request_get_ring(obj->last_write_req);
11167 }
11168
11169 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11170 struct intel_unpin_work *work)
11171 {
11172 struct drm_device *dev = intel_crtc->base.dev;
11173 struct drm_i915_private *dev_priv = dev->dev_private;
11174 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11175 const enum pipe pipe = intel_crtc->pipe;
11176 u32 ctl, stride;
11177
11178 ctl = I915_READ(PLANE_CTL(pipe, 0));
11179 ctl &= ~PLANE_CTL_TILED_MASK;
11180 switch (fb->modifier[0]) {
11181 case DRM_FORMAT_MOD_NONE:
11182 break;
11183 case I915_FORMAT_MOD_X_TILED:
11184 ctl |= PLANE_CTL_TILED_X;
11185 break;
11186 case I915_FORMAT_MOD_Y_TILED:
11187 ctl |= PLANE_CTL_TILED_Y;
11188 break;
11189 case I915_FORMAT_MOD_Yf_TILED:
11190 ctl |= PLANE_CTL_TILED_YF;
11191 break;
11192 default:
11193 MISSING_CASE(fb->modifier[0]);
11194 }
11195
11196 /*
11197 * The stride is either expressed as a multiple of 64 bytes chunks for
11198 * linear buffers or in number of tiles for tiled buffers.
11199 */
11200 stride = fb->pitches[0] /
11201 intel_fb_stride_alignment(dev, fb->modifier[0],
11202 fb->pixel_format);
11203
11204 /*
11205 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11206 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11207 */
11208 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11209 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11210
11211 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11212 POSTING_READ(PLANE_SURF(pipe, 0));
11213 }
11214
11215 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11216 struct intel_unpin_work *work)
11217 {
11218 struct drm_device *dev = intel_crtc->base.dev;
11219 struct drm_i915_private *dev_priv = dev->dev_private;
11220 struct intel_framebuffer *intel_fb =
11221 to_intel_framebuffer(intel_crtc->base.primary->fb);
11222 struct drm_i915_gem_object *obj = intel_fb->obj;
11223 u32 dspcntr;
11224 u32 reg;
11225
11226 reg = DSPCNTR(intel_crtc->plane);
11227 dspcntr = I915_READ(reg);
11228
11229 if (obj->tiling_mode != I915_TILING_NONE)
11230 dspcntr |= DISPPLANE_TILED;
11231 else
11232 dspcntr &= ~DISPPLANE_TILED;
11233
11234 I915_WRITE(reg, dspcntr);
11235
11236 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11237 POSTING_READ(DSPSURF(intel_crtc->plane));
11238 }
11239
11240 /*
11241 * XXX: This is the temporary way to update the plane registers until we get
11242 * around to using the usual plane update functions for MMIO flips
11243 */
11244 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11245 {
11246 struct intel_crtc *crtc = mmio_flip->crtc;
11247 struct intel_unpin_work *work;
11248
11249 spin_lock_irq(&crtc->base.dev->event_lock);
11250 work = crtc->unpin_work;
11251 spin_unlock_irq(&crtc->base.dev->event_lock);
11252 if (work == NULL)
11253 return;
11254
11255 intel_mark_page_flip_active(work);
11256
11257 intel_pipe_update_start(crtc);
11258
11259 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11260 skl_do_mmio_flip(crtc, work);
11261 else
11262 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11263 ilk_do_mmio_flip(crtc, work);
11264
11265 intel_pipe_update_end(crtc);
11266 }
11267
11268 static void intel_mmio_flip_work_func(struct work_struct *work)
11269 {
11270 struct intel_mmio_flip *mmio_flip =
11271 container_of(work, struct intel_mmio_flip, work);
11272
11273 if (mmio_flip->req) {
11274 WARN_ON(__i915_wait_request(mmio_flip->req,
11275 mmio_flip->crtc->reset_counter,
11276 false, NULL,
11277 &mmio_flip->i915->rps.mmioflips));
11278 i915_gem_request_unreference__unlocked(mmio_flip->req);
11279 }
11280
11281 intel_do_mmio_flip(mmio_flip);
11282 kfree(mmio_flip);
11283 }
11284
11285 static int intel_queue_mmio_flip(struct drm_device *dev,
11286 struct drm_crtc *crtc,
11287 struct drm_framebuffer *fb,
11288 struct drm_i915_gem_object *obj,
11289 struct intel_engine_cs *ring,
11290 uint32_t flags)
11291 {
11292 struct intel_mmio_flip *mmio_flip;
11293
11294 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11295 if (mmio_flip == NULL)
11296 return -ENOMEM;
11297
11298 mmio_flip->i915 = to_i915(dev);
11299 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11300 mmio_flip->crtc = to_intel_crtc(crtc);
11301
11302 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11303 schedule_work(&mmio_flip->work);
11304
11305 return 0;
11306 }
11307
11308 static int intel_default_queue_flip(struct drm_device *dev,
11309 struct drm_crtc *crtc,
11310 struct drm_framebuffer *fb,
11311 struct drm_i915_gem_object *obj,
11312 struct drm_i915_gem_request *req,
11313 uint32_t flags)
11314 {
11315 return -ENODEV;
11316 }
11317
11318 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11319 struct drm_crtc *crtc)
11320 {
11321 struct drm_i915_private *dev_priv = dev->dev_private;
11322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11323 struct intel_unpin_work *work = intel_crtc->unpin_work;
11324 u32 addr;
11325
11326 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11327 return true;
11328
11329 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11330 return false;
11331
11332 if (!work->enable_stall_check)
11333 return false;
11334
11335 if (work->flip_ready_vblank == 0) {
11336 if (work->flip_queued_req &&
11337 !i915_gem_request_completed(work->flip_queued_req, true))
11338 return false;
11339
11340 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11341 }
11342
11343 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11344 return false;
11345
11346 /* Potential stall - if we see that the flip has happened,
11347 * assume a missed interrupt. */
11348 if (INTEL_INFO(dev)->gen >= 4)
11349 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11350 else
11351 addr = I915_READ(DSPADDR(intel_crtc->plane));
11352
11353 /* There is a potential issue here with a false positive after a flip
11354 * to the same address. We could address this by checking for a
11355 * non-incrementing frame counter.
11356 */
11357 return addr == work->gtt_offset;
11358 }
11359
11360 void intel_check_page_flip(struct drm_device *dev, int pipe)
11361 {
11362 struct drm_i915_private *dev_priv = dev->dev_private;
11363 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11365 struct intel_unpin_work *work;
11366
11367 WARN_ON(!in_interrupt());
11368
11369 if (crtc == NULL)
11370 return;
11371
11372 spin_lock(&dev->event_lock);
11373 work = intel_crtc->unpin_work;
11374 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11375 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11376 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11377 page_flip_completed(intel_crtc);
11378 work = NULL;
11379 }
11380 if (work != NULL &&
11381 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11382 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11383 spin_unlock(&dev->event_lock);
11384 }
11385
11386 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11387 struct drm_framebuffer *fb,
11388 struct drm_pending_vblank_event *event,
11389 uint32_t page_flip_flags)
11390 {
11391 struct drm_device *dev = crtc->dev;
11392 struct drm_i915_private *dev_priv = dev->dev_private;
11393 struct drm_framebuffer *old_fb = crtc->primary->fb;
11394 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11396 struct drm_plane *primary = crtc->primary;
11397 enum pipe pipe = intel_crtc->pipe;
11398 struct intel_unpin_work *work;
11399 struct intel_engine_cs *ring;
11400 bool mmio_flip;
11401 struct drm_i915_gem_request *request = NULL;
11402 int ret;
11403
11404 /*
11405 * drm_mode_page_flip_ioctl() should already catch this, but double
11406 * check to be safe. In the future we may enable pageflipping from
11407 * a disabled primary plane.
11408 */
11409 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11410 return -EBUSY;
11411
11412 /* Can't change pixel format via MI display flips. */
11413 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11414 return -EINVAL;
11415
11416 /*
11417 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11418 * Note that pitch changes could also affect these register.
11419 */
11420 if (INTEL_INFO(dev)->gen > 3 &&
11421 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11422 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11423 return -EINVAL;
11424
11425 if (i915_terminally_wedged(&dev_priv->gpu_error))
11426 goto out_hang;
11427
11428 work = kzalloc(sizeof(*work), GFP_KERNEL);
11429 if (work == NULL)
11430 return -ENOMEM;
11431
11432 work->event = event;
11433 work->crtc = crtc;
11434 work->old_fb = old_fb;
11435 INIT_WORK(&work->work, intel_unpin_work_fn);
11436
11437 ret = drm_crtc_vblank_get(crtc);
11438 if (ret)
11439 goto free_work;
11440
11441 /* We borrow the event spin lock for protecting unpin_work */
11442 spin_lock_irq(&dev->event_lock);
11443 if (intel_crtc->unpin_work) {
11444 /* Before declaring the flip queue wedged, check if
11445 * the hardware completed the operation behind our backs.
11446 */
11447 if (__intel_pageflip_stall_check(dev, crtc)) {
11448 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11449 page_flip_completed(intel_crtc);
11450 } else {
11451 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11452 spin_unlock_irq(&dev->event_lock);
11453
11454 drm_crtc_vblank_put(crtc);
11455 kfree(work);
11456 return -EBUSY;
11457 }
11458 }
11459 intel_crtc->unpin_work = work;
11460 spin_unlock_irq(&dev->event_lock);
11461
11462 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11463 flush_workqueue(dev_priv->wq);
11464
11465 /* Reference the objects for the scheduled work. */
11466 drm_framebuffer_reference(work->old_fb);
11467 drm_gem_object_reference(&obj->base);
11468
11469 crtc->primary->fb = fb;
11470 update_state_fb(crtc->primary);
11471
11472 work->pending_flip_obj = obj;
11473
11474 ret = i915_mutex_lock_interruptible(dev);
11475 if (ret)
11476 goto cleanup;
11477
11478 atomic_inc(&intel_crtc->unpin_work_count);
11479 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11480
11481 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11482 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11483
11484 if (IS_VALLEYVIEW(dev)) {
11485 ring = &dev_priv->ring[BCS];
11486 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11487 /* vlv: DISPLAY_FLIP fails to change tiling */
11488 ring = NULL;
11489 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11490 ring = &dev_priv->ring[BCS];
11491 } else if (INTEL_INFO(dev)->gen >= 7) {
11492 ring = i915_gem_request_get_ring(obj->last_write_req);
11493 if (ring == NULL || ring->id != RCS)
11494 ring = &dev_priv->ring[BCS];
11495 } else {
11496 ring = &dev_priv->ring[RCS];
11497 }
11498
11499 mmio_flip = use_mmio_flip(ring, obj);
11500
11501 /* When using CS flips, we want to emit semaphores between rings.
11502 * However, when using mmio flips we will create a task to do the
11503 * synchronisation, so all we want here is to pin the framebuffer
11504 * into the display plane and skip any waits.
11505 */
11506 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11507 crtc->primary->state,
11508 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11509 if (ret)
11510 goto cleanup_pending;
11511
11512 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11513 obj, 0);
11514 work->gtt_offset += intel_crtc->dspaddr_offset;
11515
11516 if (mmio_flip) {
11517 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11518 page_flip_flags);
11519 if (ret)
11520 goto cleanup_unpin;
11521
11522 i915_gem_request_assign(&work->flip_queued_req,
11523 obj->last_write_req);
11524 } else {
11525 if (!request) {
11526 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11527 if (ret)
11528 goto cleanup_unpin;
11529 }
11530
11531 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11532 page_flip_flags);
11533 if (ret)
11534 goto cleanup_unpin;
11535
11536 i915_gem_request_assign(&work->flip_queued_req, request);
11537 }
11538
11539 if (request)
11540 i915_add_request_no_flush(request);
11541
11542 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11543 work->enable_stall_check = true;
11544
11545 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11546 to_intel_plane(primary)->frontbuffer_bit);
11547 mutex_unlock(&dev->struct_mutex);
11548
11549 intel_fbc_disable_crtc(intel_crtc);
11550 intel_frontbuffer_flip_prepare(dev,
11551 to_intel_plane(primary)->frontbuffer_bit);
11552
11553 trace_i915_flip_request(intel_crtc->plane, obj);
11554
11555 return 0;
11556
11557 cleanup_unpin:
11558 intel_unpin_fb_obj(fb, crtc->primary->state);
11559 cleanup_pending:
11560 if (request)
11561 i915_gem_request_cancel(request);
11562 atomic_dec(&intel_crtc->unpin_work_count);
11563 mutex_unlock(&dev->struct_mutex);
11564 cleanup:
11565 crtc->primary->fb = old_fb;
11566 update_state_fb(crtc->primary);
11567
11568 drm_gem_object_unreference_unlocked(&obj->base);
11569 drm_framebuffer_unreference(work->old_fb);
11570
11571 spin_lock_irq(&dev->event_lock);
11572 intel_crtc->unpin_work = NULL;
11573 spin_unlock_irq(&dev->event_lock);
11574
11575 drm_crtc_vblank_put(crtc);
11576 free_work:
11577 kfree(work);
11578
11579 if (ret == -EIO) {
11580 struct drm_atomic_state *state;
11581 struct drm_plane_state *plane_state;
11582
11583 out_hang:
11584 state = drm_atomic_state_alloc(dev);
11585 if (!state)
11586 return -ENOMEM;
11587 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11588
11589 retry:
11590 plane_state = drm_atomic_get_plane_state(state, primary);
11591 ret = PTR_ERR_OR_ZERO(plane_state);
11592 if (!ret) {
11593 drm_atomic_set_fb_for_plane(plane_state, fb);
11594
11595 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11596 if (!ret)
11597 ret = drm_atomic_commit(state);
11598 }
11599
11600 if (ret == -EDEADLK) {
11601 drm_modeset_backoff(state->acquire_ctx);
11602 drm_atomic_state_clear(state);
11603 goto retry;
11604 }
11605
11606 if (ret)
11607 drm_atomic_state_free(state);
11608
11609 if (ret == 0 && event) {
11610 spin_lock_irq(&dev->event_lock);
11611 drm_send_vblank_event(dev, pipe, event);
11612 spin_unlock_irq(&dev->event_lock);
11613 }
11614 }
11615 return ret;
11616 }
11617
11618
11619 /**
11620 * intel_wm_need_update - Check whether watermarks need updating
11621 * @plane: drm plane
11622 * @state: new plane state
11623 *
11624 * Check current plane state versus the new one to determine whether
11625 * watermarks need to be recalculated.
11626 *
11627 * Returns true or false.
11628 */
11629 static bool intel_wm_need_update(struct drm_plane *plane,
11630 struct drm_plane_state *state)
11631 {
11632 /* Update watermarks on tiling changes. */
11633 if (!plane->state->fb || !state->fb ||
11634 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11635 plane->state->rotation != state->rotation)
11636 return true;
11637
11638 if (plane->state->crtc_w != state->crtc_w)
11639 return true;
11640
11641 return false;
11642 }
11643
11644 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11645 struct drm_plane_state *plane_state)
11646 {
11647 struct drm_crtc *crtc = crtc_state->crtc;
11648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11649 struct drm_plane *plane = plane_state->plane;
11650 struct drm_device *dev = crtc->dev;
11651 struct drm_i915_private *dev_priv = dev->dev_private;
11652 struct intel_plane_state *old_plane_state =
11653 to_intel_plane_state(plane->state);
11654 int idx = intel_crtc->base.base.id, ret;
11655 int i = drm_plane_index(plane);
11656 bool mode_changed = needs_modeset(crtc_state);
11657 bool was_crtc_enabled = crtc->state->active;
11658 bool is_crtc_enabled = crtc_state->active;
11659
11660 bool turn_off, turn_on, visible, was_visible;
11661 struct drm_framebuffer *fb = plane_state->fb;
11662
11663 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11664 plane->type != DRM_PLANE_TYPE_CURSOR) {
11665 ret = skl_update_scaler_plane(
11666 to_intel_crtc_state(crtc_state),
11667 to_intel_plane_state(plane_state));
11668 if (ret)
11669 return ret;
11670 }
11671
11672 /*
11673 * Disabling a plane is always okay; we just need to update
11674 * fb tracking in a special way since cleanup_fb() won't
11675 * get called by the plane helpers.
11676 */
11677 if (old_plane_state->base.fb && !fb)
11678 intel_crtc->atomic.disabled_planes |= 1 << i;
11679
11680 was_visible = old_plane_state->visible;
11681 visible = to_intel_plane_state(plane_state)->visible;
11682
11683 if (!was_crtc_enabled && WARN_ON(was_visible))
11684 was_visible = false;
11685
11686 if (!is_crtc_enabled && WARN_ON(visible))
11687 visible = false;
11688
11689 if (!was_visible && !visible)
11690 return 0;
11691
11692 turn_off = was_visible && (!visible || mode_changed);
11693 turn_on = visible && (!was_visible || mode_changed);
11694
11695 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11696 plane->base.id, fb ? fb->base.id : -1);
11697
11698 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11699 plane->base.id, was_visible, visible,
11700 turn_off, turn_on, mode_changed);
11701
11702 if (turn_on) {
11703 intel_crtc->atomic.update_wm_pre = true;
11704 /* must disable cxsr around plane enable/disable */
11705 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11706 intel_crtc->atomic.disable_cxsr = true;
11707 /* to potentially re-enable cxsr */
11708 intel_crtc->atomic.wait_vblank = true;
11709 intel_crtc->atomic.update_wm_post = true;
11710 }
11711 } else if (turn_off) {
11712 intel_crtc->atomic.update_wm_post = true;
11713 /* must disable cxsr around plane enable/disable */
11714 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11715 if (is_crtc_enabled)
11716 intel_crtc->atomic.wait_vblank = true;
11717 intel_crtc->atomic.disable_cxsr = true;
11718 }
11719 } else if (intel_wm_need_update(plane, plane_state)) {
11720 intel_crtc->atomic.update_wm_pre = true;
11721 }
11722
11723 if (visible || was_visible)
11724 intel_crtc->atomic.fb_bits |=
11725 to_intel_plane(plane)->frontbuffer_bit;
11726
11727 switch (plane->type) {
11728 case DRM_PLANE_TYPE_PRIMARY:
11729 intel_crtc->atomic.wait_for_flips = true;
11730 intel_crtc->atomic.pre_disable_primary = turn_off;
11731 intel_crtc->atomic.post_enable_primary = turn_on;
11732
11733 if (turn_off) {
11734 /*
11735 * FIXME: Actually if we will still have any other
11736 * plane enabled on the pipe we could let IPS enabled
11737 * still, but for now lets consider that when we make
11738 * primary invisible by setting DSPCNTR to 0 on
11739 * update_primary_plane function IPS needs to be
11740 * disable.
11741 */
11742 intel_crtc->atomic.disable_ips = true;
11743
11744 intel_crtc->atomic.disable_fbc = true;
11745 }
11746
11747 /*
11748 * FBC does not work on some platforms for rotated
11749 * planes, so disable it when rotation is not 0 and
11750 * update it when rotation is set back to 0.
11751 *
11752 * FIXME: This is redundant with the fbc update done in
11753 * the primary plane enable function except that that
11754 * one is done too late. We eventually need to unify
11755 * this.
11756 */
11757
11758 if (visible &&
11759 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11760 dev_priv->fbc.crtc == intel_crtc &&
11761 plane_state->rotation != BIT(DRM_ROTATE_0))
11762 intel_crtc->atomic.disable_fbc = true;
11763
11764 /*
11765 * BDW signals flip done immediately if the plane
11766 * is disabled, even if the plane enable is already
11767 * armed to occur at the next vblank :(
11768 */
11769 if (turn_on && IS_BROADWELL(dev))
11770 intel_crtc->atomic.wait_vblank = true;
11771
11772 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11773 break;
11774 case DRM_PLANE_TYPE_CURSOR:
11775 break;
11776 case DRM_PLANE_TYPE_OVERLAY:
11777 if (turn_off && !mode_changed) {
11778 intel_crtc->atomic.wait_vblank = true;
11779 intel_crtc->atomic.update_sprite_watermarks |=
11780 1 << i;
11781 }
11782 }
11783 return 0;
11784 }
11785
11786 static bool encoders_cloneable(const struct intel_encoder *a,
11787 const struct intel_encoder *b)
11788 {
11789 /* masks could be asymmetric, so check both ways */
11790 return a == b || (a->cloneable & (1 << b->type) &&
11791 b->cloneable & (1 << a->type));
11792 }
11793
11794 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11795 struct intel_crtc *crtc,
11796 struct intel_encoder *encoder)
11797 {
11798 struct intel_encoder *source_encoder;
11799 struct drm_connector *connector;
11800 struct drm_connector_state *connector_state;
11801 int i;
11802
11803 for_each_connector_in_state(state, connector, connector_state, i) {
11804 if (connector_state->crtc != &crtc->base)
11805 continue;
11806
11807 source_encoder =
11808 to_intel_encoder(connector_state->best_encoder);
11809 if (!encoders_cloneable(encoder, source_encoder))
11810 return false;
11811 }
11812
11813 return true;
11814 }
11815
11816 static bool check_encoder_cloning(struct drm_atomic_state *state,
11817 struct intel_crtc *crtc)
11818 {
11819 struct intel_encoder *encoder;
11820 struct drm_connector *connector;
11821 struct drm_connector_state *connector_state;
11822 int i;
11823
11824 for_each_connector_in_state(state, connector, connector_state, i) {
11825 if (connector_state->crtc != &crtc->base)
11826 continue;
11827
11828 encoder = to_intel_encoder(connector_state->best_encoder);
11829 if (!check_single_encoder_cloning(state, crtc, encoder))
11830 return false;
11831 }
11832
11833 return true;
11834 }
11835
11836 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11837 struct drm_crtc_state *crtc_state)
11838 {
11839 struct drm_device *dev = crtc->dev;
11840 struct drm_i915_private *dev_priv = dev->dev_private;
11841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11842 struct intel_crtc_state *pipe_config =
11843 to_intel_crtc_state(crtc_state);
11844 struct drm_atomic_state *state = crtc_state->state;
11845 int ret;
11846 bool mode_changed = needs_modeset(crtc_state);
11847
11848 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11849 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11850 return -EINVAL;
11851 }
11852
11853 if (mode_changed && !crtc_state->active)
11854 intel_crtc->atomic.update_wm_post = true;
11855
11856 if (mode_changed && crtc_state->enable &&
11857 dev_priv->display.crtc_compute_clock &&
11858 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11859 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11860 pipe_config);
11861 if (ret)
11862 return ret;
11863 }
11864
11865 ret = 0;
11866 if (INTEL_INFO(dev)->gen >= 9) {
11867 if (mode_changed)
11868 ret = skl_update_scaler_crtc(pipe_config);
11869
11870 if (!ret)
11871 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11872 pipe_config);
11873 }
11874
11875 return ret;
11876 }
11877
11878 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11879 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11880 .load_lut = intel_crtc_load_lut,
11881 .atomic_begin = intel_begin_crtc_commit,
11882 .atomic_flush = intel_finish_crtc_commit,
11883 .atomic_check = intel_crtc_atomic_check,
11884 };
11885
11886 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11887 {
11888 struct intel_connector *connector;
11889
11890 for_each_intel_connector(dev, connector) {
11891 if (connector->base.encoder) {
11892 connector->base.state->best_encoder =
11893 connector->base.encoder;
11894 connector->base.state->crtc =
11895 connector->base.encoder->crtc;
11896 } else {
11897 connector->base.state->best_encoder = NULL;
11898 connector->base.state->crtc = NULL;
11899 }
11900 }
11901 }
11902
11903 static void
11904 connected_sink_compute_bpp(struct intel_connector *connector,
11905 struct intel_crtc_state *pipe_config)
11906 {
11907 int bpp = pipe_config->pipe_bpp;
11908
11909 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11910 connector->base.base.id,
11911 connector->base.name);
11912
11913 /* Don't use an invalid EDID bpc value */
11914 if (connector->base.display_info.bpc &&
11915 connector->base.display_info.bpc * 3 < bpp) {
11916 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11917 bpp, connector->base.display_info.bpc*3);
11918 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11919 }
11920
11921 /* Clamp bpp to 8 on screens without EDID 1.4 */
11922 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11923 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11924 bpp);
11925 pipe_config->pipe_bpp = 24;
11926 }
11927 }
11928
11929 static int
11930 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11931 struct intel_crtc_state *pipe_config)
11932 {
11933 struct drm_device *dev = crtc->base.dev;
11934 struct drm_atomic_state *state;
11935 struct drm_connector *connector;
11936 struct drm_connector_state *connector_state;
11937 int bpp, i;
11938
11939 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11940 bpp = 10*3;
11941 else if (INTEL_INFO(dev)->gen >= 5)
11942 bpp = 12*3;
11943 else
11944 bpp = 8*3;
11945
11946
11947 pipe_config->pipe_bpp = bpp;
11948
11949 state = pipe_config->base.state;
11950
11951 /* Clamp display bpp to EDID value */
11952 for_each_connector_in_state(state, connector, connector_state, i) {
11953 if (connector_state->crtc != &crtc->base)
11954 continue;
11955
11956 connected_sink_compute_bpp(to_intel_connector(connector),
11957 pipe_config);
11958 }
11959
11960 return bpp;
11961 }
11962
11963 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11964 {
11965 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11966 "type: 0x%x flags: 0x%x\n",
11967 mode->crtc_clock,
11968 mode->crtc_hdisplay, mode->crtc_hsync_start,
11969 mode->crtc_hsync_end, mode->crtc_htotal,
11970 mode->crtc_vdisplay, mode->crtc_vsync_start,
11971 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11972 }
11973
11974 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11975 struct intel_crtc_state *pipe_config,
11976 const char *context)
11977 {
11978 struct drm_device *dev = crtc->base.dev;
11979 struct drm_plane *plane;
11980 struct intel_plane *intel_plane;
11981 struct intel_plane_state *state;
11982 struct drm_framebuffer *fb;
11983
11984 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11985 context, pipe_config, pipe_name(crtc->pipe));
11986
11987 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11988 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11989 pipe_config->pipe_bpp, pipe_config->dither);
11990 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11991 pipe_config->has_pch_encoder,
11992 pipe_config->fdi_lanes,
11993 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11994 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11995 pipe_config->fdi_m_n.tu);
11996 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11997 pipe_config->has_dp_encoder,
11998 pipe_config->lane_count,
11999 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12000 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12001 pipe_config->dp_m_n.tu);
12002
12003 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12004 pipe_config->has_dp_encoder,
12005 pipe_config->lane_count,
12006 pipe_config->dp_m2_n2.gmch_m,
12007 pipe_config->dp_m2_n2.gmch_n,
12008 pipe_config->dp_m2_n2.link_m,
12009 pipe_config->dp_m2_n2.link_n,
12010 pipe_config->dp_m2_n2.tu);
12011
12012 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12013 pipe_config->has_audio,
12014 pipe_config->has_infoframe);
12015
12016 DRM_DEBUG_KMS("requested mode:\n");
12017 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12018 DRM_DEBUG_KMS("adjusted mode:\n");
12019 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12020 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12021 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12022 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12023 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12024 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12025 crtc->num_scalers,
12026 pipe_config->scaler_state.scaler_users,
12027 pipe_config->scaler_state.scaler_id);
12028 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12029 pipe_config->gmch_pfit.control,
12030 pipe_config->gmch_pfit.pgm_ratios,
12031 pipe_config->gmch_pfit.lvds_border_bits);
12032 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12033 pipe_config->pch_pfit.pos,
12034 pipe_config->pch_pfit.size,
12035 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12036 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12037 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12038
12039 if (IS_BROXTON(dev)) {
12040 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12041 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12042 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12043 pipe_config->ddi_pll_sel,
12044 pipe_config->dpll_hw_state.ebb0,
12045 pipe_config->dpll_hw_state.ebb4,
12046 pipe_config->dpll_hw_state.pll0,
12047 pipe_config->dpll_hw_state.pll1,
12048 pipe_config->dpll_hw_state.pll2,
12049 pipe_config->dpll_hw_state.pll3,
12050 pipe_config->dpll_hw_state.pll6,
12051 pipe_config->dpll_hw_state.pll8,
12052 pipe_config->dpll_hw_state.pll9,
12053 pipe_config->dpll_hw_state.pll10,
12054 pipe_config->dpll_hw_state.pcsdw12);
12055 } else if (IS_SKYLAKE(dev)) {
12056 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12057 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12058 pipe_config->ddi_pll_sel,
12059 pipe_config->dpll_hw_state.ctrl1,
12060 pipe_config->dpll_hw_state.cfgcr1,
12061 pipe_config->dpll_hw_state.cfgcr2);
12062 } else if (HAS_DDI(dev)) {
12063 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12064 pipe_config->ddi_pll_sel,
12065 pipe_config->dpll_hw_state.wrpll,
12066 pipe_config->dpll_hw_state.spll);
12067 } else {
12068 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12069 "fp0: 0x%x, fp1: 0x%x\n",
12070 pipe_config->dpll_hw_state.dpll,
12071 pipe_config->dpll_hw_state.dpll_md,
12072 pipe_config->dpll_hw_state.fp0,
12073 pipe_config->dpll_hw_state.fp1);
12074 }
12075
12076 DRM_DEBUG_KMS("planes on this crtc\n");
12077 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12078 intel_plane = to_intel_plane(plane);
12079 if (intel_plane->pipe != crtc->pipe)
12080 continue;
12081
12082 state = to_intel_plane_state(plane->state);
12083 fb = state->base.fb;
12084 if (!fb) {
12085 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12086 "disabled, scaler_id = %d\n",
12087 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12088 plane->base.id, intel_plane->pipe,
12089 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12090 drm_plane_index(plane), state->scaler_id);
12091 continue;
12092 }
12093
12094 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12095 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12096 plane->base.id, intel_plane->pipe,
12097 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12098 drm_plane_index(plane));
12099 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12100 fb->base.id, fb->width, fb->height, fb->pixel_format);
12101 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12102 state->scaler_id,
12103 state->src.x1 >> 16, state->src.y1 >> 16,
12104 drm_rect_width(&state->src) >> 16,
12105 drm_rect_height(&state->src) >> 16,
12106 state->dst.x1, state->dst.y1,
12107 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12108 }
12109 }
12110
12111 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12112 {
12113 struct drm_device *dev = state->dev;
12114 struct intel_encoder *encoder;
12115 struct drm_connector *connector;
12116 struct drm_connector_state *connector_state;
12117 unsigned int used_ports = 0;
12118 int i;
12119
12120 /*
12121 * Walk the connector list instead of the encoder
12122 * list to detect the problem on ddi platforms
12123 * where there's just one encoder per digital port.
12124 */
12125 for_each_connector_in_state(state, connector, connector_state, i) {
12126 if (!connector_state->best_encoder)
12127 continue;
12128
12129 encoder = to_intel_encoder(connector_state->best_encoder);
12130
12131 WARN_ON(!connector_state->crtc);
12132
12133 switch (encoder->type) {
12134 unsigned int port_mask;
12135 case INTEL_OUTPUT_UNKNOWN:
12136 if (WARN_ON(!HAS_DDI(dev)))
12137 break;
12138 case INTEL_OUTPUT_DISPLAYPORT:
12139 case INTEL_OUTPUT_HDMI:
12140 case INTEL_OUTPUT_EDP:
12141 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12142
12143 /* the same port mustn't appear more than once */
12144 if (used_ports & port_mask)
12145 return false;
12146
12147 used_ports |= port_mask;
12148 default:
12149 break;
12150 }
12151 }
12152
12153 return true;
12154 }
12155
12156 static void
12157 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12158 {
12159 struct drm_crtc_state tmp_state;
12160 struct intel_crtc_scaler_state scaler_state;
12161 struct intel_dpll_hw_state dpll_hw_state;
12162 enum intel_dpll_id shared_dpll;
12163 uint32_t ddi_pll_sel;
12164 bool force_thru;
12165
12166 /* FIXME: before the switch to atomic started, a new pipe_config was
12167 * kzalloc'd. Code that depends on any field being zero should be
12168 * fixed, so that the crtc_state can be safely duplicated. For now,
12169 * only fields that are know to not cause problems are preserved. */
12170
12171 tmp_state = crtc_state->base;
12172 scaler_state = crtc_state->scaler_state;
12173 shared_dpll = crtc_state->shared_dpll;
12174 dpll_hw_state = crtc_state->dpll_hw_state;
12175 ddi_pll_sel = crtc_state->ddi_pll_sel;
12176 force_thru = crtc_state->pch_pfit.force_thru;
12177
12178 memset(crtc_state, 0, sizeof *crtc_state);
12179
12180 crtc_state->base = tmp_state;
12181 crtc_state->scaler_state = scaler_state;
12182 crtc_state->shared_dpll = shared_dpll;
12183 crtc_state->dpll_hw_state = dpll_hw_state;
12184 crtc_state->ddi_pll_sel = ddi_pll_sel;
12185 crtc_state->pch_pfit.force_thru = force_thru;
12186 }
12187
12188 static int
12189 intel_modeset_pipe_config(struct drm_crtc *crtc,
12190 struct intel_crtc_state *pipe_config)
12191 {
12192 struct drm_atomic_state *state = pipe_config->base.state;
12193 struct intel_encoder *encoder;
12194 struct drm_connector *connector;
12195 struct drm_connector_state *connector_state;
12196 int base_bpp, ret = -EINVAL;
12197 int i;
12198 bool retry = true;
12199
12200 clear_intel_crtc_state(pipe_config);
12201
12202 pipe_config->cpu_transcoder =
12203 (enum transcoder) to_intel_crtc(crtc)->pipe;
12204
12205 /*
12206 * Sanitize sync polarity flags based on requested ones. If neither
12207 * positive or negative polarity is requested, treat this as meaning
12208 * negative polarity.
12209 */
12210 if (!(pipe_config->base.adjusted_mode.flags &
12211 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12212 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12213
12214 if (!(pipe_config->base.adjusted_mode.flags &
12215 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12216 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12217
12218 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12219 pipe_config);
12220 if (base_bpp < 0)
12221 goto fail;
12222
12223 /*
12224 * Determine the real pipe dimensions. Note that stereo modes can
12225 * increase the actual pipe size due to the frame doubling and
12226 * insertion of additional space for blanks between the frame. This
12227 * is stored in the crtc timings. We use the requested mode to do this
12228 * computation to clearly distinguish it from the adjusted mode, which
12229 * can be changed by the connectors in the below retry loop.
12230 */
12231 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12232 &pipe_config->pipe_src_w,
12233 &pipe_config->pipe_src_h);
12234
12235 encoder_retry:
12236 /* Ensure the port clock defaults are reset when retrying. */
12237 pipe_config->port_clock = 0;
12238 pipe_config->pixel_multiplier = 1;
12239
12240 /* Fill in default crtc timings, allow encoders to overwrite them. */
12241 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12242 CRTC_STEREO_DOUBLE);
12243
12244 /* Pass our mode to the connectors and the CRTC to give them a chance to
12245 * adjust it according to limitations or connector properties, and also
12246 * a chance to reject the mode entirely.
12247 */
12248 for_each_connector_in_state(state, connector, connector_state, i) {
12249 if (connector_state->crtc != crtc)
12250 continue;
12251
12252 encoder = to_intel_encoder(connector_state->best_encoder);
12253
12254 if (!(encoder->compute_config(encoder, pipe_config))) {
12255 DRM_DEBUG_KMS("Encoder config failure\n");
12256 goto fail;
12257 }
12258 }
12259
12260 /* Set default port clock if not overwritten by the encoder. Needs to be
12261 * done afterwards in case the encoder adjusts the mode. */
12262 if (!pipe_config->port_clock)
12263 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12264 * pipe_config->pixel_multiplier;
12265
12266 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12267 if (ret < 0) {
12268 DRM_DEBUG_KMS("CRTC fixup failed\n");
12269 goto fail;
12270 }
12271
12272 if (ret == RETRY) {
12273 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12274 ret = -EINVAL;
12275 goto fail;
12276 }
12277
12278 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12279 retry = false;
12280 goto encoder_retry;
12281 }
12282
12283 /* Dithering seems to not pass-through bits correctly when it should, so
12284 * only enable it on 6bpc panels. */
12285 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12286 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12287 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12288
12289 fail:
12290 return ret;
12291 }
12292
12293 static void
12294 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12295 {
12296 struct drm_crtc *crtc;
12297 struct drm_crtc_state *crtc_state;
12298 int i;
12299
12300 /* Double check state. */
12301 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12302 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12303
12304 /* Update hwmode for vblank functions */
12305 if (crtc->state->active)
12306 crtc->hwmode = crtc->state->adjusted_mode;
12307 else
12308 crtc->hwmode.crtc_clock = 0;
12309 }
12310 }
12311
12312 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12313 {
12314 int diff;
12315
12316 if (clock1 == clock2)
12317 return true;
12318
12319 if (!clock1 || !clock2)
12320 return false;
12321
12322 diff = abs(clock1 - clock2);
12323
12324 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12325 return true;
12326
12327 return false;
12328 }
12329
12330 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12331 list_for_each_entry((intel_crtc), \
12332 &(dev)->mode_config.crtc_list, \
12333 base.head) \
12334 if (mask & (1 <<(intel_crtc)->pipe))
12335
12336 static bool
12337 intel_compare_m_n(unsigned int m, unsigned int n,
12338 unsigned int m2, unsigned int n2,
12339 bool exact)
12340 {
12341 if (m == m2 && n == n2)
12342 return true;
12343
12344 if (exact || !m || !n || !m2 || !n2)
12345 return false;
12346
12347 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12348
12349 if (m > m2) {
12350 while (m > m2) {
12351 m2 <<= 1;
12352 n2 <<= 1;
12353 }
12354 } else if (m < m2) {
12355 while (m < m2) {
12356 m <<= 1;
12357 n <<= 1;
12358 }
12359 }
12360
12361 return m == m2 && n == n2;
12362 }
12363
12364 static bool
12365 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12366 struct intel_link_m_n *m2_n2,
12367 bool adjust)
12368 {
12369 if (m_n->tu == m2_n2->tu &&
12370 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12371 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12372 intel_compare_m_n(m_n->link_m, m_n->link_n,
12373 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12374 if (adjust)
12375 *m2_n2 = *m_n;
12376
12377 return true;
12378 }
12379
12380 return false;
12381 }
12382
12383 static bool
12384 intel_pipe_config_compare(struct drm_device *dev,
12385 struct intel_crtc_state *current_config,
12386 struct intel_crtc_state *pipe_config,
12387 bool adjust)
12388 {
12389 bool ret = true;
12390
12391 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12392 do { \
12393 if (!adjust) \
12394 DRM_ERROR(fmt, ##__VA_ARGS__); \
12395 else \
12396 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12397 } while (0)
12398
12399 #define PIPE_CONF_CHECK_X(name) \
12400 if (current_config->name != pipe_config->name) { \
12401 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12402 "(expected 0x%08x, found 0x%08x)\n", \
12403 current_config->name, \
12404 pipe_config->name); \
12405 ret = false; \
12406 }
12407
12408 #define PIPE_CONF_CHECK_I(name) \
12409 if (current_config->name != pipe_config->name) { \
12410 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12411 "(expected %i, found %i)\n", \
12412 current_config->name, \
12413 pipe_config->name); \
12414 ret = false; \
12415 }
12416
12417 #define PIPE_CONF_CHECK_M_N(name) \
12418 if (!intel_compare_link_m_n(&current_config->name, \
12419 &pipe_config->name,\
12420 adjust)) { \
12421 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12422 "(expected tu %i gmch %i/%i link %i/%i, " \
12423 "found tu %i, gmch %i/%i link %i/%i)\n", \
12424 current_config->name.tu, \
12425 current_config->name.gmch_m, \
12426 current_config->name.gmch_n, \
12427 current_config->name.link_m, \
12428 current_config->name.link_n, \
12429 pipe_config->name.tu, \
12430 pipe_config->name.gmch_m, \
12431 pipe_config->name.gmch_n, \
12432 pipe_config->name.link_m, \
12433 pipe_config->name.link_n); \
12434 ret = false; \
12435 }
12436
12437 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12438 if (!intel_compare_link_m_n(&current_config->name, \
12439 &pipe_config->name, adjust) && \
12440 !intel_compare_link_m_n(&current_config->alt_name, \
12441 &pipe_config->name, adjust)) { \
12442 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12443 "(expected tu %i gmch %i/%i link %i/%i, " \
12444 "or tu %i gmch %i/%i link %i/%i, " \
12445 "found tu %i, gmch %i/%i link %i/%i)\n", \
12446 current_config->name.tu, \
12447 current_config->name.gmch_m, \
12448 current_config->name.gmch_n, \
12449 current_config->name.link_m, \
12450 current_config->name.link_n, \
12451 current_config->alt_name.tu, \
12452 current_config->alt_name.gmch_m, \
12453 current_config->alt_name.gmch_n, \
12454 current_config->alt_name.link_m, \
12455 current_config->alt_name.link_n, \
12456 pipe_config->name.tu, \
12457 pipe_config->name.gmch_m, \
12458 pipe_config->name.gmch_n, \
12459 pipe_config->name.link_m, \
12460 pipe_config->name.link_n); \
12461 ret = false; \
12462 }
12463
12464 /* This is required for BDW+ where there is only one set of registers for
12465 * switching between high and low RR.
12466 * This macro can be used whenever a comparison has to be made between one
12467 * hw state and multiple sw state variables.
12468 */
12469 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12470 if ((current_config->name != pipe_config->name) && \
12471 (current_config->alt_name != pipe_config->name)) { \
12472 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12473 "(expected %i or %i, found %i)\n", \
12474 current_config->name, \
12475 current_config->alt_name, \
12476 pipe_config->name); \
12477 ret = false; \
12478 }
12479
12480 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12481 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12482 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12483 "(expected %i, found %i)\n", \
12484 current_config->name & (mask), \
12485 pipe_config->name & (mask)); \
12486 ret = false; \
12487 }
12488
12489 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12490 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12491 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12492 "(expected %i, found %i)\n", \
12493 current_config->name, \
12494 pipe_config->name); \
12495 ret = false; \
12496 }
12497
12498 #define PIPE_CONF_QUIRK(quirk) \
12499 ((current_config->quirks | pipe_config->quirks) & (quirk))
12500
12501 PIPE_CONF_CHECK_I(cpu_transcoder);
12502
12503 PIPE_CONF_CHECK_I(has_pch_encoder);
12504 PIPE_CONF_CHECK_I(fdi_lanes);
12505 PIPE_CONF_CHECK_M_N(fdi_m_n);
12506
12507 PIPE_CONF_CHECK_I(has_dp_encoder);
12508 PIPE_CONF_CHECK_I(lane_count);
12509
12510 if (INTEL_INFO(dev)->gen < 8) {
12511 PIPE_CONF_CHECK_M_N(dp_m_n);
12512
12513 if (current_config->has_drrs)
12514 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12515 } else
12516 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12517
12518 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12519 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12520 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12521 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12522 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12523 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12524
12525 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12526 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12527 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12528 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12529 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12530 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12531
12532 PIPE_CONF_CHECK_I(pixel_multiplier);
12533 PIPE_CONF_CHECK_I(has_hdmi_sink);
12534 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12535 IS_VALLEYVIEW(dev))
12536 PIPE_CONF_CHECK_I(limited_color_range);
12537 PIPE_CONF_CHECK_I(has_infoframe);
12538
12539 PIPE_CONF_CHECK_I(has_audio);
12540
12541 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12542 DRM_MODE_FLAG_INTERLACE);
12543
12544 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12545 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12546 DRM_MODE_FLAG_PHSYNC);
12547 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12548 DRM_MODE_FLAG_NHSYNC);
12549 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12550 DRM_MODE_FLAG_PVSYNC);
12551 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12552 DRM_MODE_FLAG_NVSYNC);
12553 }
12554
12555 PIPE_CONF_CHECK_X(gmch_pfit.control);
12556 /* pfit ratios are autocomputed by the hw on gen4+ */
12557 if (INTEL_INFO(dev)->gen < 4)
12558 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12559 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12560
12561 if (!adjust) {
12562 PIPE_CONF_CHECK_I(pipe_src_w);
12563 PIPE_CONF_CHECK_I(pipe_src_h);
12564
12565 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12566 if (current_config->pch_pfit.enabled) {
12567 PIPE_CONF_CHECK_X(pch_pfit.pos);
12568 PIPE_CONF_CHECK_X(pch_pfit.size);
12569 }
12570
12571 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12572 }
12573
12574 /* BDW+ don't expose a synchronous way to read the state */
12575 if (IS_HASWELL(dev))
12576 PIPE_CONF_CHECK_I(ips_enabled);
12577
12578 PIPE_CONF_CHECK_I(double_wide);
12579
12580 PIPE_CONF_CHECK_X(ddi_pll_sel);
12581
12582 PIPE_CONF_CHECK_I(shared_dpll);
12583 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12584 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12585 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12586 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12587 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12588 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12589 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12590 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12591 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12592
12593 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12594 PIPE_CONF_CHECK_I(pipe_bpp);
12595
12596 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12597 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12598
12599 #undef PIPE_CONF_CHECK_X
12600 #undef PIPE_CONF_CHECK_I
12601 #undef PIPE_CONF_CHECK_I_ALT
12602 #undef PIPE_CONF_CHECK_FLAGS
12603 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12604 #undef PIPE_CONF_QUIRK
12605 #undef INTEL_ERR_OR_DBG_KMS
12606
12607 return ret;
12608 }
12609
12610 static void check_wm_state(struct drm_device *dev)
12611 {
12612 struct drm_i915_private *dev_priv = dev->dev_private;
12613 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12614 struct intel_crtc *intel_crtc;
12615 int plane;
12616
12617 if (INTEL_INFO(dev)->gen < 9)
12618 return;
12619
12620 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12621 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12622
12623 for_each_intel_crtc(dev, intel_crtc) {
12624 struct skl_ddb_entry *hw_entry, *sw_entry;
12625 const enum pipe pipe = intel_crtc->pipe;
12626
12627 if (!intel_crtc->active)
12628 continue;
12629
12630 /* planes */
12631 for_each_plane(dev_priv, pipe, plane) {
12632 hw_entry = &hw_ddb.plane[pipe][plane];
12633 sw_entry = &sw_ddb->plane[pipe][plane];
12634
12635 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12636 continue;
12637
12638 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12639 "(expected (%u,%u), found (%u,%u))\n",
12640 pipe_name(pipe), plane + 1,
12641 sw_entry->start, sw_entry->end,
12642 hw_entry->start, hw_entry->end);
12643 }
12644
12645 /* cursor */
12646 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12647 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12648
12649 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12650 continue;
12651
12652 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12653 "(expected (%u,%u), found (%u,%u))\n",
12654 pipe_name(pipe),
12655 sw_entry->start, sw_entry->end,
12656 hw_entry->start, hw_entry->end);
12657 }
12658 }
12659
12660 static void
12661 check_connector_state(struct drm_device *dev,
12662 struct drm_atomic_state *old_state)
12663 {
12664 struct drm_connector_state *old_conn_state;
12665 struct drm_connector *connector;
12666 int i;
12667
12668 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12669 struct drm_encoder *encoder = connector->encoder;
12670 struct drm_connector_state *state = connector->state;
12671
12672 /* This also checks the encoder/connector hw state with the
12673 * ->get_hw_state callbacks. */
12674 intel_connector_check_state(to_intel_connector(connector));
12675
12676 I915_STATE_WARN(state->best_encoder != encoder,
12677 "connector's atomic encoder doesn't match legacy encoder\n");
12678 }
12679 }
12680
12681 static void
12682 check_encoder_state(struct drm_device *dev)
12683 {
12684 struct intel_encoder *encoder;
12685 struct intel_connector *connector;
12686
12687 for_each_intel_encoder(dev, encoder) {
12688 bool enabled = false;
12689 enum pipe pipe;
12690
12691 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12692 encoder->base.base.id,
12693 encoder->base.name);
12694
12695 for_each_intel_connector(dev, connector) {
12696 if (connector->base.state->best_encoder != &encoder->base)
12697 continue;
12698 enabled = true;
12699
12700 I915_STATE_WARN(connector->base.state->crtc !=
12701 encoder->base.crtc,
12702 "connector's crtc doesn't match encoder crtc\n");
12703 }
12704
12705 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12706 "encoder's enabled state mismatch "
12707 "(expected %i, found %i)\n",
12708 !!encoder->base.crtc, enabled);
12709
12710 if (!encoder->base.crtc) {
12711 bool active;
12712
12713 active = encoder->get_hw_state(encoder, &pipe);
12714 I915_STATE_WARN(active,
12715 "encoder detached but still enabled on pipe %c.\n",
12716 pipe_name(pipe));
12717 }
12718 }
12719 }
12720
12721 static void
12722 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12723 {
12724 struct drm_i915_private *dev_priv = dev->dev_private;
12725 struct intel_encoder *encoder;
12726 struct drm_crtc_state *old_crtc_state;
12727 struct drm_crtc *crtc;
12728 int i;
12729
12730 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12732 struct intel_crtc_state *pipe_config, *sw_config;
12733 bool active;
12734
12735 if (!needs_modeset(crtc->state) &&
12736 !to_intel_crtc_state(crtc->state)->update_pipe)
12737 continue;
12738
12739 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12740 pipe_config = to_intel_crtc_state(old_crtc_state);
12741 memset(pipe_config, 0, sizeof(*pipe_config));
12742 pipe_config->base.crtc = crtc;
12743 pipe_config->base.state = old_state;
12744
12745 DRM_DEBUG_KMS("[CRTC:%d]\n",
12746 crtc->base.id);
12747
12748 active = dev_priv->display.get_pipe_config(intel_crtc,
12749 pipe_config);
12750
12751 /* hw state is inconsistent with the pipe quirk */
12752 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12753 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12754 active = crtc->state->active;
12755
12756 I915_STATE_WARN(crtc->state->active != active,
12757 "crtc active state doesn't match with hw state "
12758 "(expected %i, found %i)\n", crtc->state->active, active);
12759
12760 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12761 "transitional active state does not match atomic hw state "
12762 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12763
12764 for_each_encoder_on_crtc(dev, crtc, encoder) {
12765 enum pipe pipe;
12766
12767 active = encoder->get_hw_state(encoder, &pipe);
12768 I915_STATE_WARN(active != crtc->state->active,
12769 "[ENCODER:%i] active %i with crtc active %i\n",
12770 encoder->base.base.id, active, crtc->state->active);
12771
12772 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12773 "Encoder connected to wrong pipe %c\n",
12774 pipe_name(pipe));
12775
12776 if (active)
12777 encoder->get_config(encoder, pipe_config);
12778 }
12779
12780 if (!crtc->state->active)
12781 continue;
12782
12783 sw_config = to_intel_crtc_state(crtc->state);
12784 if (!intel_pipe_config_compare(dev, sw_config,
12785 pipe_config, false)) {
12786 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12787 intel_dump_pipe_config(intel_crtc, pipe_config,
12788 "[hw state]");
12789 intel_dump_pipe_config(intel_crtc, sw_config,
12790 "[sw state]");
12791 }
12792 }
12793 }
12794
12795 static void
12796 check_shared_dpll_state(struct drm_device *dev)
12797 {
12798 struct drm_i915_private *dev_priv = dev->dev_private;
12799 struct intel_crtc *crtc;
12800 struct intel_dpll_hw_state dpll_hw_state;
12801 int i;
12802
12803 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12804 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12805 int enabled_crtcs = 0, active_crtcs = 0;
12806 bool active;
12807
12808 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12809
12810 DRM_DEBUG_KMS("%s\n", pll->name);
12811
12812 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12813
12814 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12815 "more active pll users than references: %i vs %i\n",
12816 pll->active, hweight32(pll->config.crtc_mask));
12817 I915_STATE_WARN(pll->active && !pll->on,
12818 "pll in active use but not on in sw tracking\n");
12819 I915_STATE_WARN(pll->on && !pll->active,
12820 "pll in on but not on in use in sw tracking\n");
12821 I915_STATE_WARN(pll->on != active,
12822 "pll on state mismatch (expected %i, found %i)\n",
12823 pll->on, active);
12824
12825 for_each_intel_crtc(dev, crtc) {
12826 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12827 enabled_crtcs++;
12828 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12829 active_crtcs++;
12830 }
12831 I915_STATE_WARN(pll->active != active_crtcs,
12832 "pll active crtcs mismatch (expected %i, found %i)\n",
12833 pll->active, active_crtcs);
12834 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12835 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12836 hweight32(pll->config.crtc_mask), enabled_crtcs);
12837
12838 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12839 sizeof(dpll_hw_state)),
12840 "pll hw state mismatch\n");
12841 }
12842 }
12843
12844 static void
12845 intel_modeset_check_state(struct drm_device *dev,
12846 struct drm_atomic_state *old_state)
12847 {
12848 check_wm_state(dev);
12849 check_connector_state(dev, old_state);
12850 check_encoder_state(dev);
12851 check_crtc_state(dev, old_state);
12852 check_shared_dpll_state(dev);
12853 }
12854
12855 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12856 int dotclock)
12857 {
12858 /*
12859 * FDI already provided one idea for the dotclock.
12860 * Yell if the encoder disagrees.
12861 */
12862 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12863 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12864 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12865 }
12866
12867 static void update_scanline_offset(struct intel_crtc *crtc)
12868 {
12869 struct drm_device *dev = crtc->base.dev;
12870
12871 /*
12872 * The scanline counter increments at the leading edge of hsync.
12873 *
12874 * On most platforms it starts counting from vtotal-1 on the
12875 * first active line. That means the scanline counter value is
12876 * always one less than what we would expect. Ie. just after
12877 * start of vblank, which also occurs at start of hsync (on the
12878 * last active line), the scanline counter will read vblank_start-1.
12879 *
12880 * On gen2 the scanline counter starts counting from 1 instead
12881 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12882 * to keep the value positive), instead of adding one.
12883 *
12884 * On HSW+ the behaviour of the scanline counter depends on the output
12885 * type. For DP ports it behaves like most other platforms, but on HDMI
12886 * there's an extra 1 line difference. So we need to add two instead of
12887 * one to the value.
12888 */
12889 if (IS_GEN2(dev)) {
12890 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12891 int vtotal;
12892
12893 vtotal = adjusted_mode->crtc_vtotal;
12894 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12895 vtotal /= 2;
12896
12897 crtc->scanline_offset = vtotal - 1;
12898 } else if (HAS_DDI(dev) &&
12899 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12900 crtc->scanline_offset = 2;
12901 } else
12902 crtc->scanline_offset = 1;
12903 }
12904
12905 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12906 {
12907 struct drm_device *dev = state->dev;
12908 struct drm_i915_private *dev_priv = to_i915(dev);
12909 struct intel_shared_dpll_config *shared_dpll = NULL;
12910 struct intel_crtc *intel_crtc;
12911 struct intel_crtc_state *intel_crtc_state;
12912 struct drm_crtc *crtc;
12913 struct drm_crtc_state *crtc_state;
12914 int i;
12915
12916 if (!dev_priv->display.crtc_compute_clock)
12917 return;
12918
12919 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12920 int dpll;
12921
12922 intel_crtc = to_intel_crtc(crtc);
12923 intel_crtc_state = to_intel_crtc_state(crtc_state);
12924 dpll = intel_crtc_state->shared_dpll;
12925
12926 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12927 continue;
12928
12929 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12930
12931 if (!shared_dpll)
12932 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12933
12934 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12935 }
12936 }
12937
12938 /*
12939 * This implements the workaround described in the "notes" section of the mode
12940 * set sequence documentation. When going from no pipes or single pipe to
12941 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12942 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12943 */
12944 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12945 {
12946 struct drm_crtc_state *crtc_state;
12947 struct intel_crtc *intel_crtc;
12948 struct drm_crtc *crtc;
12949 struct intel_crtc_state *first_crtc_state = NULL;
12950 struct intel_crtc_state *other_crtc_state = NULL;
12951 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12952 int i;
12953
12954 /* look at all crtc's that are going to be enabled in during modeset */
12955 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12956 intel_crtc = to_intel_crtc(crtc);
12957
12958 if (!crtc_state->active || !needs_modeset(crtc_state))
12959 continue;
12960
12961 if (first_crtc_state) {
12962 other_crtc_state = to_intel_crtc_state(crtc_state);
12963 break;
12964 } else {
12965 first_crtc_state = to_intel_crtc_state(crtc_state);
12966 first_pipe = intel_crtc->pipe;
12967 }
12968 }
12969
12970 /* No workaround needed? */
12971 if (!first_crtc_state)
12972 return 0;
12973
12974 /* w/a possibly needed, check how many crtc's are already enabled. */
12975 for_each_intel_crtc(state->dev, intel_crtc) {
12976 struct intel_crtc_state *pipe_config;
12977
12978 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12979 if (IS_ERR(pipe_config))
12980 return PTR_ERR(pipe_config);
12981
12982 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12983
12984 if (!pipe_config->base.active ||
12985 needs_modeset(&pipe_config->base))
12986 continue;
12987
12988 /* 2 or more enabled crtcs means no need for w/a */
12989 if (enabled_pipe != INVALID_PIPE)
12990 return 0;
12991
12992 enabled_pipe = intel_crtc->pipe;
12993 }
12994
12995 if (enabled_pipe != INVALID_PIPE)
12996 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12997 else if (other_crtc_state)
12998 other_crtc_state->hsw_workaround_pipe = first_pipe;
12999
13000 return 0;
13001 }
13002
13003 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13004 {
13005 struct drm_crtc *crtc;
13006 struct drm_crtc_state *crtc_state;
13007 int ret = 0;
13008
13009 /* add all active pipes to the state */
13010 for_each_crtc(state->dev, crtc) {
13011 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13012 if (IS_ERR(crtc_state))
13013 return PTR_ERR(crtc_state);
13014
13015 if (!crtc_state->active || needs_modeset(crtc_state))
13016 continue;
13017
13018 crtc_state->mode_changed = true;
13019
13020 ret = drm_atomic_add_affected_connectors(state, crtc);
13021 if (ret)
13022 break;
13023
13024 ret = drm_atomic_add_affected_planes(state, crtc);
13025 if (ret)
13026 break;
13027 }
13028
13029 return ret;
13030 }
13031
13032 static int intel_modeset_checks(struct drm_atomic_state *state)
13033 {
13034 struct drm_device *dev = state->dev;
13035 struct drm_i915_private *dev_priv = dev->dev_private;
13036 int ret;
13037
13038 if (!check_digital_port_conflicts(state)) {
13039 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13040 return -EINVAL;
13041 }
13042
13043 /*
13044 * See if the config requires any additional preparation, e.g.
13045 * to adjust global state with pipes off. We need to do this
13046 * here so we can get the modeset_pipe updated config for the new
13047 * mode set on this crtc. For other crtcs we need to use the
13048 * adjusted_mode bits in the crtc directly.
13049 */
13050 if (dev_priv->display.modeset_calc_cdclk) {
13051 unsigned int cdclk;
13052
13053 ret = dev_priv->display.modeset_calc_cdclk(state);
13054
13055 cdclk = to_intel_atomic_state(state)->cdclk;
13056 if (!ret && cdclk != dev_priv->cdclk_freq)
13057 ret = intel_modeset_all_pipes(state);
13058
13059 if (ret < 0)
13060 return ret;
13061 } else
13062 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13063
13064 intel_modeset_clear_plls(state);
13065
13066 if (IS_HASWELL(dev))
13067 return haswell_mode_set_planes_workaround(state);
13068
13069 return 0;
13070 }
13071
13072 /**
13073 * intel_atomic_check - validate state object
13074 * @dev: drm device
13075 * @state: state to validate
13076 */
13077 static int intel_atomic_check(struct drm_device *dev,
13078 struct drm_atomic_state *state)
13079 {
13080 struct drm_crtc *crtc;
13081 struct drm_crtc_state *crtc_state;
13082 int ret, i;
13083 bool any_ms = false;
13084
13085 ret = drm_atomic_helper_check_modeset(dev, state);
13086 if (ret)
13087 return ret;
13088
13089 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13090 struct intel_crtc_state *pipe_config =
13091 to_intel_crtc_state(crtc_state);
13092
13093 memset(&to_intel_crtc(crtc)->atomic, 0,
13094 sizeof(struct intel_crtc_atomic_commit));
13095
13096 /* Catch I915_MODE_FLAG_INHERITED */
13097 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13098 crtc_state->mode_changed = true;
13099
13100 if (!crtc_state->enable) {
13101 if (needs_modeset(crtc_state))
13102 any_ms = true;
13103 continue;
13104 }
13105
13106 if (!needs_modeset(crtc_state))
13107 continue;
13108
13109 /* FIXME: For only active_changed we shouldn't need to do any
13110 * state recomputation at all. */
13111
13112 ret = drm_atomic_add_affected_connectors(state, crtc);
13113 if (ret)
13114 return ret;
13115
13116 ret = intel_modeset_pipe_config(crtc, pipe_config);
13117 if (ret)
13118 return ret;
13119
13120 if (i915.fastboot &&
13121 intel_pipe_config_compare(state->dev,
13122 to_intel_crtc_state(crtc->state),
13123 pipe_config, true)) {
13124 crtc_state->mode_changed = false;
13125 to_intel_crtc_state(crtc_state)->update_pipe = true;
13126 }
13127
13128 if (needs_modeset(crtc_state)) {
13129 any_ms = true;
13130
13131 ret = drm_atomic_add_affected_planes(state, crtc);
13132 if (ret)
13133 return ret;
13134 }
13135
13136 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13137 needs_modeset(crtc_state) ?
13138 "[modeset]" : "[fastset]");
13139 }
13140
13141 if (any_ms) {
13142 ret = intel_modeset_checks(state);
13143
13144 if (ret)
13145 return ret;
13146 } else
13147 to_intel_atomic_state(state)->cdclk =
13148 to_i915(state->dev)->cdclk_freq;
13149
13150 return drm_atomic_helper_check_planes(state->dev, state);
13151 }
13152
13153 /**
13154 * intel_atomic_commit - commit validated state object
13155 * @dev: DRM device
13156 * @state: the top-level driver state object
13157 * @async: asynchronous commit
13158 *
13159 * This function commits a top-level state object that has been validated
13160 * with drm_atomic_helper_check().
13161 *
13162 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13163 * we can only handle plane-related operations and do not yet support
13164 * asynchronous commit.
13165 *
13166 * RETURNS
13167 * Zero for success or -errno.
13168 */
13169 static int intel_atomic_commit(struct drm_device *dev,
13170 struct drm_atomic_state *state,
13171 bool async)
13172 {
13173 struct drm_i915_private *dev_priv = dev->dev_private;
13174 struct drm_crtc *crtc;
13175 struct drm_crtc_state *crtc_state;
13176 int ret = 0;
13177 int i;
13178 bool any_ms = false;
13179
13180 if (async) {
13181 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13182 return -EINVAL;
13183 }
13184
13185 ret = drm_atomic_helper_prepare_planes(dev, state);
13186 if (ret)
13187 return ret;
13188
13189 drm_atomic_helper_swap_state(dev, state);
13190
13191 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13193
13194 if (!needs_modeset(crtc->state))
13195 continue;
13196
13197 any_ms = true;
13198 intel_pre_plane_update(intel_crtc);
13199
13200 if (crtc_state->active) {
13201 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13202 dev_priv->display.crtc_disable(crtc);
13203 intel_crtc->active = false;
13204 intel_disable_shared_dpll(intel_crtc);
13205 }
13206 }
13207
13208 /* Only after disabling all output pipelines that will be changed can we
13209 * update the the output configuration. */
13210 intel_modeset_update_crtc_state(state);
13211
13212 if (any_ms) {
13213 intel_shared_dpll_commit(state);
13214
13215 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13216 modeset_update_crtc_power_domains(state);
13217 }
13218
13219 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13220 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13222 bool modeset = needs_modeset(crtc->state);
13223 bool update_pipe = !modeset &&
13224 to_intel_crtc_state(crtc->state)->update_pipe;
13225 unsigned long put_domains = 0;
13226
13227 if (modeset && crtc->state->active) {
13228 update_scanline_offset(to_intel_crtc(crtc));
13229 dev_priv->display.crtc_enable(crtc);
13230 }
13231
13232 if (update_pipe) {
13233 put_domains = modeset_get_crtc_power_domains(crtc);
13234
13235 /* make sure intel_modeset_check_state runs */
13236 any_ms = true;
13237 }
13238
13239 if (!modeset)
13240 intel_pre_plane_update(intel_crtc);
13241
13242 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13243
13244 if (put_domains)
13245 modeset_put_power_domains(dev_priv, put_domains);
13246
13247 intel_post_plane_update(intel_crtc);
13248 }
13249
13250 /* FIXME: add subpixel order */
13251
13252 drm_atomic_helper_wait_for_vblanks(dev, state);
13253 drm_atomic_helper_cleanup_planes(dev, state);
13254
13255 if (any_ms)
13256 intel_modeset_check_state(dev, state);
13257
13258 drm_atomic_state_free(state);
13259
13260 return 0;
13261 }
13262
13263 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13264 {
13265 struct drm_device *dev = crtc->dev;
13266 struct drm_atomic_state *state;
13267 struct drm_crtc_state *crtc_state;
13268 int ret;
13269
13270 state = drm_atomic_state_alloc(dev);
13271 if (!state) {
13272 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13273 crtc->base.id);
13274 return;
13275 }
13276
13277 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13278
13279 retry:
13280 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13281 ret = PTR_ERR_OR_ZERO(crtc_state);
13282 if (!ret) {
13283 if (!crtc_state->active)
13284 goto out;
13285
13286 crtc_state->mode_changed = true;
13287 ret = drm_atomic_commit(state);
13288 }
13289
13290 if (ret == -EDEADLK) {
13291 drm_atomic_state_clear(state);
13292 drm_modeset_backoff(state->acquire_ctx);
13293 goto retry;
13294 }
13295
13296 if (ret)
13297 out:
13298 drm_atomic_state_free(state);
13299 }
13300
13301 #undef for_each_intel_crtc_masked
13302
13303 static const struct drm_crtc_funcs intel_crtc_funcs = {
13304 .gamma_set = intel_crtc_gamma_set,
13305 .set_config = drm_atomic_helper_set_config,
13306 .destroy = intel_crtc_destroy,
13307 .page_flip = intel_crtc_page_flip,
13308 .atomic_duplicate_state = intel_crtc_duplicate_state,
13309 .atomic_destroy_state = intel_crtc_destroy_state,
13310 };
13311
13312 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13313 struct intel_shared_dpll *pll,
13314 struct intel_dpll_hw_state *hw_state)
13315 {
13316 uint32_t val;
13317
13318 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13319 return false;
13320
13321 val = I915_READ(PCH_DPLL(pll->id));
13322 hw_state->dpll = val;
13323 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13324 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13325
13326 return val & DPLL_VCO_ENABLE;
13327 }
13328
13329 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13330 struct intel_shared_dpll *pll)
13331 {
13332 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13333 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13334 }
13335
13336 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13337 struct intel_shared_dpll *pll)
13338 {
13339 /* PCH refclock must be enabled first */
13340 ibx_assert_pch_refclk_enabled(dev_priv);
13341
13342 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13343
13344 /* Wait for the clocks to stabilize. */
13345 POSTING_READ(PCH_DPLL(pll->id));
13346 udelay(150);
13347
13348 /* The pixel multiplier can only be updated once the
13349 * DPLL is enabled and the clocks are stable.
13350 *
13351 * So write it again.
13352 */
13353 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13354 POSTING_READ(PCH_DPLL(pll->id));
13355 udelay(200);
13356 }
13357
13358 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13359 struct intel_shared_dpll *pll)
13360 {
13361 struct drm_device *dev = dev_priv->dev;
13362 struct intel_crtc *crtc;
13363
13364 /* Make sure no transcoder isn't still depending on us. */
13365 for_each_intel_crtc(dev, crtc) {
13366 if (intel_crtc_to_shared_dpll(crtc) == pll)
13367 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13368 }
13369
13370 I915_WRITE(PCH_DPLL(pll->id), 0);
13371 POSTING_READ(PCH_DPLL(pll->id));
13372 udelay(200);
13373 }
13374
13375 static char *ibx_pch_dpll_names[] = {
13376 "PCH DPLL A",
13377 "PCH DPLL B",
13378 };
13379
13380 static void ibx_pch_dpll_init(struct drm_device *dev)
13381 {
13382 struct drm_i915_private *dev_priv = dev->dev_private;
13383 int i;
13384
13385 dev_priv->num_shared_dpll = 2;
13386
13387 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13388 dev_priv->shared_dplls[i].id = i;
13389 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13390 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13391 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13392 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13393 dev_priv->shared_dplls[i].get_hw_state =
13394 ibx_pch_dpll_get_hw_state;
13395 }
13396 }
13397
13398 static void intel_shared_dpll_init(struct drm_device *dev)
13399 {
13400 struct drm_i915_private *dev_priv = dev->dev_private;
13401
13402 if (HAS_DDI(dev))
13403 intel_ddi_pll_init(dev);
13404 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13405 ibx_pch_dpll_init(dev);
13406 else
13407 dev_priv->num_shared_dpll = 0;
13408
13409 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13410 }
13411
13412 /**
13413 * intel_prepare_plane_fb - Prepare fb for usage on plane
13414 * @plane: drm plane to prepare for
13415 * @fb: framebuffer to prepare for presentation
13416 *
13417 * Prepares a framebuffer for usage on a display plane. Generally this
13418 * involves pinning the underlying object and updating the frontbuffer tracking
13419 * bits. Some older platforms need special physical address handling for
13420 * cursor planes.
13421 *
13422 * Returns 0 on success, negative error code on failure.
13423 */
13424 int
13425 intel_prepare_plane_fb(struct drm_plane *plane,
13426 const struct drm_plane_state *new_state)
13427 {
13428 struct drm_device *dev = plane->dev;
13429 struct drm_framebuffer *fb = new_state->fb;
13430 struct intel_plane *intel_plane = to_intel_plane(plane);
13431 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13432 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13433 int ret = 0;
13434
13435 if (!obj)
13436 return 0;
13437
13438 mutex_lock(&dev->struct_mutex);
13439
13440 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13441 INTEL_INFO(dev)->cursor_needs_physical) {
13442 int align = IS_I830(dev) ? 16 * 1024 : 256;
13443 ret = i915_gem_object_attach_phys(obj, align);
13444 if (ret)
13445 DRM_DEBUG_KMS("failed to attach phys object\n");
13446 } else {
13447 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13448 }
13449
13450 if (ret == 0)
13451 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13452
13453 mutex_unlock(&dev->struct_mutex);
13454
13455 return ret;
13456 }
13457
13458 /**
13459 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13460 * @plane: drm plane to clean up for
13461 * @fb: old framebuffer that was on plane
13462 *
13463 * Cleans up a framebuffer that has just been removed from a plane.
13464 */
13465 void
13466 intel_cleanup_plane_fb(struct drm_plane *plane,
13467 const struct drm_plane_state *old_state)
13468 {
13469 struct drm_device *dev = plane->dev;
13470 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13471
13472 if (!obj)
13473 return;
13474
13475 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13476 !INTEL_INFO(dev)->cursor_needs_physical) {
13477 mutex_lock(&dev->struct_mutex);
13478 intel_unpin_fb_obj(old_state->fb, old_state);
13479 mutex_unlock(&dev->struct_mutex);
13480 }
13481 }
13482
13483 int
13484 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13485 {
13486 int max_scale;
13487 struct drm_device *dev;
13488 struct drm_i915_private *dev_priv;
13489 int crtc_clock, cdclk;
13490
13491 if (!intel_crtc || !crtc_state)
13492 return DRM_PLANE_HELPER_NO_SCALING;
13493
13494 dev = intel_crtc->base.dev;
13495 dev_priv = dev->dev_private;
13496 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13497 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13498
13499 if (!crtc_clock || !cdclk)
13500 return DRM_PLANE_HELPER_NO_SCALING;
13501
13502 /*
13503 * skl max scale is lower of:
13504 * close to 3 but not 3, -1 is for that purpose
13505 * or
13506 * cdclk/crtc_clock
13507 */
13508 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13509
13510 return max_scale;
13511 }
13512
13513 static int
13514 intel_check_primary_plane(struct drm_plane *plane,
13515 struct intel_crtc_state *crtc_state,
13516 struct intel_plane_state *state)
13517 {
13518 struct drm_crtc *crtc = state->base.crtc;
13519 struct drm_framebuffer *fb = state->base.fb;
13520 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13521 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13522 bool can_position = false;
13523
13524 /* use scaler when colorkey is not required */
13525 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13526 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13527 min_scale = 1;
13528 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13529 can_position = true;
13530 }
13531
13532 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13533 &state->dst, &state->clip,
13534 min_scale, max_scale,
13535 can_position, true,
13536 &state->visible);
13537 }
13538
13539 static void
13540 intel_commit_primary_plane(struct drm_plane *plane,
13541 struct intel_plane_state *state)
13542 {
13543 struct drm_crtc *crtc = state->base.crtc;
13544 struct drm_framebuffer *fb = state->base.fb;
13545 struct drm_device *dev = plane->dev;
13546 struct drm_i915_private *dev_priv = dev->dev_private;
13547 struct intel_crtc *intel_crtc;
13548 struct drm_rect *src = &state->src;
13549
13550 crtc = crtc ? crtc : plane->crtc;
13551 intel_crtc = to_intel_crtc(crtc);
13552
13553 plane->fb = fb;
13554 crtc->x = src->x1 >> 16;
13555 crtc->y = src->y1 >> 16;
13556
13557 if (!crtc->state->active)
13558 return;
13559
13560 dev_priv->display.update_primary_plane(crtc, fb,
13561 state->src.x1 >> 16,
13562 state->src.y1 >> 16);
13563 }
13564
13565 static void
13566 intel_disable_primary_plane(struct drm_plane *plane,
13567 struct drm_crtc *crtc)
13568 {
13569 struct drm_device *dev = plane->dev;
13570 struct drm_i915_private *dev_priv = dev->dev_private;
13571
13572 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13573 }
13574
13575 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13576 struct drm_crtc_state *old_crtc_state)
13577 {
13578 struct drm_device *dev = crtc->dev;
13579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13580 struct intel_crtc_state *old_intel_state =
13581 to_intel_crtc_state(old_crtc_state);
13582 bool modeset = needs_modeset(crtc->state);
13583
13584 if (intel_crtc->atomic.update_wm_pre)
13585 intel_update_watermarks(crtc);
13586
13587 /* Perform vblank evasion around commit operation */
13588 if (crtc->state->active)
13589 intel_pipe_update_start(intel_crtc);
13590
13591 if (modeset)
13592 return;
13593
13594 if (to_intel_crtc_state(crtc->state)->update_pipe)
13595 intel_update_pipe_config(intel_crtc, old_intel_state);
13596 else if (INTEL_INFO(dev)->gen >= 9)
13597 skl_detach_scalers(intel_crtc);
13598 }
13599
13600 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13601 struct drm_crtc_state *old_crtc_state)
13602 {
13603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13604
13605 if (crtc->state->active)
13606 intel_pipe_update_end(intel_crtc);
13607 }
13608
13609 /**
13610 * intel_plane_destroy - destroy a plane
13611 * @plane: plane to destroy
13612 *
13613 * Common destruction function for all types of planes (primary, cursor,
13614 * sprite).
13615 */
13616 void intel_plane_destroy(struct drm_plane *plane)
13617 {
13618 struct intel_plane *intel_plane = to_intel_plane(plane);
13619 drm_plane_cleanup(plane);
13620 kfree(intel_plane);
13621 }
13622
13623 const struct drm_plane_funcs intel_plane_funcs = {
13624 .update_plane = drm_atomic_helper_update_plane,
13625 .disable_plane = drm_atomic_helper_disable_plane,
13626 .destroy = intel_plane_destroy,
13627 .set_property = drm_atomic_helper_plane_set_property,
13628 .atomic_get_property = intel_plane_atomic_get_property,
13629 .atomic_set_property = intel_plane_atomic_set_property,
13630 .atomic_duplicate_state = intel_plane_duplicate_state,
13631 .atomic_destroy_state = intel_plane_destroy_state,
13632
13633 };
13634
13635 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13636 int pipe)
13637 {
13638 struct intel_plane *primary;
13639 struct intel_plane_state *state;
13640 const uint32_t *intel_primary_formats;
13641 unsigned int num_formats;
13642
13643 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13644 if (primary == NULL)
13645 return NULL;
13646
13647 state = intel_create_plane_state(&primary->base);
13648 if (!state) {
13649 kfree(primary);
13650 return NULL;
13651 }
13652 primary->base.state = &state->base;
13653
13654 primary->can_scale = false;
13655 primary->max_downscale = 1;
13656 if (INTEL_INFO(dev)->gen >= 9) {
13657 primary->can_scale = true;
13658 state->scaler_id = -1;
13659 }
13660 primary->pipe = pipe;
13661 primary->plane = pipe;
13662 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13663 primary->check_plane = intel_check_primary_plane;
13664 primary->commit_plane = intel_commit_primary_plane;
13665 primary->disable_plane = intel_disable_primary_plane;
13666 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13667 primary->plane = !pipe;
13668
13669 if (INTEL_INFO(dev)->gen >= 9) {
13670 intel_primary_formats = skl_primary_formats;
13671 num_formats = ARRAY_SIZE(skl_primary_formats);
13672 } else if (INTEL_INFO(dev)->gen >= 4) {
13673 intel_primary_formats = i965_primary_formats;
13674 num_formats = ARRAY_SIZE(i965_primary_formats);
13675 } else {
13676 intel_primary_formats = i8xx_primary_formats;
13677 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13678 }
13679
13680 drm_universal_plane_init(dev, &primary->base, 0,
13681 &intel_plane_funcs,
13682 intel_primary_formats, num_formats,
13683 DRM_PLANE_TYPE_PRIMARY);
13684
13685 if (INTEL_INFO(dev)->gen >= 4)
13686 intel_create_rotation_property(dev, primary);
13687
13688 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13689
13690 return &primary->base;
13691 }
13692
13693 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13694 {
13695 if (!dev->mode_config.rotation_property) {
13696 unsigned long flags = BIT(DRM_ROTATE_0) |
13697 BIT(DRM_ROTATE_180);
13698
13699 if (INTEL_INFO(dev)->gen >= 9)
13700 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13701
13702 dev->mode_config.rotation_property =
13703 drm_mode_create_rotation_property(dev, flags);
13704 }
13705 if (dev->mode_config.rotation_property)
13706 drm_object_attach_property(&plane->base.base,
13707 dev->mode_config.rotation_property,
13708 plane->base.state->rotation);
13709 }
13710
13711 static int
13712 intel_check_cursor_plane(struct drm_plane *plane,
13713 struct intel_crtc_state *crtc_state,
13714 struct intel_plane_state *state)
13715 {
13716 struct drm_crtc *crtc = crtc_state->base.crtc;
13717 struct drm_framebuffer *fb = state->base.fb;
13718 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13719 unsigned stride;
13720 int ret;
13721
13722 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13723 &state->dst, &state->clip,
13724 DRM_PLANE_HELPER_NO_SCALING,
13725 DRM_PLANE_HELPER_NO_SCALING,
13726 true, true, &state->visible);
13727 if (ret)
13728 return ret;
13729
13730 /* if we want to turn off the cursor ignore width and height */
13731 if (!obj)
13732 return 0;
13733
13734 /* Check for which cursor types we support */
13735 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13736 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13737 state->base.crtc_w, state->base.crtc_h);
13738 return -EINVAL;
13739 }
13740
13741 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13742 if (obj->base.size < stride * state->base.crtc_h) {
13743 DRM_DEBUG_KMS("buffer is too small\n");
13744 return -ENOMEM;
13745 }
13746
13747 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13748 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13749 return -EINVAL;
13750 }
13751
13752 return 0;
13753 }
13754
13755 static void
13756 intel_disable_cursor_plane(struct drm_plane *plane,
13757 struct drm_crtc *crtc)
13758 {
13759 intel_crtc_update_cursor(crtc, false);
13760 }
13761
13762 static void
13763 intel_commit_cursor_plane(struct drm_plane *plane,
13764 struct intel_plane_state *state)
13765 {
13766 struct drm_crtc *crtc = state->base.crtc;
13767 struct drm_device *dev = plane->dev;
13768 struct intel_crtc *intel_crtc;
13769 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13770 uint32_t addr;
13771
13772 crtc = crtc ? crtc : plane->crtc;
13773 intel_crtc = to_intel_crtc(crtc);
13774
13775 if (intel_crtc->cursor_bo == obj)
13776 goto update;
13777
13778 if (!obj)
13779 addr = 0;
13780 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13781 addr = i915_gem_obj_ggtt_offset(obj);
13782 else
13783 addr = obj->phys_handle->busaddr;
13784
13785 intel_crtc->cursor_addr = addr;
13786 intel_crtc->cursor_bo = obj;
13787
13788 update:
13789 if (crtc->state->active)
13790 intel_crtc_update_cursor(crtc, state->visible);
13791 }
13792
13793 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13794 int pipe)
13795 {
13796 struct intel_plane *cursor;
13797 struct intel_plane_state *state;
13798
13799 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13800 if (cursor == NULL)
13801 return NULL;
13802
13803 state = intel_create_plane_state(&cursor->base);
13804 if (!state) {
13805 kfree(cursor);
13806 return NULL;
13807 }
13808 cursor->base.state = &state->base;
13809
13810 cursor->can_scale = false;
13811 cursor->max_downscale = 1;
13812 cursor->pipe = pipe;
13813 cursor->plane = pipe;
13814 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13815 cursor->check_plane = intel_check_cursor_plane;
13816 cursor->commit_plane = intel_commit_cursor_plane;
13817 cursor->disable_plane = intel_disable_cursor_plane;
13818
13819 drm_universal_plane_init(dev, &cursor->base, 0,
13820 &intel_plane_funcs,
13821 intel_cursor_formats,
13822 ARRAY_SIZE(intel_cursor_formats),
13823 DRM_PLANE_TYPE_CURSOR);
13824
13825 if (INTEL_INFO(dev)->gen >= 4) {
13826 if (!dev->mode_config.rotation_property)
13827 dev->mode_config.rotation_property =
13828 drm_mode_create_rotation_property(dev,
13829 BIT(DRM_ROTATE_0) |
13830 BIT(DRM_ROTATE_180));
13831 if (dev->mode_config.rotation_property)
13832 drm_object_attach_property(&cursor->base.base,
13833 dev->mode_config.rotation_property,
13834 state->base.rotation);
13835 }
13836
13837 if (INTEL_INFO(dev)->gen >=9)
13838 state->scaler_id = -1;
13839
13840 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13841
13842 return &cursor->base;
13843 }
13844
13845 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13846 struct intel_crtc_state *crtc_state)
13847 {
13848 int i;
13849 struct intel_scaler *intel_scaler;
13850 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13851
13852 for (i = 0; i < intel_crtc->num_scalers; i++) {
13853 intel_scaler = &scaler_state->scalers[i];
13854 intel_scaler->in_use = 0;
13855 intel_scaler->mode = PS_SCALER_MODE_DYN;
13856 }
13857
13858 scaler_state->scaler_id = -1;
13859 }
13860
13861 static void intel_crtc_init(struct drm_device *dev, int pipe)
13862 {
13863 struct drm_i915_private *dev_priv = dev->dev_private;
13864 struct intel_crtc *intel_crtc;
13865 struct intel_crtc_state *crtc_state = NULL;
13866 struct drm_plane *primary = NULL;
13867 struct drm_plane *cursor = NULL;
13868 int i, ret;
13869
13870 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13871 if (intel_crtc == NULL)
13872 return;
13873
13874 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13875 if (!crtc_state)
13876 goto fail;
13877 intel_crtc->config = crtc_state;
13878 intel_crtc->base.state = &crtc_state->base;
13879 crtc_state->base.crtc = &intel_crtc->base;
13880
13881 /* initialize shared scalers */
13882 if (INTEL_INFO(dev)->gen >= 9) {
13883 if (pipe == PIPE_C)
13884 intel_crtc->num_scalers = 1;
13885 else
13886 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13887
13888 skl_init_scalers(dev, intel_crtc, crtc_state);
13889 }
13890
13891 primary = intel_primary_plane_create(dev, pipe);
13892 if (!primary)
13893 goto fail;
13894
13895 cursor = intel_cursor_plane_create(dev, pipe);
13896 if (!cursor)
13897 goto fail;
13898
13899 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13900 cursor, &intel_crtc_funcs);
13901 if (ret)
13902 goto fail;
13903
13904 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13905 for (i = 0; i < 256; i++) {
13906 intel_crtc->lut_r[i] = i;
13907 intel_crtc->lut_g[i] = i;
13908 intel_crtc->lut_b[i] = i;
13909 }
13910
13911 /*
13912 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13913 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13914 */
13915 intel_crtc->pipe = pipe;
13916 intel_crtc->plane = pipe;
13917 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13918 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13919 intel_crtc->plane = !pipe;
13920 }
13921
13922 intel_crtc->cursor_base = ~0;
13923 intel_crtc->cursor_cntl = ~0;
13924 intel_crtc->cursor_size = ~0;
13925
13926 intel_crtc->wm.cxsr_allowed = true;
13927
13928 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13929 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13930 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13931 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13932
13933 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13934
13935 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13936 return;
13937
13938 fail:
13939 if (primary)
13940 drm_plane_cleanup(primary);
13941 if (cursor)
13942 drm_plane_cleanup(cursor);
13943 kfree(crtc_state);
13944 kfree(intel_crtc);
13945 }
13946
13947 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13948 {
13949 struct drm_encoder *encoder = connector->base.encoder;
13950 struct drm_device *dev = connector->base.dev;
13951
13952 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13953
13954 if (!encoder || WARN_ON(!encoder->crtc))
13955 return INVALID_PIPE;
13956
13957 return to_intel_crtc(encoder->crtc)->pipe;
13958 }
13959
13960 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13961 struct drm_file *file)
13962 {
13963 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13964 struct drm_crtc *drmmode_crtc;
13965 struct intel_crtc *crtc;
13966
13967 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13968
13969 if (!drmmode_crtc) {
13970 DRM_ERROR("no such CRTC id\n");
13971 return -ENOENT;
13972 }
13973
13974 crtc = to_intel_crtc(drmmode_crtc);
13975 pipe_from_crtc_id->pipe = crtc->pipe;
13976
13977 return 0;
13978 }
13979
13980 static int intel_encoder_clones(struct intel_encoder *encoder)
13981 {
13982 struct drm_device *dev = encoder->base.dev;
13983 struct intel_encoder *source_encoder;
13984 int index_mask = 0;
13985 int entry = 0;
13986
13987 for_each_intel_encoder(dev, source_encoder) {
13988 if (encoders_cloneable(encoder, source_encoder))
13989 index_mask |= (1 << entry);
13990
13991 entry++;
13992 }
13993
13994 return index_mask;
13995 }
13996
13997 static bool has_edp_a(struct drm_device *dev)
13998 {
13999 struct drm_i915_private *dev_priv = dev->dev_private;
14000
14001 if (!IS_MOBILE(dev))
14002 return false;
14003
14004 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14005 return false;
14006
14007 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14008 return false;
14009
14010 return true;
14011 }
14012
14013 static bool intel_crt_present(struct drm_device *dev)
14014 {
14015 struct drm_i915_private *dev_priv = dev->dev_private;
14016
14017 if (INTEL_INFO(dev)->gen >= 9)
14018 return false;
14019
14020 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14021 return false;
14022
14023 if (IS_CHERRYVIEW(dev))
14024 return false;
14025
14026 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14027 return false;
14028
14029 return true;
14030 }
14031
14032 static void intel_setup_outputs(struct drm_device *dev)
14033 {
14034 struct drm_i915_private *dev_priv = dev->dev_private;
14035 struct intel_encoder *encoder;
14036 bool dpd_is_edp = false;
14037
14038 intel_lvds_init(dev);
14039
14040 if (intel_crt_present(dev))
14041 intel_crt_init(dev);
14042
14043 if (IS_BROXTON(dev)) {
14044 /*
14045 * FIXME: Broxton doesn't support port detection via the
14046 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14047 * detect the ports.
14048 */
14049 intel_ddi_init(dev, PORT_A);
14050 intel_ddi_init(dev, PORT_B);
14051 intel_ddi_init(dev, PORT_C);
14052 } else if (HAS_DDI(dev)) {
14053 int found;
14054
14055 /*
14056 * Haswell uses DDI functions to detect digital outputs.
14057 * On SKL pre-D0 the strap isn't connected, so we assume
14058 * it's there.
14059 */
14060 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14061 /* WaIgnoreDDIAStrap: skl */
14062 if (found || IS_SKYLAKE(dev))
14063 intel_ddi_init(dev, PORT_A);
14064
14065 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14066 * register */
14067 found = I915_READ(SFUSE_STRAP);
14068
14069 if (found & SFUSE_STRAP_DDIB_DETECTED)
14070 intel_ddi_init(dev, PORT_B);
14071 if (found & SFUSE_STRAP_DDIC_DETECTED)
14072 intel_ddi_init(dev, PORT_C);
14073 if (found & SFUSE_STRAP_DDID_DETECTED)
14074 intel_ddi_init(dev, PORT_D);
14075 /*
14076 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14077 */
14078 if (IS_SKYLAKE(dev) &&
14079 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14080 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14081 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14082 intel_ddi_init(dev, PORT_E);
14083
14084 } else if (HAS_PCH_SPLIT(dev)) {
14085 int found;
14086 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14087
14088 if (has_edp_a(dev))
14089 intel_dp_init(dev, DP_A, PORT_A);
14090
14091 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14092 /* PCH SDVOB multiplex with HDMIB */
14093 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14094 if (!found)
14095 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14096 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14097 intel_dp_init(dev, PCH_DP_B, PORT_B);
14098 }
14099
14100 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14101 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14102
14103 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14104 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14105
14106 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14107 intel_dp_init(dev, PCH_DP_C, PORT_C);
14108
14109 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14110 intel_dp_init(dev, PCH_DP_D, PORT_D);
14111 } else if (IS_VALLEYVIEW(dev)) {
14112 /*
14113 * The DP_DETECTED bit is the latched state of the DDC
14114 * SDA pin at boot. However since eDP doesn't require DDC
14115 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14116 * eDP ports may have been muxed to an alternate function.
14117 * Thus we can't rely on the DP_DETECTED bit alone to detect
14118 * eDP ports. Consult the VBT as well as DP_DETECTED to
14119 * detect eDP ports.
14120 */
14121 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14122 !intel_dp_is_edp(dev, PORT_B))
14123 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14124 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14125 intel_dp_is_edp(dev, PORT_B))
14126 intel_dp_init(dev, VLV_DP_B, PORT_B);
14127
14128 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14129 !intel_dp_is_edp(dev, PORT_C))
14130 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14131 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14132 intel_dp_is_edp(dev, PORT_C))
14133 intel_dp_init(dev, VLV_DP_C, PORT_C);
14134
14135 if (IS_CHERRYVIEW(dev)) {
14136 /* eDP not supported on port D, so don't check VBT */
14137 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14138 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14139 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14140 intel_dp_init(dev, CHV_DP_D, PORT_D);
14141 }
14142
14143 intel_dsi_init(dev);
14144 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14145 bool found = false;
14146
14147 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14148 DRM_DEBUG_KMS("probing SDVOB\n");
14149 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14150 if (!found && IS_G4X(dev)) {
14151 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14152 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14153 }
14154
14155 if (!found && IS_G4X(dev))
14156 intel_dp_init(dev, DP_B, PORT_B);
14157 }
14158
14159 /* Before G4X SDVOC doesn't have its own detect register */
14160
14161 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14162 DRM_DEBUG_KMS("probing SDVOC\n");
14163 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14164 }
14165
14166 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14167
14168 if (IS_G4X(dev)) {
14169 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14170 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14171 }
14172 if (IS_G4X(dev))
14173 intel_dp_init(dev, DP_C, PORT_C);
14174 }
14175
14176 if (IS_G4X(dev) &&
14177 (I915_READ(DP_D) & DP_DETECTED))
14178 intel_dp_init(dev, DP_D, PORT_D);
14179 } else if (IS_GEN2(dev))
14180 intel_dvo_init(dev);
14181
14182 if (SUPPORTS_TV(dev))
14183 intel_tv_init(dev);
14184
14185 intel_psr_init(dev);
14186
14187 for_each_intel_encoder(dev, encoder) {
14188 encoder->base.possible_crtcs = encoder->crtc_mask;
14189 encoder->base.possible_clones =
14190 intel_encoder_clones(encoder);
14191 }
14192
14193 intel_init_pch_refclk(dev);
14194
14195 drm_helper_move_panel_connectors_to_head(dev);
14196 }
14197
14198 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14199 {
14200 struct drm_device *dev = fb->dev;
14201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14202
14203 drm_framebuffer_cleanup(fb);
14204 mutex_lock(&dev->struct_mutex);
14205 WARN_ON(!intel_fb->obj->framebuffer_references--);
14206 drm_gem_object_unreference(&intel_fb->obj->base);
14207 mutex_unlock(&dev->struct_mutex);
14208 kfree(intel_fb);
14209 }
14210
14211 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14212 struct drm_file *file,
14213 unsigned int *handle)
14214 {
14215 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14216 struct drm_i915_gem_object *obj = intel_fb->obj;
14217
14218 if (obj->userptr.mm) {
14219 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14220 return -EINVAL;
14221 }
14222
14223 return drm_gem_handle_create(file, &obj->base, handle);
14224 }
14225
14226 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14227 struct drm_file *file,
14228 unsigned flags, unsigned color,
14229 struct drm_clip_rect *clips,
14230 unsigned num_clips)
14231 {
14232 struct drm_device *dev = fb->dev;
14233 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14234 struct drm_i915_gem_object *obj = intel_fb->obj;
14235
14236 mutex_lock(&dev->struct_mutex);
14237 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14238 mutex_unlock(&dev->struct_mutex);
14239
14240 return 0;
14241 }
14242
14243 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14244 .destroy = intel_user_framebuffer_destroy,
14245 .create_handle = intel_user_framebuffer_create_handle,
14246 .dirty = intel_user_framebuffer_dirty,
14247 };
14248
14249 static
14250 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14251 uint32_t pixel_format)
14252 {
14253 u32 gen = INTEL_INFO(dev)->gen;
14254
14255 if (gen >= 9) {
14256 /* "The stride in bytes must not exceed the of the size of 8K
14257 * pixels and 32K bytes."
14258 */
14259 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14260 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14261 return 32*1024;
14262 } else if (gen >= 4) {
14263 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14264 return 16*1024;
14265 else
14266 return 32*1024;
14267 } else if (gen >= 3) {
14268 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14269 return 8*1024;
14270 else
14271 return 16*1024;
14272 } else {
14273 /* XXX DSPC is limited to 4k tiled */
14274 return 8*1024;
14275 }
14276 }
14277
14278 static int intel_framebuffer_init(struct drm_device *dev,
14279 struct intel_framebuffer *intel_fb,
14280 struct drm_mode_fb_cmd2 *mode_cmd,
14281 struct drm_i915_gem_object *obj)
14282 {
14283 unsigned int aligned_height;
14284 int ret;
14285 u32 pitch_limit, stride_alignment;
14286
14287 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14288
14289 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14290 /* Enforce that fb modifier and tiling mode match, but only for
14291 * X-tiled. This is needed for FBC. */
14292 if (!!(obj->tiling_mode == I915_TILING_X) !=
14293 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14294 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14295 return -EINVAL;
14296 }
14297 } else {
14298 if (obj->tiling_mode == I915_TILING_X)
14299 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14300 else if (obj->tiling_mode == I915_TILING_Y) {
14301 DRM_DEBUG("No Y tiling for legacy addfb\n");
14302 return -EINVAL;
14303 }
14304 }
14305
14306 /* Passed in modifier sanity checking. */
14307 switch (mode_cmd->modifier[0]) {
14308 case I915_FORMAT_MOD_Y_TILED:
14309 case I915_FORMAT_MOD_Yf_TILED:
14310 if (INTEL_INFO(dev)->gen < 9) {
14311 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14312 mode_cmd->modifier[0]);
14313 return -EINVAL;
14314 }
14315 case DRM_FORMAT_MOD_NONE:
14316 case I915_FORMAT_MOD_X_TILED:
14317 break;
14318 default:
14319 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14320 mode_cmd->modifier[0]);
14321 return -EINVAL;
14322 }
14323
14324 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14325 mode_cmd->pixel_format);
14326 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14327 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14328 mode_cmd->pitches[0], stride_alignment);
14329 return -EINVAL;
14330 }
14331
14332 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14333 mode_cmd->pixel_format);
14334 if (mode_cmd->pitches[0] > pitch_limit) {
14335 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14336 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14337 "tiled" : "linear",
14338 mode_cmd->pitches[0], pitch_limit);
14339 return -EINVAL;
14340 }
14341
14342 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14343 mode_cmd->pitches[0] != obj->stride) {
14344 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14345 mode_cmd->pitches[0], obj->stride);
14346 return -EINVAL;
14347 }
14348
14349 /* Reject formats not supported by any plane early. */
14350 switch (mode_cmd->pixel_format) {
14351 case DRM_FORMAT_C8:
14352 case DRM_FORMAT_RGB565:
14353 case DRM_FORMAT_XRGB8888:
14354 case DRM_FORMAT_ARGB8888:
14355 break;
14356 case DRM_FORMAT_XRGB1555:
14357 if (INTEL_INFO(dev)->gen > 3) {
14358 DRM_DEBUG("unsupported pixel format: %s\n",
14359 drm_get_format_name(mode_cmd->pixel_format));
14360 return -EINVAL;
14361 }
14362 break;
14363 case DRM_FORMAT_ABGR8888:
14364 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14365 DRM_DEBUG("unsupported pixel format: %s\n",
14366 drm_get_format_name(mode_cmd->pixel_format));
14367 return -EINVAL;
14368 }
14369 break;
14370 case DRM_FORMAT_XBGR8888:
14371 case DRM_FORMAT_XRGB2101010:
14372 case DRM_FORMAT_XBGR2101010:
14373 if (INTEL_INFO(dev)->gen < 4) {
14374 DRM_DEBUG("unsupported pixel format: %s\n",
14375 drm_get_format_name(mode_cmd->pixel_format));
14376 return -EINVAL;
14377 }
14378 break;
14379 case DRM_FORMAT_ABGR2101010:
14380 if (!IS_VALLEYVIEW(dev)) {
14381 DRM_DEBUG("unsupported pixel format: %s\n",
14382 drm_get_format_name(mode_cmd->pixel_format));
14383 return -EINVAL;
14384 }
14385 break;
14386 case DRM_FORMAT_YUYV:
14387 case DRM_FORMAT_UYVY:
14388 case DRM_FORMAT_YVYU:
14389 case DRM_FORMAT_VYUY:
14390 if (INTEL_INFO(dev)->gen < 5) {
14391 DRM_DEBUG("unsupported pixel format: %s\n",
14392 drm_get_format_name(mode_cmd->pixel_format));
14393 return -EINVAL;
14394 }
14395 break;
14396 default:
14397 DRM_DEBUG("unsupported pixel format: %s\n",
14398 drm_get_format_name(mode_cmd->pixel_format));
14399 return -EINVAL;
14400 }
14401
14402 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14403 if (mode_cmd->offsets[0] != 0)
14404 return -EINVAL;
14405
14406 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14407 mode_cmd->pixel_format,
14408 mode_cmd->modifier[0]);
14409 /* FIXME drm helper for size checks (especially planar formats)? */
14410 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14411 return -EINVAL;
14412
14413 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14414 intel_fb->obj = obj;
14415 intel_fb->obj->framebuffer_references++;
14416
14417 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14418 if (ret) {
14419 DRM_ERROR("framebuffer init failed %d\n", ret);
14420 return ret;
14421 }
14422
14423 return 0;
14424 }
14425
14426 static struct drm_framebuffer *
14427 intel_user_framebuffer_create(struct drm_device *dev,
14428 struct drm_file *filp,
14429 struct drm_mode_fb_cmd2 *user_mode_cmd)
14430 {
14431 struct drm_i915_gem_object *obj;
14432 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14433
14434 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14435 mode_cmd.handles[0]));
14436 if (&obj->base == NULL)
14437 return ERR_PTR(-ENOENT);
14438
14439 return intel_framebuffer_create(dev, &mode_cmd, obj);
14440 }
14441
14442 #ifndef CONFIG_DRM_FBDEV_EMULATION
14443 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14444 {
14445 }
14446 #endif
14447
14448 static const struct drm_mode_config_funcs intel_mode_funcs = {
14449 .fb_create = intel_user_framebuffer_create,
14450 .output_poll_changed = intel_fbdev_output_poll_changed,
14451 .atomic_check = intel_atomic_check,
14452 .atomic_commit = intel_atomic_commit,
14453 .atomic_state_alloc = intel_atomic_state_alloc,
14454 .atomic_state_clear = intel_atomic_state_clear,
14455 };
14456
14457 /* Set up chip specific display functions */
14458 static void intel_init_display(struct drm_device *dev)
14459 {
14460 struct drm_i915_private *dev_priv = dev->dev_private;
14461
14462 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14463 dev_priv->display.find_dpll = g4x_find_best_dpll;
14464 else if (IS_CHERRYVIEW(dev))
14465 dev_priv->display.find_dpll = chv_find_best_dpll;
14466 else if (IS_VALLEYVIEW(dev))
14467 dev_priv->display.find_dpll = vlv_find_best_dpll;
14468 else if (IS_PINEVIEW(dev))
14469 dev_priv->display.find_dpll = pnv_find_best_dpll;
14470 else
14471 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14472
14473 if (INTEL_INFO(dev)->gen >= 9) {
14474 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14475 dev_priv->display.get_initial_plane_config =
14476 skylake_get_initial_plane_config;
14477 dev_priv->display.crtc_compute_clock =
14478 haswell_crtc_compute_clock;
14479 dev_priv->display.crtc_enable = haswell_crtc_enable;
14480 dev_priv->display.crtc_disable = haswell_crtc_disable;
14481 dev_priv->display.update_primary_plane =
14482 skylake_update_primary_plane;
14483 } else if (HAS_DDI(dev)) {
14484 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14485 dev_priv->display.get_initial_plane_config =
14486 ironlake_get_initial_plane_config;
14487 dev_priv->display.crtc_compute_clock =
14488 haswell_crtc_compute_clock;
14489 dev_priv->display.crtc_enable = haswell_crtc_enable;
14490 dev_priv->display.crtc_disable = haswell_crtc_disable;
14491 dev_priv->display.update_primary_plane =
14492 ironlake_update_primary_plane;
14493 } else if (HAS_PCH_SPLIT(dev)) {
14494 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14495 dev_priv->display.get_initial_plane_config =
14496 ironlake_get_initial_plane_config;
14497 dev_priv->display.crtc_compute_clock =
14498 ironlake_crtc_compute_clock;
14499 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14500 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14501 dev_priv->display.update_primary_plane =
14502 ironlake_update_primary_plane;
14503 } else if (IS_VALLEYVIEW(dev)) {
14504 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14505 dev_priv->display.get_initial_plane_config =
14506 i9xx_get_initial_plane_config;
14507 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14508 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14509 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14510 dev_priv->display.update_primary_plane =
14511 i9xx_update_primary_plane;
14512 } else {
14513 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14514 dev_priv->display.get_initial_plane_config =
14515 i9xx_get_initial_plane_config;
14516 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14517 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14518 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14519 dev_priv->display.update_primary_plane =
14520 i9xx_update_primary_plane;
14521 }
14522
14523 /* Returns the core display clock speed */
14524 if (IS_SKYLAKE(dev))
14525 dev_priv->display.get_display_clock_speed =
14526 skylake_get_display_clock_speed;
14527 else if (IS_BROXTON(dev))
14528 dev_priv->display.get_display_clock_speed =
14529 broxton_get_display_clock_speed;
14530 else if (IS_BROADWELL(dev))
14531 dev_priv->display.get_display_clock_speed =
14532 broadwell_get_display_clock_speed;
14533 else if (IS_HASWELL(dev))
14534 dev_priv->display.get_display_clock_speed =
14535 haswell_get_display_clock_speed;
14536 else if (IS_VALLEYVIEW(dev))
14537 dev_priv->display.get_display_clock_speed =
14538 valleyview_get_display_clock_speed;
14539 else if (IS_GEN5(dev))
14540 dev_priv->display.get_display_clock_speed =
14541 ilk_get_display_clock_speed;
14542 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14543 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14544 dev_priv->display.get_display_clock_speed =
14545 i945_get_display_clock_speed;
14546 else if (IS_GM45(dev))
14547 dev_priv->display.get_display_clock_speed =
14548 gm45_get_display_clock_speed;
14549 else if (IS_CRESTLINE(dev))
14550 dev_priv->display.get_display_clock_speed =
14551 i965gm_get_display_clock_speed;
14552 else if (IS_PINEVIEW(dev))
14553 dev_priv->display.get_display_clock_speed =
14554 pnv_get_display_clock_speed;
14555 else if (IS_G33(dev) || IS_G4X(dev))
14556 dev_priv->display.get_display_clock_speed =
14557 g33_get_display_clock_speed;
14558 else if (IS_I915G(dev))
14559 dev_priv->display.get_display_clock_speed =
14560 i915_get_display_clock_speed;
14561 else if (IS_I945GM(dev) || IS_845G(dev))
14562 dev_priv->display.get_display_clock_speed =
14563 i9xx_misc_get_display_clock_speed;
14564 else if (IS_PINEVIEW(dev))
14565 dev_priv->display.get_display_clock_speed =
14566 pnv_get_display_clock_speed;
14567 else if (IS_I915GM(dev))
14568 dev_priv->display.get_display_clock_speed =
14569 i915gm_get_display_clock_speed;
14570 else if (IS_I865G(dev))
14571 dev_priv->display.get_display_clock_speed =
14572 i865_get_display_clock_speed;
14573 else if (IS_I85X(dev))
14574 dev_priv->display.get_display_clock_speed =
14575 i85x_get_display_clock_speed;
14576 else { /* 830 */
14577 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14578 dev_priv->display.get_display_clock_speed =
14579 i830_get_display_clock_speed;
14580 }
14581
14582 if (IS_GEN5(dev)) {
14583 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14584 } else if (IS_GEN6(dev)) {
14585 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14586 } else if (IS_IVYBRIDGE(dev)) {
14587 /* FIXME: detect B0+ stepping and use auto training */
14588 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14589 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14590 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14591 if (IS_BROADWELL(dev)) {
14592 dev_priv->display.modeset_commit_cdclk =
14593 broadwell_modeset_commit_cdclk;
14594 dev_priv->display.modeset_calc_cdclk =
14595 broadwell_modeset_calc_cdclk;
14596 }
14597 } else if (IS_VALLEYVIEW(dev)) {
14598 dev_priv->display.modeset_commit_cdclk =
14599 valleyview_modeset_commit_cdclk;
14600 dev_priv->display.modeset_calc_cdclk =
14601 valleyview_modeset_calc_cdclk;
14602 } else if (IS_BROXTON(dev)) {
14603 dev_priv->display.modeset_commit_cdclk =
14604 broxton_modeset_commit_cdclk;
14605 dev_priv->display.modeset_calc_cdclk =
14606 broxton_modeset_calc_cdclk;
14607 }
14608
14609 switch (INTEL_INFO(dev)->gen) {
14610 case 2:
14611 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14612 break;
14613
14614 case 3:
14615 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14616 break;
14617
14618 case 4:
14619 case 5:
14620 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14621 break;
14622
14623 case 6:
14624 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14625 break;
14626 case 7:
14627 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14628 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14629 break;
14630 case 9:
14631 /* Drop through - unsupported since execlist only. */
14632 default:
14633 /* Default just returns -ENODEV to indicate unsupported */
14634 dev_priv->display.queue_flip = intel_default_queue_flip;
14635 }
14636
14637 mutex_init(&dev_priv->pps_mutex);
14638 }
14639
14640 /*
14641 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14642 * resume, or other times. This quirk makes sure that's the case for
14643 * affected systems.
14644 */
14645 static void quirk_pipea_force(struct drm_device *dev)
14646 {
14647 struct drm_i915_private *dev_priv = dev->dev_private;
14648
14649 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14650 DRM_INFO("applying pipe a force quirk\n");
14651 }
14652
14653 static void quirk_pipeb_force(struct drm_device *dev)
14654 {
14655 struct drm_i915_private *dev_priv = dev->dev_private;
14656
14657 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14658 DRM_INFO("applying pipe b force quirk\n");
14659 }
14660
14661 /*
14662 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14663 */
14664 static void quirk_ssc_force_disable(struct drm_device *dev)
14665 {
14666 struct drm_i915_private *dev_priv = dev->dev_private;
14667 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14668 DRM_INFO("applying lvds SSC disable quirk\n");
14669 }
14670
14671 /*
14672 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14673 * brightness value
14674 */
14675 static void quirk_invert_brightness(struct drm_device *dev)
14676 {
14677 struct drm_i915_private *dev_priv = dev->dev_private;
14678 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14679 DRM_INFO("applying inverted panel brightness quirk\n");
14680 }
14681
14682 /* Some VBT's incorrectly indicate no backlight is present */
14683 static void quirk_backlight_present(struct drm_device *dev)
14684 {
14685 struct drm_i915_private *dev_priv = dev->dev_private;
14686 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14687 DRM_INFO("applying backlight present quirk\n");
14688 }
14689
14690 struct intel_quirk {
14691 int device;
14692 int subsystem_vendor;
14693 int subsystem_device;
14694 void (*hook)(struct drm_device *dev);
14695 };
14696
14697 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14698 struct intel_dmi_quirk {
14699 void (*hook)(struct drm_device *dev);
14700 const struct dmi_system_id (*dmi_id_list)[];
14701 };
14702
14703 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14704 {
14705 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14706 return 1;
14707 }
14708
14709 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14710 {
14711 .dmi_id_list = &(const struct dmi_system_id[]) {
14712 {
14713 .callback = intel_dmi_reverse_brightness,
14714 .ident = "NCR Corporation",
14715 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14716 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14717 },
14718 },
14719 { } /* terminating entry */
14720 },
14721 .hook = quirk_invert_brightness,
14722 },
14723 };
14724
14725 static struct intel_quirk intel_quirks[] = {
14726 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14727 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14728
14729 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14730 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14731
14732 /* 830 needs to leave pipe A & dpll A up */
14733 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14734
14735 /* 830 needs to leave pipe B & dpll B up */
14736 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14737
14738 /* Lenovo U160 cannot use SSC on LVDS */
14739 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14740
14741 /* Sony Vaio Y cannot use SSC on LVDS */
14742 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14743
14744 /* Acer Aspire 5734Z must invert backlight brightness */
14745 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14746
14747 /* Acer/eMachines G725 */
14748 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14749
14750 /* Acer/eMachines e725 */
14751 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14752
14753 /* Acer/Packard Bell NCL20 */
14754 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14755
14756 /* Acer Aspire 4736Z */
14757 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14758
14759 /* Acer Aspire 5336 */
14760 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14761
14762 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14763 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14764
14765 /* Acer C720 Chromebook (Core i3 4005U) */
14766 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14767
14768 /* Apple Macbook 2,1 (Core 2 T7400) */
14769 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14770
14771 /* Apple Macbook 4,1 */
14772 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14773
14774 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14775 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14776
14777 /* HP Chromebook 14 (Celeron 2955U) */
14778 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14779
14780 /* Dell Chromebook 11 */
14781 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14782
14783 /* Dell Chromebook 11 (2015 version) */
14784 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14785 };
14786
14787 static void intel_init_quirks(struct drm_device *dev)
14788 {
14789 struct pci_dev *d = dev->pdev;
14790 int i;
14791
14792 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14793 struct intel_quirk *q = &intel_quirks[i];
14794
14795 if (d->device == q->device &&
14796 (d->subsystem_vendor == q->subsystem_vendor ||
14797 q->subsystem_vendor == PCI_ANY_ID) &&
14798 (d->subsystem_device == q->subsystem_device ||
14799 q->subsystem_device == PCI_ANY_ID))
14800 q->hook(dev);
14801 }
14802 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14803 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14804 intel_dmi_quirks[i].hook(dev);
14805 }
14806 }
14807
14808 /* Disable the VGA plane that we never use */
14809 static void i915_disable_vga(struct drm_device *dev)
14810 {
14811 struct drm_i915_private *dev_priv = dev->dev_private;
14812 u8 sr1;
14813 u32 vga_reg = i915_vgacntrl_reg(dev);
14814
14815 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14816 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14817 outb(SR01, VGA_SR_INDEX);
14818 sr1 = inb(VGA_SR_DATA);
14819 outb(sr1 | 1<<5, VGA_SR_DATA);
14820 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14821 udelay(300);
14822
14823 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14824 POSTING_READ(vga_reg);
14825 }
14826
14827 void intel_modeset_init_hw(struct drm_device *dev)
14828 {
14829 intel_update_cdclk(dev);
14830 intel_prepare_ddi(dev);
14831 intel_init_clock_gating(dev);
14832 intel_enable_gt_powersave(dev);
14833 }
14834
14835 void intel_modeset_init(struct drm_device *dev)
14836 {
14837 struct drm_i915_private *dev_priv = dev->dev_private;
14838 int sprite, ret;
14839 enum pipe pipe;
14840 struct intel_crtc *crtc;
14841
14842 drm_mode_config_init(dev);
14843
14844 dev->mode_config.min_width = 0;
14845 dev->mode_config.min_height = 0;
14846
14847 dev->mode_config.preferred_depth = 24;
14848 dev->mode_config.prefer_shadow = 1;
14849
14850 dev->mode_config.allow_fb_modifiers = true;
14851
14852 dev->mode_config.funcs = &intel_mode_funcs;
14853
14854 intel_init_quirks(dev);
14855
14856 intel_init_pm(dev);
14857
14858 if (INTEL_INFO(dev)->num_pipes == 0)
14859 return;
14860
14861 /*
14862 * There may be no VBT; and if the BIOS enabled SSC we can
14863 * just keep using it to avoid unnecessary flicker. Whereas if the
14864 * BIOS isn't using it, don't assume it will work even if the VBT
14865 * indicates as much.
14866 */
14867 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14868 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14869 DREF_SSC1_ENABLE);
14870
14871 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14872 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14873 bios_lvds_use_ssc ? "en" : "dis",
14874 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14875 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14876 }
14877 }
14878
14879 intel_init_display(dev);
14880 intel_init_audio(dev);
14881
14882 if (IS_GEN2(dev)) {
14883 dev->mode_config.max_width = 2048;
14884 dev->mode_config.max_height = 2048;
14885 } else if (IS_GEN3(dev)) {
14886 dev->mode_config.max_width = 4096;
14887 dev->mode_config.max_height = 4096;
14888 } else {
14889 dev->mode_config.max_width = 8192;
14890 dev->mode_config.max_height = 8192;
14891 }
14892
14893 if (IS_845G(dev) || IS_I865G(dev)) {
14894 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14895 dev->mode_config.cursor_height = 1023;
14896 } else if (IS_GEN2(dev)) {
14897 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14898 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14899 } else {
14900 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14901 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14902 }
14903
14904 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14905
14906 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14907 INTEL_INFO(dev)->num_pipes,
14908 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14909
14910 for_each_pipe(dev_priv, pipe) {
14911 intel_crtc_init(dev, pipe);
14912 for_each_sprite(dev_priv, pipe, sprite) {
14913 ret = intel_plane_init(dev, pipe, sprite);
14914 if (ret)
14915 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14916 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14917 }
14918 }
14919
14920 intel_update_czclk(dev_priv);
14921 intel_update_cdclk(dev);
14922
14923 intel_shared_dpll_init(dev);
14924
14925 /* Just disable it once at startup */
14926 i915_disable_vga(dev);
14927 intel_setup_outputs(dev);
14928
14929 /* Just in case the BIOS is doing something questionable. */
14930 intel_fbc_disable(dev_priv);
14931
14932 drm_modeset_lock_all(dev);
14933 intel_modeset_setup_hw_state(dev);
14934 drm_modeset_unlock_all(dev);
14935
14936 for_each_intel_crtc(dev, crtc) {
14937 struct intel_initial_plane_config plane_config = {};
14938
14939 if (!crtc->active)
14940 continue;
14941
14942 /*
14943 * Note that reserving the BIOS fb up front prevents us
14944 * from stuffing other stolen allocations like the ring
14945 * on top. This prevents some ugliness at boot time, and
14946 * can even allow for smooth boot transitions if the BIOS
14947 * fb is large enough for the active pipe configuration.
14948 */
14949 dev_priv->display.get_initial_plane_config(crtc,
14950 &plane_config);
14951
14952 /*
14953 * If the fb is shared between multiple heads, we'll
14954 * just get the first one.
14955 */
14956 intel_find_initial_plane_obj(crtc, &plane_config);
14957 }
14958 }
14959
14960 static void intel_enable_pipe_a(struct drm_device *dev)
14961 {
14962 struct intel_connector *connector;
14963 struct drm_connector *crt = NULL;
14964 struct intel_load_detect_pipe load_detect_temp;
14965 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14966
14967 /* We can't just switch on the pipe A, we need to set things up with a
14968 * proper mode and output configuration. As a gross hack, enable pipe A
14969 * by enabling the load detect pipe once. */
14970 for_each_intel_connector(dev, connector) {
14971 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14972 crt = &connector->base;
14973 break;
14974 }
14975 }
14976
14977 if (!crt)
14978 return;
14979
14980 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14981 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14982 }
14983
14984 static bool
14985 intel_check_plane_mapping(struct intel_crtc *crtc)
14986 {
14987 struct drm_device *dev = crtc->base.dev;
14988 struct drm_i915_private *dev_priv = dev->dev_private;
14989 u32 val;
14990
14991 if (INTEL_INFO(dev)->num_pipes == 1)
14992 return true;
14993
14994 val = I915_READ(DSPCNTR(!crtc->plane));
14995
14996 if ((val & DISPLAY_PLANE_ENABLE) &&
14997 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14998 return false;
14999
15000 return true;
15001 }
15002
15003 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15004 {
15005 struct drm_device *dev = crtc->base.dev;
15006 struct intel_encoder *encoder;
15007
15008 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15009 return true;
15010
15011 return false;
15012 }
15013
15014 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15015 {
15016 struct drm_device *dev = crtc->base.dev;
15017 struct drm_i915_private *dev_priv = dev->dev_private;
15018 u32 reg;
15019
15020 /* Clear any frame start delays used for debugging left by the BIOS */
15021 reg = PIPECONF(crtc->config->cpu_transcoder);
15022 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15023
15024 /* restore vblank interrupts to correct state */
15025 drm_crtc_vblank_reset(&crtc->base);
15026 if (crtc->active) {
15027 struct intel_plane *plane;
15028
15029 drm_crtc_vblank_on(&crtc->base);
15030
15031 /* Disable everything but the primary plane */
15032 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15033 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15034 continue;
15035
15036 plane->disable_plane(&plane->base, &crtc->base);
15037 }
15038 }
15039
15040 /* We need to sanitize the plane -> pipe mapping first because this will
15041 * disable the crtc (and hence change the state) if it is wrong. Note
15042 * that gen4+ has a fixed plane -> pipe mapping. */
15043 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15044 bool plane;
15045
15046 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15047 crtc->base.base.id);
15048
15049 /* Pipe has the wrong plane attached and the plane is active.
15050 * Temporarily change the plane mapping and disable everything
15051 * ... */
15052 plane = crtc->plane;
15053 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15054 crtc->plane = !plane;
15055 intel_crtc_disable_noatomic(&crtc->base);
15056 crtc->plane = plane;
15057 }
15058
15059 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15060 crtc->pipe == PIPE_A && !crtc->active) {
15061 /* BIOS forgot to enable pipe A, this mostly happens after
15062 * resume. Force-enable the pipe to fix this, the update_dpms
15063 * call below we restore the pipe to the right state, but leave
15064 * the required bits on. */
15065 intel_enable_pipe_a(dev);
15066 }
15067
15068 /* Adjust the state of the output pipe according to whether we
15069 * have active connectors/encoders. */
15070 if (!intel_crtc_has_encoders(crtc))
15071 intel_crtc_disable_noatomic(&crtc->base);
15072
15073 if (crtc->active != crtc->base.state->active) {
15074 struct intel_encoder *encoder;
15075
15076 /* This can happen either due to bugs in the get_hw_state
15077 * functions or because of calls to intel_crtc_disable_noatomic,
15078 * or because the pipe is force-enabled due to the
15079 * pipe A quirk. */
15080 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15081 crtc->base.base.id,
15082 crtc->base.state->enable ? "enabled" : "disabled",
15083 crtc->active ? "enabled" : "disabled");
15084
15085 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15086 crtc->base.state->active = crtc->active;
15087 crtc->base.enabled = crtc->active;
15088
15089 /* Because we only establish the connector -> encoder ->
15090 * crtc links if something is active, this means the
15091 * crtc is now deactivated. Break the links. connector
15092 * -> encoder links are only establish when things are
15093 * actually up, hence no need to break them. */
15094 WARN_ON(crtc->active);
15095
15096 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15097 encoder->base.crtc = NULL;
15098 }
15099
15100 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15101 /*
15102 * We start out with underrun reporting disabled to avoid races.
15103 * For correct bookkeeping mark this on active crtcs.
15104 *
15105 * Also on gmch platforms we dont have any hardware bits to
15106 * disable the underrun reporting. Which means we need to start
15107 * out with underrun reporting disabled also on inactive pipes,
15108 * since otherwise we'll complain about the garbage we read when
15109 * e.g. coming up after runtime pm.
15110 *
15111 * No protection against concurrent access is required - at
15112 * worst a fifo underrun happens which also sets this to false.
15113 */
15114 crtc->cpu_fifo_underrun_disabled = true;
15115 crtc->pch_fifo_underrun_disabled = true;
15116 }
15117 }
15118
15119 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15120 {
15121 struct intel_connector *connector;
15122 struct drm_device *dev = encoder->base.dev;
15123 bool active = false;
15124
15125 /* We need to check both for a crtc link (meaning that the
15126 * encoder is active and trying to read from a pipe) and the
15127 * pipe itself being active. */
15128 bool has_active_crtc = encoder->base.crtc &&
15129 to_intel_crtc(encoder->base.crtc)->active;
15130
15131 for_each_intel_connector(dev, connector) {
15132 if (connector->base.encoder != &encoder->base)
15133 continue;
15134
15135 active = true;
15136 break;
15137 }
15138
15139 if (active && !has_active_crtc) {
15140 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15141 encoder->base.base.id,
15142 encoder->base.name);
15143
15144 /* Connector is active, but has no active pipe. This is
15145 * fallout from our resume register restoring. Disable
15146 * the encoder manually again. */
15147 if (encoder->base.crtc) {
15148 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15149 encoder->base.base.id,
15150 encoder->base.name);
15151 encoder->disable(encoder);
15152 if (encoder->post_disable)
15153 encoder->post_disable(encoder);
15154 }
15155 encoder->base.crtc = NULL;
15156
15157 /* Inconsistent output/port/pipe state happens presumably due to
15158 * a bug in one of the get_hw_state functions. Or someplace else
15159 * in our code, like the register restore mess on resume. Clamp
15160 * things to off as a safer default. */
15161 for_each_intel_connector(dev, connector) {
15162 if (connector->encoder != encoder)
15163 continue;
15164 connector->base.dpms = DRM_MODE_DPMS_OFF;
15165 connector->base.encoder = NULL;
15166 }
15167 }
15168 /* Enabled encoders without active connectors will be fixed in
15169 * the crtc fixup. */
15170 }
15171
15172 void i915_redisable_vga_power_on(struct drm_device *dev)
15173 {
15174 struct drm_i915_private *dev_priv = dev->dev_private;
15175 u32 vga_reg = i915_vgacntrl_reg(dev);
15176
15177 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15178 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15179 i915_disable_vga(dev);
15180 }
15181 }
15182
15183 void i915_redisable_vga(struct drm_device *dev)
15184 {
15185 struct drm_i915_private *dev_priv = dev->dev_private;
15186
15187 /* This function can be called both from intel_modeset_setup_hw_state or
15188 * at a very early point in our resume sequence, where the power well
15189 * structures are not yet restored. Since this function is at a very
15190 * paranoid "someone might have enabled VGA while we were not looking"
15191 * level, just check if the power well is enabled instead of trying to
15192 * follow the "don't touch the power well if we don't need it" policy
15193 * the rest of the driver uses. */
15194 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15195 return;
15196
15197 i915_redisable_vga_power_on(dev);
15198 }
15199
15200 static bool primary_get_hw_state(struct intel_plane *plane)
15201 {
15202 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15203
15204 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15205 }
15206
15207 /* FIXME read out full plane state for all planes */
15208 static void readout_plane_state(struct intel_crtc *crtc)
15209 {
15210 struct drm_plane *primary = crtc->base.primary;
15211 struct intel_plane_state *plane_state =
15212 to_intel_plane_state(primary->state);
15213
15214 plane_state->visible =
15215 primary_get_hw_state(to_intel_plane(primary));
15216
15217 if (plane_state->visible)
15218 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15219 }
15220
15221 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15222 {
15223 struct drm_i915_private *dev_priv = dev->dev_private;
15224 enum pipe pipe;
15225 struct intel_crtc *crtc;
15226 struct intel_encoder *encoder;
15227 struct intel_connector *connector;
15228 int i;
15229
15230 for_each_intel_crtc(dev, crtc) {
15231 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15232 memset(crtc->config, 0, sizeof(*crtc->config));
15233 crtc->config->base.crtc = &crtc->base;
15234
15235 crtc->active = dev_priv->display.get_pipe_config(crtc,
15236 crtc->config);
15237
15238 crtc->base.state->active = crtc->active;
15239 crtc->base.enabled = crtc->active;
15240
15241 readout_plane_state(crtc);
15242
15243 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15244 crtc->base.base.id,
15245 crtc->active ? "enabled" : "disabled");
15246 }
15247
15248 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15249 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15250
15251 pll->on = pll->get_hw_state(dev_priv, pll,
15252 &pll->config.hw_state);
15253 pll->active = 0;
15254 pll->config.crtc_mask = 0;
15255 for_each_intel_crtc(dev, crtc) {
15256 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15257 pll->active++;
15258 pll->config.crtc_mask |= 1 << crtc->pipe;
15259 }
15260 }
15261
15262 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15263 pll->name, pll->config.crtc_mask, pll->on);
15264
15265 if (pll->config.crtc_mask)
15266 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15267 }
15268
15269 for_each_intel_encoder(dev, encoder) {
15270 pipe = 0;
15271
15272 if (encoder->get_hw_state(encoder, &pipe)) {
15273 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15274 encoder->base.crtc = &crtc->base;
15275 encoder->get_config(encoder, crtc->config);
15276 } else {
15277 encoder->base.crtc = NULL;
15278 }
15279
15280 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15281 encoder->base.base.id,
15282 encoder->base.name,
15283 encoder->base.crtc ? "enabled" : "disabled",
15284 pipe_name(pipe));
15285 }
15286
15287 for_each_intel_connector(dev, connector) {
15288 if (connector->get_hw_state(connector)) {
15289 connector->base.dpms = DRM_MODE_DPMS_ON;
15290 connector->base.encoder = &connector->encoder->base;
15291 } else {
15292 connector->base.dpms = DRM_MODE_DPMS_OFF;
15293 connector->base.encoder = NULL;
15294 }
15295 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15296 connector->base.base.id,
15297 connector->base.name,
15298 connector->base.encoder ? "enabled" : "disabled");
15299 }
15300
15301 for_each_intel_crtc(dev, crtc) {
15302 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15303
15304 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15305 if (crtc->base.state->active) {
15306 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15307 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15308 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15309
15310 /*
15311 * The initial mode needs to be set in order to keep
15312 * the atomic core happy. It wants a valid mode if the
15313 * crtc's enabled, so we do the above call.
15314 *
15315 * At this point some state updated by the connectors
15316 * in their ->detect() callback has not run yet, so
15317 * no recalculation can be done yet.
15318 *
15319 * Even if we could do a recalculation and modeset
15320 * right now it would cause a double modeset if
15321 * fbdev or userspace chooses a different initial mode.
15322 *
15323 * If that happens, someone indicated they wanted a
15324 * mode change, which means it's safe to do a full
15325 * recalculation.
15326 */
15327 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15328
15329 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15330 update_scanline_offset(crtc);
15331 }
15332 }
15333 }
15334
15335 /* Scan out the current hw modeset state,
15336 * and sanitizes it to the current state
15337 */
15338 static void
15339 intel_modeset_setup_hw_state(struct drm_device *dev)
15340 {
15341 struct drm_i915_private *dev_priv = dev->dev_private;
15342 enum pipe pipe;
15343 struct intel_crtc *crtc;
15344 struct intel_encoder *encoder;
15345 int i;
15346
15347 intel_modeset_readout_hw_state(dev);
15348
15349 /* HW state is read out, now we need to sanitize this mess. */
15350 for_each_intel_encoder(dev, encoder) {
15351 intel_sanitize_encoder(encoder);
15352 }
15353
15354 for_each_pipe(dev_priv, pipe) {
15355 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15356 intel_sanitize_crtc(crtc);
15357 intel_dump_pipe_config(crtc, crtc->config,
15358 "[setup_hw_state]");
15359 }
15360
15361 intel_modeset_update_connector_atomic_state(dev);
15362
15363 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15364 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15365
15366 if (!pll->on || pll->active)
15367 continue;
15368
15369 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15370
15371 pll->disable(dev_priv, pll);
15372 pll->on = false;
15373 }
15374
15375 if (IS_VALLEYVIEW(dev))
15376 vlv_wm_get_hw_state(dev);
15377 else if (IS_GEN9(dev))
15378 skl_wm_get_hw_state(dev);
15379 else if (HAS_PCH_SPLIT(dev))
15380 ilk_wm_get_hw_state(dev);
15381
15382 for_each_intel_crtc(dev, crtc) {
15383 unsigned long put_domains;
15384
15385 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15386 if (WARN_ON(put_domains))
15387 modeset_put_power_domains(dev_priv, put_domains);
15388 }
15389 intel_display_set_init_power(dev_priv, false);
15390 }
15391
15392 void intel_display_resume(struct drm_device *dev)
15393 {
15394 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15395 struct intel_connector *conn;
15396 struct intel_plane *plane;
15397 struct drm_crtc *crtc;
15398 int ret;
15399
15400 if (!state)
15401 return;
15402
15403 state->acquire_ctx = dev->mode_config.acquire_ctx;
15404
15405 /* preserve complete old state, including dpll */
15406 intel_atomic_get_shared_dpll_state(state);
15407
15408 for_each_crtc(dev, crtc) {
15409 struct drm_crtc_state *crtc_state =
15410 drm_atomic_get_crtc_state(state, crtc);
15411
15412 ret = PTR_ERR_OR_ZERO(crtc_state);
15413 if (ret)
15414 goto err;
15415
15416 /* force a restore */
15417 crtc_state->mode_changed = true;
15418 }
15419
15420 for_each_intel_plane(dev, plane) {
15421 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15422 if (ret)
15423 goto err;
15424 }
15425
15426 for_each_intel_connector(dev, conn) {
15427 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15428 if (ret)
15429 goto err;
15430 }
15431
15432 intel_modeset_setup_hw_state(dev);
15433
15434 i915_redisable_vga(dev);
15435 ret = drm_atomic_commit(state);
15436 if (!ret)
15437 return;
15438
15439 err:
15440 DRM_ERROR("Restoring old state failed with %i\n", ret);
15441 drm_atomic_state_free(state);
15442 }
15443
15444 void intel_modeset_gem_init(struct drm_device *dev)
15445 {
15446 struct drm_crtc *c;
15447 struct drm_i915_gem_object *obj;
15448 int ret;
15449
15450 mutex_lock(&dev->struct_mutex);
15451 intel_init_gt_powersave(dev);
15452 mutex_unlock(&dev->struct_mutex);
15453
15454 intel_modeset_init_hw(dev);
15455
15456 intel_setup_overlay(dev);
15457
15458 /*
15459 * Make sure any fbs we allocated at startup are properly
15460 * pinned & fenced. When we do the allocation it's too early
15461 * for this.
15462 */
15463 for_each_crtc(dev, c) {
15464 obj = intel_fb_obj(c->primary->fb);
15465 if (obj == NULL)
15466 continue;
15467
15468 mutex_lock(&dev->struct_mutex);
15469 ret = intel_pin_and_fence_fb_obj(c->primary,
15470 c->primary->fb,
15471 c->primary->state,
15472 NULL, NULL);
15473 mutex_unlock(&dev->struct_mutex);
15474 if (ret) {
15475 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15476 to_intel_crtc(c)->pipe);
15477 drm_framebuffer_unreference(c->primary->fb);
15478 c->primary->fb = NULL;
15479 c->primary->crtc = c->primary->state->crtc = NULL;
15480 update_state_fb(c->primary);
15481 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15482 }
15483 }
15484
15485 intel_backlight_register(dev);
15486 }
15487
15488 void intel_connector_unregister(struct intel_connector *intel_connector)
15489 {
15490 struct drm_connector *connector = &intel_connector->base;
15491
15492 intel_panel_destroy_backlight(connector);
15493 drm_connector_unregister(connector);
15494 }
15495
15496 void intel_modeset_cleanup(struct drm_device *dev)
15497 {
15498 struct drm_i915_private *dev_priv = dev->dev_private;
15499 struct drm_connector *connector;
15500
15501 intel_disable_gt_powersave(dev);
15502
15503 intel_backlight_unregister(dev);
15504
15505 /*
15506 * Interrupts and polling as the first thing to avoid creating havoc.
15507 * Too much stuff here (turning of connectors, ...) would
15508 * experience fancy races otherwise.
15509 */
15510 intel_irq_uninstall(dev_priv);
15511
15512 /*
15513 * Due to the hpd irq storm handling the hotplug work can re-arm the
15514 * poll handlers. Hence disable polling after hpd handling is shut down.
15515 */
15516 drm_kms_helper_poll_fini(dev);
15517
15518 intel_unregister_dsm_handler();
15519
15520 intel_fbc_disable(dev_priv);
15521
15522 /* flush any delayed tasks or pending work */
15523 flush_scheduled_work();
15524
15525 /* destroy the backlight and sysfs files before encoders/connectors */
15526 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15527 struct intel_connector *intel_connector;
15528
15529 intel_connector = to_intel_connector(connector);
15530 intel_connector->unregister(intel_connector);
15531 }
15532
15533 drm_mode_config_cleanup(dev);
15534
15535 intel_cleanup_overlay(dev);
15536
15537 mutex_lock(&dev->struct_mutex);
15538 intel_cleanup_gt_powersave(dev);
15539 mutex_unlock(&dev->struct_mutex);
15540 }
15541
15542 /*
15543 * Return which encoder is currently attached for connector.
15544 */
15545 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15546 {
15547 return &intel_attached_encoder(connector)->base;
15548 }
15549
15550 void intel_connector_attach_encoder(struct intel_connector *connector,
15551 struct intel_encoder *encoder)
15552 {
15553 connector->encoder = encoder;
15554 drm_mode_connector_attach_encoder(&connector->base,
15555 &encoder->base);
15556 }
15557
15558 /*
15559 * set vga decode state - true == enable VGA decode
15560 */
15561 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15562 {
15563 struct drm_i915_private *dev_priv = dev->dev_private;
15564 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15565 u16 gmch_ctrl;
15566
15567 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15568 DRM_ERROR("failed to read control word\n");
15569 return -EIO;
15570 }
15571
15572 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15573 return 0;
15574
15575 if (state)
15576 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15577 else
15578 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15579
15580 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15581 DRM_ERROR("failed to write control word\n");
15582 return -EIO;
15583 }
15584
15585 return 0;
15586 }
15587
15588 struct intel_display_error_state {
15589
15590 u32 power_well_driver;
15591
15592 int num_transcoders;
15593
15594 struct intel_cursor_error_state {
15595 u32 control;
15596 u32 position;
15597 u32 base;
15598 u32 size;
15599 } cursor[I915_MAX_PIPES];
15600
15601 struct intel_pipe_error_state {
15602 bool power_domain_on;
15603 u32 source;
15604 u32 stat;
15605 } pipe[I915_MAX_PIPES];
15606
15607 struct intel_plane_error_state {
15608 u32 control;
15609 u32 stride;
15610 u32 size;
15611 u32 pos;
15612 u32 addr;
15613 u32 surface;
15614 u32 tile_offset;
15615 } plane[I915_MAX_PIPES];
15616
15617 struct intel_transcoder_error_state {
15618 bool power_domain_on;
15619 enum transcoder cpu_transcoder;
15620
15621 u32 conf;
15622
15623 u32 htotal;
15624 u32 hblank;
15625 u32 hsync;
15626 u32 vtotal;
15627 u32 vblank;
15628 u32 vsync;
15629 } transcoder[4];
15630 };
15631
15632 struct intel_display_error_state *
15633 intel_display_capture_error_state(struct drm_device *dev)
15634 {
15635 struct drm_i915_private *dev_priv = dev->dev_private;
15636 struct intel_display_error_state *error;
15637 int transcoders[] = {
15638 TRANSCODER_A,
15639 TRANSCODER_B,
15640 TRANSCODER_C,
15641 TRANSCODER_EDP,
15642 };
15643 int i;
15644
15645 if (INTEL_INFO(dev)->num_pipes == 0)
15646 return NULL;
15647
15648 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15649 if (error == NULL)
15650 return NULL;
15651
15652 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15653 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15654
15655 for_each_pipe(dev_priv, i) {
15656 error->pipe[i].power_domain_on =
15657 __intel_display_power_is_enabled(dev_priv,
15658 POWER_DOMAIN_PIPE(i));
15659 if (!error->pipe[i].power_domain_on)
15660 continue;
15661
15662 error->cursor[i].control = I915_READ(CURCNTR(i));
15663 error->cursor[i].position = I915_READ(CURPOS(i));
15664 error->cursor[i].base = I915_READ(CURBASE(i));
15665
15666 error->plane[i].control = I915_READ(DSPCNTR(i));
15667 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15668 if (INTEL_INFO(dev)->gen <= 3) {
15669 error->plane[i].size = I915_READ(DSPSIZE(i));
15670 error->plane[i].pos = I915_READ(DSPPOS(i));
15671 }
15672 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15673 error->plane[i].addr = I915_READ(DSPADDR(i));
15674 if (INTEL_INFO(dev)->gen >= 4) {
15675 error->plane[i].surface = I915_READ(DSPSURF(i));
15676 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15677 }
15678
15679 error->pipe[i].source = I915_READ(PIPESRC(i));
15680
15681 if (HAS_GMCH_DISPLAY(dev))
15682 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15683 }
15684
15685 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15686 if (HAS_DDI(dev_priv->dev))
15687 error->num_transcoders++; /* Account for eDP. */
15688
15689 for (i = 0; i < error->num_transcoders; i++) {
15690 enum transcoder cpu_transcoder = transcoders[i];
15691
15692 error->transcoder[i].power_domain_on =
15693 __intel_display_power_is_enabled(dev_priv,
15694 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15695 if (!error->transcoder[i].power_domain_on)
15696 continue;
15697
15698 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15699
15700 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15701 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15702 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15703 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15704 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15705 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15706 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15707 }
15708
15709 return error;
15710 }
15711
15712 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15713
15714 void
15715 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15716 struct drm_device *dev,
15717 struct intel_display_error_state *error)
15718 {
15719 struct drm_i915_private *dev_priv = dev->dev_private;
15720 int i;
15721
15722 if (!error)
15723 return;
15724
15725 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15726 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15727 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15728 error->power_well_driver);
15729 for_each_pipe(dev_priv, i) {
15730 err_printf(m, "Pipe [%d]:\n", i);
15731 err_printf(m, " Power: %s\n",
15732 error->pipe[i].power_domain_on ? "on" : "off");
15733 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15734 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15735
15736 err_printf(m, "Plane [%d]:\n", i);
15737 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15738 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15739 if (INTEL_INFO(dev)->gen <= 3) {
15740 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15741 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15742 }
15743 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15744 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15745 if (INTEL_INFO(dev)->gen >= 4) {
15746 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15747 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15748 }
15749
15750 err_printf(m, "Cursor [%d]:\n", i);
15751 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15752 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15753 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15754 }
15755
15756 for (i = 0; i < error->num_transcoders; i++) {
15757 err_printf(m, "CPU transcoder: %c\n",
15758 transcoder_name(error->transcoder[i].cpu_transcoder));
15759 err_printf(m, " Power: %s\n",
15760 error->transcoder[i].power_domain_on ? "on" : "off");
15761 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15762 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15763 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15764 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15765 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15766 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15767 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15768 }
15769 }
15770
15771 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15772 {
15773 struct intel_crtc *crtc;
15774
15775 for_each_intel_crtc(dev, crtc) {
15776 struct intel_unpin_work *work;
15777
15778 spin_lock_irq(&dev->event_lock);
15779
15780 work = crtc->unpin_work;
15781
15782 if (work && work->event &&
15783 work->event->base.file_priv == file) {
15784 kfree(work->event);
15785 work->event = NULL;
15786 }
15787
15788 spin_unlock_irq(&dev->event_lock);
15789 }
15790 }
Linux with added FPC-III support