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iwlwifi: fix FAT channel config for 5000 series
[linux/fpc-iii.git] / drivers / char / synclink_gt.c
blobefb3dc928a43a7b6fe26bcfc551511f84d601772
1 /*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24 /*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 //#define DBGTBUF(info) dump_tbufs(info)
44 //#define DBGRBUF(info) dump_rbufs(info)
45
46
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
62 #include <linux/mm.h>
63 #include <linux/slab.h>
64 #include <linux/netdevice.h>
65 #include <linux/vmalloc.h>
66 #include <linux/init.h>
67 #include <linux/delay.h>
68 #include <linux/ioctl.h>
69 #include <linux/termios.h>
70 #include <linux/bitops.h>
71 #include <linux/workqueue.h>
72 #include <linux/hdlc.h>
73 #include <linux/synclink.h>
74
75 #include <asm/system.h>
76 #include <asm/io.h>
77 #include <asm/irq.h>
78 #include <asm/dma.h>
79 #include <asm/types.h>
80 #include <asm/uaccess.h>
81
82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
83 #define SYNCLINK_GENERIC_HDLC 1
84 #else
85 #define SYNCLINK_GENERIC_HDLC 0
86 #endif
87
88 /*
89 * module identification
90 */
91 static char *driver_name = "SyncLink GT";
92 static char *tty_driver_name = "synclink_gt";
93 static char *tty_dev_prefix = "ttySLG";
94 MODULE_LICENSE("GPL");
95 #define MGSL_MAGIC 0x5401
96 #define MAX_DEVICES 32
97
98 static struct pci_device_id pci_table[] = {
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {0,}, /* terminate list */
104 };
105 MODULE_DEVICE_TABLE(pci, pci_table);
106
107 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108 static void remove_one(struct pci_dev *dev);
109 static struct pci_driver pci_driver = {
110 .name = "synclink_gt",
111 .id_table = pci_table,
112 .probe = init_one,
113 .remove = __devexit_p(remove_one),
114 };
115
116 static bool pci_registered;
117
118 /*
119 * module configuration and status
120 */
121 static struct slgt_info *slgt_device_list;
122 static int slgt_device_count;
123
124 static int ttymajor;
125 static int debug_level;
126 static int maxframe[MAX_DEVICES];
127
128 module_param(ttymajor, int, 0);
129 module_param(debug_level, int, 0);
130 module_param_array(maxframe, int, NULL, 0);
131
132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
135
136 /*
137 * tty support and callbacks
138 */
139 static struct tty_driver *serial_driver;
140
141 static int open(struct tty_struct *tty, struct file * filp);
142 static void close(struct tty_struct *tty, struct file * filp);
143 static void hangup(struct tty_struct *tty);
144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
145
146 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
147 static int put_char(struct tty_struct *tty, unsigned char ch);
148 static void send_xchar(struct tty_struct *tty, char ch);
149 static void wait_until_sent(struct tty_struct *tty, int timeout);
150 static int write_room(struct tty_struct *tty);
151 static void flush_chars(struct tty_struct *tty);
152 static void flush_buffer(struct tty_struct *tty);
153 static void tx_hold(struct tty_struct *tty);
154 static void tx_release(struct tty_struct *tty);
155
156 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
157 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
158 static int chars_in_buffer(struct tty_struct *tty);
159 static void throttle(struct tty_struct * tty);
160 static void unthrottle(struct tty_struct * tty);
161 static int set_break(struct tty_struct *tty, int break_state);
162
163 /*
164 * generic HDLC support and callbacks
165 */
166 #if SYNCLINK_GENERIC_HDLC
167 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
168 static void hdlcdev_tx_done(struct slgt_info *info);
169 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
170 static int hdlcdev_init(struct slgt_info *info);
171 static void hdlcdev_exit(struct slgt_info *info);
172 #endif
173
174
175 /*
176 * device specific structures, macros and functions
177 */
178
179 #define SLGT_MAX_PORTS 4
180 #define SLGT_REG_SIZE 256
181
182 /*
183 * conditional wait facility
184 */
185 struct cond_wait {
186 struct cond_wait *next;
187 wait_queue_head_t q;
188 wait_queue_t wait;
189 unsigned int data;
190 };
191 static void init_cond_wait(struct cond_wait *w, unsigned int data);
192 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
194 static void flush_cond_wait(struct cond_wait **head);
195
196 /*
197 * DMA buffer descriptor and access macros
198 */
199 struct slgt_desc
200 {
201 __le16 count;
202 __le16 status;
203 __le32 pbuf; /* physical address of data buffer */
204 __le32 next; /* physical address of next descriptor */
205
206 /* driver book keeping */
207 char *buf; /* virtual address of data buffer */
208 unsigned int pdesc; /* physical address of this descriptor */
209 dma_addr_t buf_dma_addr;
210 unsigned short buf_count;
211 };
212
213 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
214 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
215 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
216 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
217 #define desc_count(a) (le16_to_cpu((a).count))
218 #define desc_status(a) (le16_to_cpu((a).status))
219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
224
225 struct _input_signal_events {
226 int ri_up;
227 int ri_down;
228 int dsr_up;
229 int dsr_down;
230 int dcd_up;
231 int dcd_down;
232 int cts_up;
233 int cts_down;
234 };
235
236 /*
237 * device instance data structure
238 */
239 struct slgt_info {
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
242
243 struct slgt_info *next_device; /* device list link */
244
245 int magic;
246
247 char device_name[25];
248 struct pci_dev *pdev;
249
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
253
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
256
257 int line; /* tty line instance number */
258
259 struct mgsl_icount icount;
260
261 int timeout;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
265
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
270
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
273
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
275
276 struct work_struct task;
277 u32 pending_bh;
278 bool bh_requested;
279 bool bh_running;
280
281 int isr_overflow;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
284
285 /* device configuration */
286
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
290
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
292 u32 phys_reg_addr;
293 bool reg_addr_requested;
294
295 MGSL_PARAMS params; /* communications parameters */
296 u32 idle_mode;
297 u32 max_frame_size; /* as set by device config */
298
299 unsigned int rbuf_fill_level;
300 unsigned int if_mode;
301
302 /* device status */
303
304 bool rx_enabled;
305 bool rx_restart;
306
307 bool tx_enabled;
308 bool tx_active;
309
310 unsigned char signals; /* serial signal states */
311 int init_error; /* initialization error */
312
313 unsigned char *tx_buf;
314 int tx_count;
315
316 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
317 char char_buf[MAX_ASYNC_BUFFER_SIZE];
318 bool drop_rts_on_tx_done;
319 struct _input_signal_events input_signal_events;
320
321 int dcd_chkcount; /* check counts to prevent */
322 int cts_chkcount; /* too many IRQs if a signal */
323 int dsr_chkcount; /* is floating */
324 int ri_chkcount;
325
326 char *bufs; /* virtual address of DMA buffer lists */
327 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
328
329 unsigned int rbuf_count;
330 struct slgt_desc *rbufs;
331 unsigned int rbuf_current;
332 unsigned int rbuf_index;
333
334 unsigned int tbuf_count;
335 struct slgt_desc *tbufs;
336 unsigned int tbuf_current;
337 unsigned int tbuf_start;
338
339 unsigned char *tmp_rbuf;
340 unsigned int tmp_rbuf_count;
341
342 /* SPPP/Cisco HDLC device parts */
343
344 int netcount;
345 spinlock_t netlock;
346 #if SYNCLINK_GENERIC_HDLC
347 struct net_device *netdev;
348 #endif
349
350 };
351
352 static MGSL_PARAMS default_params = {
353 .mode = MGSL_MODE_HDLC,
354 .loopback = 0,
355 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
356 .encoding = HDLC_ENCODING_NRZI_SPACE,
357 .clock_speed = 0,
358 .addr_filter = 0xff,
359 .crc_type = HDLC_CRC_16_CCITT,
360 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
361 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
362 .data_rate = 9600,
363 .data_bits = 8,
364 .stop_bits = 1,
365 .parity = ASYNC_PARITY_NONE
366 };
367
368
369 #define BH_RECEIVE 1
370 #define BH_TRANSMIT 2
371 #define BH_STATUS 4
372 #define IO_PIN_SHUTDOWN_LIMIT 100
373
374 #define DMABUFSIZE 256
375 #define DESC_LIST_SIZE 4096
376
377 #define MASK_PARITY BIT1
378 #define MASK_FRAMING BIT0
379 #define MASK_BREAK BIT14
380 #define MASK_OVERRUN BIT4
381
382 #define GSR 0x00 /* global status */
383 #define JCR 0x04 /* JTAG control */
384 #define IODR 0x08 /* GPIO direction */
385 #define IOER 0x0c /* GPIO interrupt enable */
386 #define IOVR 0x10 /* GPIO value */
387 #define IOSR 0x14 /* GPIO interrupt status */
388 #define TDR 0x80 /* tx data */
389 #define RDR 0x80 /* rx data */
390 #define TCR 0x82 /* tx control */
391 #define TIR 0x84 /* tx idle */
392 #define TPR 0x85 /* tx preamble */
393 #define RCR 0x86 /* rx control */
394 #define VCR 0x88 /* V.24 control */
395 #define CCR 0x89 /* clock control */
396 #define BDR 0x8a /* baud divisor */
397 #define SCR 0x8c /* serial control */
398 #define SSR 0x8e /* serial status */
399 #define RDCSR 0x90 /* rx DMA control/status */
400 #define TDCSR 0x94 /* tx DMA control/status */
401 #define RDDAR 0x98 /* rx DMA descriptor address */
402 #define TDDAR 0x9c /* tx DMA descriptor address */
403
404 #define RXIDLE BIT14
405 #define RXBREAK BIT14
406 #define IRQ_TXDATA BIT13
407 #define IRQ_TXIDLE BIT12
408 #define IRQ_TXUNDER BIT11 /* HDLC */
409 #define IRQ_RXDATA BIT10
410 #define IRQ_RXIDLE BIT9 /* HDLC */
411 #define IRQ_RXBREAK BIT9 /* async */
412 #define IRQ_RXOVER BIT8
413 #define IRQ_DSR BIT7
414 #define IRQ_CTS BIT6
415 #define IRQ_DCD BIT5
416 #define IRQ_RI BIT4
417 #define IRQ_ALL 0x3ff0
418 #define IRQ_MASTER BIT0
419
420 #define slgt_irq_on(info, mask) \
421 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
422 #define slgt_irq_off(info, mask) \
423 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
424
425 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
426 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
427 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
428 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
429 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
430 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
431
432 static void msc_set_vcr(struct slgt_info *info);
433
434 static int startup(struct slgt_info *info);
435 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
436 static void shutdown(struct slgt_info *info);
437 static void program_hw(struct slgt_info *info);
438 static void change_params(struct slgt_info *info);
439
440 static int register_test(struct slgt_info *info);
441 static int irq_test(struct slgt_info *info);
442 static int loopback_test(struct slgt_info *info);
443 static int adapter_test(struct slgt_info *info);
444
445 static void reset_adapter(struct slgt_info *info);
446 static void reset_port(struct slgt_info *info);
447 static void async_mode(struct slgt_info *info);
448 static void sync_mode(struct slgt_info *info);
449
450 static void rx_stop(struct slgt_info *info);
451 static void rx_start(struct slgt_info *info);
452 static void reset_rbufs(struct slgt_info *info);
453 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
454 static void rdma_reset(struct slgt_info *info);
455 static bool rx_get_frame(struct slgt_info *info);
456 static bool rx_get_buf(struct slgt_info *info);
457
458 static void tx_start(struct slgt_info *info);
459 static void tx_stop(struct slgt_info *info);
460 static void tx_set_idle(struct slgt_info *info);
461 static unsigned int free_tbuf_count(struct slgt_info *info);
462 static unsigned int tbuf_bytes(struct slgt_info *info);
463 static void reset_tbufs(struct slgt_info *info);
464 static void tdma_reset(struct slgt_info *info);
465 static void tdma_start(struct slgt_info *info);
466 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
467
468 static void get_signals(struct slgt_info *info);
469 static void set_signals(struct slgt_info *info);
470 static void enable_loopback(struct slgt_info *info);
471 static void set_rate(struct slgt_info *info, u32 data_rate);
472
473 static int bh_action(struct slgt_info *info);
474 static void bh_handler(struct work_struct *work);
475 static void bh_transmit(struct slgt_info *info);
476 static void isr_serial(struct slgt_info *info);
477 static void isr_rdma(struct slgt_info *info);
478 static void isr_txeom(struct slgt_info *info, unsigned short status);
479 static void isr_tdma(struct slgt_info *info);
480
481 static int alloc_dma_bufs(struct slgt_info *info);
482 static void free_dma_bufs(struct slgt_info *info);
483 static int alloc_desc(struct slgt_info *info);
484 static void free_desc(struct slgt_info *info);
485 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
486 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
487
488 static int alloc_tmp_rbuf(struct slgt_info *info);
489 static void free_tmp_rbuf(struct slgt_info *info);
490
491 static void tx_timeout(unsigned long context);
492 static void rx_timeout(unsigned long context);
493
494 /*
495 * ioctl handlers
496 */
497 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
498 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
499 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
500 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
501 static int set_txidle(struct slgt_info *info, int idle_mode);
502 static int tx_enable(struct slgt_info *info, int enable);
503 static int tx_abort(struct slgt_info *info);
504 static int rx_enable(struct slgt_info *info, int enable);
505 static int modem_input_wait(struct slgt_info *info,int arg);
506 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
507 static int tiocmget(struct tty_struct *tty, struct file *file);
508 static int tiocmset(struct tty_struct *tty, struct file *file,
509 unsigned int set, unsigned int clear);
510 static int set_break(struct tty_struct *tty, int break_state);
511 static int get_interface(struct slgt_info *info, int __user *if_mode);
512 static int set_interface(struct slgt_info *info, int if_mode);
513 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
514 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
515 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
516
517 /*
518 * driver functions
519 */
520 static void add_device(struct slgt_info *info);
521 static void device_init(int adapter_num, struct pci_dev *pdev);
522 static int claim_resources(struct slgt_info *info);
523 static void release_resources(struct slgt_info *info);
524
525 /*
526 * DEBUG OUTPUT CODE
527 */
528 #ifndef DBGINFO
529 #define DBGINFO(fmt)
530 #endif
531 #ifndef DBGERR
532 #define DBGERR(fmt)
533 #endif
534 #ifndef DBGBH
535 #define DBGBH(fmt)
536 #endif
537 #ifndef DBGISR
538 #define DBGISR(fmt)
539 #endif
540
541 #ifdef DBGDATA
542 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
543 {
544 int i;
545 int linecount;
546 printk("%s %s data:\n",info->device_name, label);
547 while(count) {
548 linecount = (count > 16) ? 16 : count;
549 for(i=0; i < linecount; i++)
550 printk("%02X ",(unsigned char)data[i]);
551 for(;i<17;i++)
552 printk(" ");
553 for(i=0;i<linecount;i++) {
554 if (data[i]>=040 && data[i]<=0176)
555 printk("%c",data[i]);
556 else
557 printk(".");
558 }
559 printk("\n");
560 data += linecount;
561 count -= linecount;
562 }
563 }
564 #else
565 #define DBGDATA(info, buf, size, label)
566 #endif
567
568 #ifdef DBGTBUF
569 static void dump_tbufs(struct slgt_info *info)
570 {
571 int i;
572 printk("tbuf_current=%d\n", info->tbuf_current);
573 for (i=0 ; i < info->tbuf_count ; i++) {
574 printk("%d: count=%04X status=%04X\n",
575 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
576 }
577 }
578 #else
579 #define DBGTBUF(info)
580 #endif
581
582 #ifdef DBGRBUF
583 static void dump_rbufs(struct slgt_info *info)
584 {
585 int i;
586 printk("rbuf_current=%d\n", info->rbuf_current);
587 for (i=0 ; i < info->rbuf_count ; i++) {
588 printk("%d: count=%04X status=%04X\n",
589 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
590 }
591 }
592 #else
593 #define DBGRBUF(info)
594 #endif
595
596 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
597 {
598 #ifdef SANITY_CHECK
599 if (!info) {
600 printk("null struct slgt_info for (%s) in %s\n", devname, name);
601 return 1;
602 }
603 if (info->magic != MGSL_MAGIC) {
604 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
605 return 1;
606 }
607 #else
608 if (!info)
609 return 1;
610 #endif
611 return 0;
612 }
613
614 /**
615 * line discipline callback wrappers
616 *
617 * The wrappers maintain line discipline references
618 * while calling into the line discipline.
619 *
620 * ldisc_receive_buf - pass receive data to line discipline
621 */
622 static void ldisc_receive_buf(struct tty_struct *tty,
623 const __u8 *data, char *flags, int count)
624 {
625 struct tty_ldisc *ld;
626 if (!tty)
627 return;
628 ld = tty_ldisc_ref(tty);
629 if (ld) {
630 if (ld->ops->receive_buf)
631 ld->ops->receive_buf(tty, data, flags, count);
632 tty_ldisc_deref(ld);
633 }
634 }
635
636 /* tty callbacks */
637
638 static int open(struct tty_struct *tty, struct file *filp)
639 {
640 struct slgt_info *info;
641 int retval, line;
642 unsigned long flags;
643
644 line = tty->index;
645 if ((line < 0) || (line >= slgt_device_count)) {
646 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
647 return -ENODEV;
648 }
649
650 info = slgt_device_list;
651 while(info && info->line != line)
652 info = info->next_device;
653 if (sanity_check(info, tty->name, "open"))
654 return -ENODEV;
655 if (info->init_error) {
656 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
657 return -ENODEV;
658 }
659
660 tty->driver_data = info;
661 info->port.tty = tty;
662
663 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
664
665 /* If port is closing, signal caller to try again */
666 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
667 if (info->port.flags & ASYNC_CLOSING)
668 interruptible_sleep_on(&info->port.close_wait);
669 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
670 -EAGAIN : -ERESTARTSYS);
671 goto cleanup;
672 }
673
674 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
675
676 spin_lock_irqsave(&info->netlock, flags);
677 if (info->netcount) {
678 retval = -EBUSY;
679 spin_unlock_irqrestore(&info->netlock, flags);
680 goto cleanup;
681 }
682 info->port.count++;
683 spin_unlock_irqrestore(&info->netlock, flags);
684
685 if (info->port.count == 1) {
686 /* 1st open on this device, init hardware */
687 retval = startup(info);
688 if (retval < 0)
689 goto cleanup;
690 }
691
692 retval = block_til_ready(tty, filp, info);
693 if (retval) {
694 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
695 goto cleanup;
696 }
697
698 retval = 0;
699
700 cleanup:
701 if (retval) {
702 if (tty->count == 1)
703 info->port.tty = NULL; /* tty layer will release tty struct */
704 if(info->port.count)
705 info->port.count--;
706 }
707
708 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
709 return retval;
710 }
711
712 static void close(struct tty_struct *tty, struct file *filp)
713 {
714 struct slgt_info *info = tty->driver_data;
715
716 if (sanity_check(info, tty->name, "close"))
717 return;
718 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
719
720 if (tty_port_close_start(&info->port, tty, filp) == 0)
721 goto cleanup;
722
723 if (info->port.flags & ASYNC_INITIALIZED)
724 wait_until_sent(tty, info->timeout);
725 flush_buffer(tty);
726 tty_ldisc_flush(tty);
727
728 shutdown(info);
729
730 tty_port_close_end(&info->port, tty);
731 info->port.tty = NULL;
732 cleanup:
733 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
734 }
735
736 static void hangup(struct tty_struct *tty)
737 {
738 struct slgt_info *info = tty->driver_data;
739
740 if (sanity_check(info, tty->name, "hangup"))
741 return;
742 DBGINFO(("%s hangup\n", info->device_name));
743
744 flush_buffer(tty);
745 shutdown(info);
746
747 info->port.count = 0;
748 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
749 info->port.tty = NULL;
750
751 wake_up_interruptible(&info->port.open_wait);
752 }
753
754 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
755 {
756 struct slgt_info *info = tty->driver_data;
757 unsigned long flags;
758
759 DBGINFO(("%s set_termios\n", tty->driver->name));
760
761 change_params(info);
762
763 /* Handle transition to B0 status */
764 if (old_termios->c_cflag & CBAUD &&
765 !(tty->termios->c_cflag & CBAUD)) {
766 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
767 spin_lock_irqsave(&info->lock,flags);
768 set_signals(info);
769 spin_unlock_irqrestore(&info->lock,flags);
770 }
771
772 /* Handle transition away from B0 status */
773 if (!(old_termios->c_cflag & CBAUD) &&
774 tty->termios->c_cflag & CBAUD) {
775 info->signals |= SerialSignal_DTR;
776 if (!(tty->termios->c_cflag & CRTSCTS) ||
777 !test_bit(TTY_THROTTLED, &tty->flags)) {
778 info->signals |= SerialSignal_RTS;
779 }
780 spin_lock_irqsave(&info->lock,flags);
781 set_signals(info);
782 spin_unlock_irqrestore(&info->lock,flags);
783 }
784
785 /* Handle turning off CRTSCTS */
786 if (old_termios->c_cflag & CRTSCTS &&
787 !(tty->termios->c_cflag & CRTSCTS)) {
788 tty->hw_stopped = 0;
789 tx_release(tty);
790 }
791 }
792
793 static int write(struct tty_struct *tty,
794 const unsigned char *buf, int count)
795 {
796 int ret = 0;
797 struct slgt_info *info = tty->driver_data;
798 unsigned long flags;
799 unsigned int bufs_needed;
800
801 if (sanity_check(info, tty->name, "write"))
802 goto cleanup;
803 DBGINFO(("%s write count=%d\n", info->device_name, count));
804
805 if (!info->tx_buf)
806 goto cleanup;
807
808 if (count > info->max_frame_size) {
809 ret = -EIO;
810 goto cleanup;
811 }
812
813 if (!count)
814 goto cleanup;
815
816 if (!info->tx_active && info->tx_count) {
817 /* send accumulated data from send_char() */
818 tx_load(info, info->tx_buf, info->tx_count);
819 goto start;
820 }
821 bufs_needed = (count/DMABUFSIZE);
822 if (count % DMABUFSIZE)
823 ++bufs_needed;
824 if (bufs_needed > free_tbuf_count(info))
825 goto cleanup;
826
827 ret = info->tx_count = count;
828 tx_load(info, buf, count);
829 goto start;
830
831 start:
832 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
833 spin_lock_irqsave(&info->lock,flags);
834 if (!info->tx_active)
835 tx_start(info);
836 else
837 tdma_start(info);
838 spin_unlock_irqrestore(&info->lock,flags);
839 }
840
841 cleanup:
842 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
843 return ret;
844 }
845
846 static int put_char(struct tty_struct *tty, unsigned char ch)
847 {
848 struct slgt_info *info = tty->driver_data;
849 unsigned long flags;
850 int ret = 0;
851
852 if (sanity_check(info, tty->name, "put_char"))
853 return 0;
854 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
855 if (!info->tx_buf)
856 return 0;
857 spin_lock_irqsave(&info->lock,flags);
858 if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
859 info->tx_buf[info->tx_count++] = ch;
860 ret = 1;
861 }
862 spin_unlock_irqrestore(&info->lock,flags);
863 return ret;
864 }
865
866 static void send_xchar(struct tty_struct *tty, char ch)
867 {
868 struct slgt_info *info = tty->driver_data;
869 unsigned long flags;
870
871 if (sanity_check(info, tty->name, "send_xchar"))
872 return;
873 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
874 info->x_char = ch;
875 if (ch) {
876 spin_lock_irqsave(&info->lock,flags);
877 if (!info->tx_enabled)
878 tx_start(info);
879 spin_unlock_irqrestore(&info->lock,flags);
880 }
881 }
882
883 static void wait_until_sent(struct tty_struct *tty, int timeout)
884 {
885 struct slgt_info *info = tty->driver_data;
886 unsigned long orig_jiffies, char_time;
887
888 if (!info )
889 return;
890 if (sanity_check(info, tty->name, "wait_until_sent"))
891 return;
892 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
893 if (!(info->port.flags & ASYNC_INITIALIZED))
894 goto exit;
895
896 orig_jiffies = jiffies;
897
898 /* Set check interval to 1/5 of estimated time to
899 * send a character, and make it at least 1. The check
900 * interval should also be less than the timeout.
901 * Note: use tight timings here to satisfy the NIST-PCTS.
902 */
903
904 lock_kernel();
905
906 if (info->params.data_rate) {
907 char_time = info->timeout/(32 * 5);
908 if (!char_time)
909 char_time++;
910 } else
911 char_time = 1;
912
913 if (timeout)
914 char_time = min_t(unsigned long, char_time, timeout);
915
916 while (info->tx_active) {
917 msleep_interruptible(jiffies_to_msecs(char_time));
918 if (signal_pending(current))
919 break;
920 if (timeout && time_after(jiffies, orig_jiffies + timeout))
921 break;
922 }
923 unlock_kernel();
924
925 exit:
926 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
927 }
928
929 static int write_room(struct tty_struct *tty)
930 {
931 struct slgt_info *info = tty->driver_data;
932 int ret;
933
934 if (sanity_check(info, tty->name, "write_room"))
935 return 0;
936 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
937 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
938 return ret;
939 }
940
941 static void flush_chars(struct tty_struct *tty)
942 {
943 struct slgt_info *info = tty->driver_data;
944 unsigned long flags;
945
946 if (sanity_check(info, tty->name, "flush_chars"))
947 return;
948 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
949
950 if (info->tx_count <= 0 || tty->stopped ||
951 tty->hw_stopped || !info->tx_buf)
952 return;
953
954 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
955
956 spin_lock_irqsave(&info->lock,flags);
957 if (!info->tx_active && info->tx_count) {
958 tx_load(info, info->tx_buf,info->tx_count);
959 tx_start(info);
960 }
961 spin_unlock_irqrestore(&info->lock,flags);
962 }
963
964 static void flush_buffer(struct tty_struct *tty)
965 {
966 struct slgt_info *info = tty->driver_data;
967 unsigned long flags;
968
969 if (sanity_check(info, tty->name, "flush_buffer"))
970 return;
971 DBGINFO(("%s flush_buffer\n", info->device_name));
972
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 info->tx_count = 0;
976 spin_unlock_irqrestore(&info->lock,flags);
977
978 tty_wakeup(tty);
979 }
980
981 /*
982 * throttle (stop) transmitter
983 */
984 static void tx_hold(struct tty_struct *tty)
985 {
986 struct slgt_info *info = tty->driver_data;
987 unsigned long flags;
988
989 if (sanity_check(info, tty->name, "tx_hold"))
990 return;
991 DBGINFO(("%s tx_hold\n", info->device_name));
992 spin_lock_irqsave(&info->lock,flags);
993 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
994 tx_stop(info);
995 spin_unlock_irqrestore(&info->lock,flags);
996 }
997
998 /*
999 * release (start) transmitter
1000 */
1001 static void tx_release(struct tty_struct *tty)
1002 {
1003 struct slgt_info *info = tty->driver_data;
1004 unsigned long flags;
1005
1006 if (sanity_check(info, tty->name, "tx_release"))
1007 return;
1008 DBGINFO(("%s tx_release\n", info->device_name));
1009 spin_lock_irqsave(&info->lock,flags);
1010 if (!info->tx_active && info->tx_count) {
1011 tx_load(info, info->tx_buf, info->tx_count);
1012 tx_start(info);
1013 }
1014 spin_unlock_irqrestore(&info->lock,flags);
1015 }
1016
1017 /*
1018 * Service an IOCTL request
1019 *
1020 * Arguments
1021 *
1022 * tty pointer to tty instance data
1023 * file pointer to associated file object for device
1024 * cmd IOCTL command code
1025 * arg command argument/context
1026 *
1027 * Return 0 if success, otherwise error code
1028 */
1029 static int ioctl(struct tty_struct *tty, struct file *file,
1030 unsigned int cmd, unsigned long arg)
1031 {
1032 struct slgt_info *info = tty->driver_data;
1033 struct mgsl_icount cnow; /* kernel counter temps */
1034 struct serial_icounter_struct __user *p_cuser; /* user space */
1035 unsigned long flags;
1036 void __user *argp = (void __user *)arg;
1037 int ret;
1038
1039 if (sanity_check(info, tty->name, "ioctl"))
1040 return -ENODEV;
1041 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1042
1043 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1044 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1045 if (tty->flags & (1 << TTY_IO_ERROR))
1046 return -EIO;
1047 }
1048
1049 lock_kernel();
1050
1051 switch (cmd) {
1052 case MGSL_IOCGPARAMS:
1053 ret = get_params(info, argp);
1054 break;
1055 case MGSL_IOCSPARAMS:
1056 ret = set_params(info, argp);
1057 break;
1058 case MGSL_IOCGTXIDLE:
1059 ret = get_txidle(info, argp);
1060 break;
1061 case MGSL_IOCSTXIDLE:
1062 ret = set_txidle(info, (int)arg);
1063 break;
1064 case MGSL_IOCTXENABLE:
1065 ret = tx_enable(info, (int)arg);
1066 break;
1067 case MGSL_IOCRXENABLE:
1068 ret = rx_enable(info, (int)arg);
1069 break;
1070 case MGSL_IOCTXABORT:
1071 ret = tx_abort(info);
1072 break;
1073 case MGSL_IOCGSTATS:
1074 ret = get_stats(info, argp);
1075 break;
1076 case MGSL_IOCWAITEVENT:
1077 ret = wait_mgsl_event(info, argp);
1078 break;
1079 case TIOCMIWAIT:
1080 ret = modem_input_wait(info,(int)arg);
1081 break;
1082 case MGSL_IOCGIF:
1083 ret = get_interface(info, argp);
1084 break;
1085 case MGSL_IOCSIF:
1086 ret = set_interface(info,(int)arg);
1087 break;
1088 case MGSL_IOCSGPIO:
1089 ret = set_gpio(info, argp);
1090 break;
1091 case MGSL_IOCGGPIO:
1092 ret = get_gpio(info, argp);
1093 break;
1094 case MGSL_IOCWAITGPIO:
1095 ret = wait_gpio(info, argp);
1096 break;
1097 case TIOCGICOUNT:
1098 spin_lock_irqsave(&info->lock,flags);
1099 cnow = info->icount;
1100 spin_unlock_irqrestore(&info->lock,flags);
1101 p_cuser = argp;
1102 if (put_user(cnow.cts, &p_cuser->cts) ||
1103 put_user(cnow.dsr, &p_cuser->dsr) ||
1104 put_user(cnow.rng, &p_cuser->rng) ||
1105 put_user(cnow.dcd, &p_cuser->dcd) ||
1106 put_user(cnow.rx, &p_cuser->rx) ||
1107 put_user(cnow.tx, &p_cuser->tx) ||
1108 put_user(cnow.frame, &p_cuser->frame) ||
1109 put_user(cnow.overrun, &p_cuser->overrun) ||
1110 put_user(cnow.parity, &p_cuser->parity) ||
1111 put_user(cnow.brk, &p_cuser->brk) ||
1112 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1113 ret = -EFAULT;
1114 ret = 0;
1115 break;
1116 default:
1117 ret = -ENOIOCTLCMD;
1118 }
1119 unlock_kernel();
1120 return ret;
1121 }
1122
1123 /*
1124 * support for 32 bit ioctl calls on 64 bit systems
1125 */
1126 #ifdef CONFIG_COMPAT
1127 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1128 {
1129 struct MGSL_PARAMS32 tmp_params;
1130
1131 DBGINFO(("%s get_params32\n", info->device_name));
1132 tmp_params.mode = (compat_ulong_t)info->params.mode;
1133 tmp_params.loopback = info->params.loopback;
1134 tmp_params.flags = info->params.flags;
1135 tmp_params.encoding = info->params.encoding;
1136 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1137 tmp_params.addr_filter = info->params.addr_filter;
1138 tmp_params.crc_type = info->params.crc_type;
1139 tmp_params.preamble_length = info->params.preamble_length;
1140 tmp_params.preamble = info->params.preamble;
1141 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1142 tmp_params.data_bits = info->params.data_bits;
1143 tmp_params.stop_bits = info->params.stop_bits;
1144 tmp_params.parity = info->params.parity;
1145 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1146 return -EFAULT;
1147 return 0;
1148 }
1149
1150 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1151 {
1152 struct MGSL_PARAMS32 tmp_params;
1153
1154 DBGINFO(("%s set_params32\n", info->device_name));
1155 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1156 return -EFAULT;
1157
1158 spin_lock(&info->lock);
1159 info->params.mode = tmp_params.mode;
1160 info->params.loopback = tmp_params.loopback;
1161 info->params.flags = tmp_params.flags;
1162 info->params.encoding = tmp_params.encoding;
1163 info->params.clock_speed = tmp_params.clock_speed;
1164 info->params.addr_filter = tmp_params.addr_filter;
1165 info->params.crc_type = tmp_params.crc_type;
1166 info->params.preamble_length = tmp_params.preamble_length;
1167 info->params.preamble = tmp_params.preamble;
1168 info->params.data_rate = tmp_params.data_rate;
1169 info->params.data_bits = tmp_params.data_bits;
1170 info->params.stop_bits = tmp_params.stop_bits;
1171 info->params.parity = tmp_params.parity;
1172 spin_unlock(&info->lock);
1173
1174 change_params(info);
1175
1176 return 0;
1177 }
1178
1179 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1180 unsigned int cmd, unsigned long arg)
1181 {
1182 struct slgt_info *info = tty->driver_data;
1183 int rc = -ENOIOCTLCMD;
1184
1185 if (sanity_check(info, tty->name, "compat_ioctl"))
1186 return -ENODEV;
1187 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1188
1189 switch (cmd) {
1190
1191 case MGSL_IOCSPARAMS32:
1192 rc = set_params32(info, compat_ptr(arg));
1193 break;
1194
1195 case MGSL_IOCGPARAMS32:
1196 rc = get_params32(info, compat_ptr(arg));
1197 break;
1198
1199 case MGSL_IOCGPARAMS:
1200 case MGSL_IOCSPARAMS:
1201 case MGSL_IOCGTXIDLE:
1202 case MGSL_IOCGSTATS:
1203 case MGSL_IOCWAITEVENT:
1204 case MGSL_IOCGIF:
1205 case MGSL_IOCSGPIO:
1206 case MGSL_IOCGGPIO:
1207 case MGSL_IOCWAITGPIO:
1208 case TIOCGICOUNT:
1209 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1210 break;
1211
1212 case MGSL_IOCSTXIDLE:
1213 case MGSL_IOCTXENABLE:
1214 case MGSL_IOCRXENABLE:
1215 case MGSL_IOCTXABORT:
1216 case TIOCMIWAIT:
1217 case MGSL_IOCSIF:
1218 rc = ioctl(tty, file, cmd, arg);
1219 break;
1220 }
1221
1222 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1223 return rc;
1224 }
1225 #else
1226 #define slgt_compat_ioctl NULL
1227 #endif /* ifdef CONFIG_COMPAT */
1228
1229 /*
1230 * proc fs support
1231 */
1232 static inline int line_info(char *buf, struct slgt_info *info)
1233 {
1234 char stat_buf[30];
1235 int ret;
1236 unsigned long flags;
1237
1238 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1239 info->device_name, info->phys_reg_addr,
1240 info->irq_level, info->max_frame_size);
1241
1242 /* output current serial signal states */
1243 spin_lock_irqsave(&info->lock,flags);
1244 get_signals(info);
1245 spin_unlock_irqrestore(&info->lock,flags);
1246
1247 stat_buf[0] = 0;
1248 stat_buf[1] = 0;
1249 if (info->signals & SerialSignal_RTS)
1250 strcat(stat_buf, "|RTS");
1251 if (info->signals & SerialSignal_CTS)
1252 strcat(stat_buf, "|CTS");
1253 if (info->signals & SerialSignal_DTR)
1254 strcat(stat_buf, "|DTR");
1255 if (info->signals & SerialSignal_DSR)
1256 strcat(stat_buf, "|DSR");
1257 if (info->signals & SerialSignal_DCD)
1258 strcat(stat_buf, "|CD");
1259 if (info->signals & SerialSignal_RI)
1260 strcat(stat_buf, "|RI");
1261
1262 if (info->params.mode != MGSL_MODE_ASYNC) {
1263 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1264 info->icount.txok, info->icount.rxok);
1265 if (info->icount.txunder)
1266 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1267 if (info->icount.txabort)
1268 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1269 if (info->icount.rxshort)
1270 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1271 if (info->icount.rxlong)
1272 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1273 if (info->icount.rxover)
1274 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1275 if (info->icount.rxcrc)
1276 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1277 } else {
1278 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1279 info->icount.tx, info->icount.rx);
1280 if (info->icount.frame)
1281 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1282 if (info->icount.parity)
1283 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1284 if (info->icount.brk)
1285 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1286 if (info->icount.overrun)
1287 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1288 }
1289
1290 /* Append serial signal status to end */
1291 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1292
1293 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1294 info->tx_active,info->bh_requested,info->bh_running,
1295 info->pending_bh);
1296
1297 return ret;
1298 }
1299
1300 /* Called to print information about devices
1301 */
1302 static int read_proc(char *page, char **start, off_t off, int count,
1303 int *eof, void *data)
1304 {
1305 int len = 0, l;
1306 off_t begin = 0;
1307 struct slgt_info *info;
1308
1309 len += sprintf(page, "synclink_gt driver\n");
1310
1311 info = slgt_device_list;
1312 while( info ) {
1313 l = line_info(page + len, info);
1314 len += l;
1315 if (len+begin > off+count)
1316 goto done;
1317 if (len+begin < off) {
1318 begin += len;
1319 len = 0;
1320 }
1321 info = info->next_device;
1322 }
1323
1324 *eof = 1;
1325 done:
1326 if (off >= len+begin)
1327 return 0;
1328 *start = page + (off-begin);
1329 return ((count < begin+len-off) ? count : begin+len-off);
1330 }
1331
1332 /*
1333 * return count of bytes in transmit buffer
1334 */
1335 static int chars_in_buffer(struct tty_struct *tty)
1336 {
1337 struct slgt_info *info = tty->driver_data;
1338 int count;
1339 if (sanity_check(info, tty->name, "chars_in_buffer"))
1340 return 0;
1341 count = tbuf_bytes(info);
1342 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1343 return count;
1344 }
1345
1346 /*
1347 * signal remote device to throttle send data (our receive data)
1348 */
1349 static void throttle(struct tty_struct * tty)
1350 {
1351 struct slgt_info *info = tty->driver_data;
1352 unsigned long flags;
1353
1354 if (sanity_check(info, tty->name, "throttle"))
1355 return;
1356 DBGINFO(("%s throttle\n", info->device_name));
1357 if (I_IXOFF(tty))
1358 send_xchar(tty, STOP_CHAR(tty));
1359 if (tty->termios->c_cflag & CRTSCTS) {
1360 spin_lock_irqsave(&info->lock,flags);
1361 info->signals &= ~SerialSignal_RTS;
1362 set_signals(info);
1363 spin_unlock_irqrestore(&info->lock,flags);
1364 }
1365 }
1366
1367 /*
1368 * signal remote device to stop throttling send data (our receive data)
1369 */
1370 static void unthrottle(struct tty_struct * tty)
1371 {
1372 struct slgt_info *info = tty->driver_data;
1373 unsigned long flags;
1374
1375 if (sanity_check(info, tty->name, "unthrottle"))
1376 return;
1377 DBGINFO(("%s unthrottle\n", info->device_name));
1378 if (I_IXOFF(tty)) {
1379 if (info->x_char)
1380 info->x_char = 0;
1381 else
1382 send_xchar(tty, START_CHAR(tty));
1383 }
1384 if (tty->termios->c_cflag & CRTSCTS) {
1385 spin_lock_irqsave(&info->lock,flags);
1386 info->signals |= SerialSignal_RTS;
1387 set_signals(info);
1388 spin_unlock_irqrestore(&info->lock,flags);
1389 }
1390 }
1391
1392 /*
1393 * set or clear transmit break condition
1394 * break_state -1=set break condition, 0=clear
1395 */
1396 static int set_break(struct tty_struct *tty, int break_state)
1397 {
1398 struct slgt_info *info = tty->driver_data;
1399 unsigned short value;
1400 unsigned long flags;
1401
1402 if (sanity_check(info, tty->name, "set_break"))
1403 return -EINVAL;
1404 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1405
1406 spin_lock_irqsave(&info->lock,flags);
1407 value = rd_reg16(info, TCR);
1408 if (break_state == -1)
1409 value |= BIT6;
1410 else
1411 value &= ~BIT6;
1412 wr_reg16(info, TCR, value);
1413 spin_unlock_irqrestore(&info->lock,flags);
1414 return 0;
1415 }
1416
1417 #if SYNCLINK_GENERIC_HDLC
1418
1419 /**
1420 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1421 * set encoding and frame check sequence (FCS) options
1422 *
1423 * dev pointer to network device structure
1424 * encoding serial encoding setting
1425 * parity FCS setting
1426 *
1427 * returns 0 if success, otherwise error code
1428 */
1429 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1430 unsigned short parity)
1431 {
1432 struct slgt_info *info = dev_to_port(dev);
1433 unsigned char new_encoding;
1434 unsigned short new_crctype;
1435
1436 /* return error if TTY interface open */
1437 if (info->port.count)
1438 return -EBUSY;
1439
1440 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1441
1442 switch (encoding)
1443 {
1444 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1445 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1446 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1447 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1448 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1449 default: return -EINVAL;
1450 }
1451
1452 switch (parity)
1453 {
1454 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1455 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1456 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1457 default: return -EINVAL;
1458 }
1459
1460 info->params.encoding = new_encoding;
1461 info->params.crc_type = new_crctype;
1462
1463 /* if network interface up, reprogram hardware */
1464 if (info->netcount)
1465 program_hw(info);
1466
1467 return 0;
1468 }
1469
1470 /**
1471 * called by generic HDLC layer to send frame
1472 *
1473 * skb socket buffer containing HDLC frame
1474 * dev pointer to network device structure
1475 *
1476 * returns 0 if success, otherwise error code
1477 */
1478 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1479 {
1480 struct slgt_info *info = dev_to_port(dev);
1481 unsigned long flags;
1482
1483 DBGINFO(("%s hdlc_xmit\n", dev->name));
1484
1485 /* stop sending until this frame completes */
1486 netif_stop_queue(dev);
1487
1488 /* copy data to device buffers */
1489 info->tx_count = skb->len;
1490 tx_load(info, skb->data, skb->len);
1491
1492 /* update network statistics */
1493 dev->stats.tx_packets++;
1494 dev->stats.tx_bytes += skb->len;
1495
1496 /* done with socket buffer, so free it */
1497 dev_kfree_skb(skb);
1498
1499 /* save start time for transmit timeout detection */
1500 dev->trans_start = jiffies;
1501
1502 /* start hardware transmitter if necessary */
1503 spin_lock_irqsave(&info->lock,flags);
1504 if (!info->tx_active)
1505 tx_start(info);
1506 spin_unlock_irqrestore(&info->lock,flags);
1507
1508 return 0;
1509 }
1510
1511 /**
1512 * called by network layer when interface enabled
1513 * claim resources and initialize hardware
1514 *
1515 * dev pointer to network device structure
1516 *
1517 * returns 0 if success, otherwise error code
1518 */
1519 static int hdlcdev_open(struct net_device *dev)
1520 {
1521 struct slgt_info *info = dev_to_port(dev);
1522 int rc;
1523 unsigned long flags;
1524
1525 if (!try_module_get(THIS_MODULE))
1526 return -EBUSY;
1527
1528 DBGINFO(("%s hdlcdev_open\n", dev->name));
1529
1530 /* generic HDLC layer open processing */
1531 if ((rc = hdlc_open(dev)))
1532 return rc;
1533
1534 /* arbitrate between network and tty opens */
1535 spin_lock_irqsave(&info->netlock, flags);
1536 if (info->port.count != 0 || info->netcount != 0) {
1537 DBGINFO(("%s hdlc_open busy\n", dev->name));
1538 spin_unlock_irqrestore(&info->netlock, flags);
1539 return -EBUSY;
1540 }
1541 info->netcount=1;
1542 spin_unlock_irqrestore(&info->netlock, flags);
1543
1544 /* claim resources and init adapter */
1545 if ((rc = startup(info)) != 0) {
1546 spin_lock_irqsave(&info->netlock, flags);
1547 info->netcount=0;
1548 spin_unlock_irqrestore(&info->netlock, flags);
1549 return rc;
1550 }
1551
1552 /* assert DTR and RTS, apply hardware settings */
1553 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1554 program_hw(info);
1555
1556 /* enable network layer transmit */
1557 dev->trans_start = jiffies;
1558 netif_start_queue(dev);
1559
1560 /* inform generic HDLC layer of current DCD status */
1561 spin_lock_irqsave(&info->lock, flags);
1562 get_signals(info);
1563 spin_unlock_irqrestore(&info->lock, flags);
1564 if (info->signals & SerialSignal_DCD)
1565 netif_carrier_on(dev);
1566 else
1567 netif_carrier_off(dev);
1568 return 0;
1569 }
1570
1571 /**
1572 * called by network layer when interface is disabled
1573 * shutdown hardware and release resources
1574 *
1575 * dev pointer to network device structure
1576 *
1577 * returns 0 if success, otherwise error code
1578 */
1579 static int hdlcdev_close(struct net_device *dev)
1580 {
1581 struct slgt_info *info = dev_to_port(dev);
1582 unsigned long flags;
1583
1584 DBGINFO(("%s hdlcdev_close\n", dev->name));
1585
1586 netif_stop_queue(dev);
1587
1588 /* shutdown adapter and release resources */
1589 shutdown(info);
1590
1591 hdlc_close(dev);
1592
1593 spin_lock_irqsave(&info->netlock, flags);
1594 info->netcount=0;
1595 spin_unlock_irqrestore(&info->netlock, flags);
1596
1597 module_put(THIS_MODULE);
1598 return 0;
1599 }
1600
1601 /**
1602 * called by network layer to process IOCTL call to network device
1603 *
1604 * dev pointer to network device structure
1605 * ifr pointer to network interface request structure
1606 * cmd IOCTL command code
1607 *
1608 * returns 0 if success, otherwise error code
1609 */
1610 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1611 {
1612 const size_t size = sizeof(sync_serial_settings);
1613 sync_serial_settings new_line;
1614 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1615 struct slgt_info *info = dev_to_port(dev);
1616 unsigned int flags;
1617
1618 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1619
1620 /* return error if TTY interface open */
1621 if (info->port.count)
1622 return -EBUSY;
1623
1624 if (cmd != SIOCWANDEV)
1625 return hdlc_ioctl(dev, ifr, cmd);
1626
1627 switch(ifr->ifr_settings.type) {
1628 case IF_GET_IFACE: /* return current sync_serial_settings */
1629
1630 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1631 if (ifr->ifr_settings.size < size) {
1632 ifr->ifr_settings.size = size; /* data size wanted */
1633 return -ENOBUFS;
1634 }
1635
1636 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1637 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1638 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1639 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1640
1641 switch (flags){
1642 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1643 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1644 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1645 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1646 default: new_line.clock_type = CLOCK_DEFAULT;
1647 }
1648
1649 new_line.clock_rate = info->params.clock_speed;
1650 new_line.loopback = info->params.loopback ? 1:0;
1651
1652 if (copy_to_user(line, &new_line, size))
1653 return -EFAULT;
1654 return 0;
1655
1656 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1657
1658 if(!capable(CAP_NET_ADMIN))
1659 return -EPERM;
1660 if (copy_from_user(&new_line, line, size))
1661 return -EFAULT;
1662
1663 switch (new_line.clock_type)
1664 {
1665 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1666 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1667 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1668 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1669 case CLOCK_DEFAULT: flags = info->params.flags &
1670 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1671 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1672 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1673 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1674 default: return -EINVAL;
1675 }
1676
1677 if (new_line.loopback != 0 && new_line.loopback != 1)
1678 return -EINVAL;
1679
1680 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1681 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1682 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1683 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1684 info->params.flags |= flags;
1685
1686 info->params.loopback = new_line.loopback;
1687
1688 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1689 info->params.clock_speed = new_line.clock_rate;
1690 else
1691 info->params.clock_speed = 0;
1692
1693 /* if network interface up, reprogram hardware */
1694 if (info->netcount)
1695 program_hw(info);
1696 return 0;
1697
1698 default:
1699 return hdlc_ioctl(dev, ifr, cmd);
1700 }
1701 }
1702
1703 /**
1704 * called by network layer when transmit timeout is detected
1705 *
1706 * dev pointer to network device structure
1707 */
1708 static void hdlcdev_tx_timeout(struct net_device *dev)
1709 {
1710 struct slgt_info *info = dev_to_port(dev);
1711 unsigned long flags;
1712
1713 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1714
1715 dev->stats.tx_errors++;
1716 dev->stats.tx_aborted_errors++;
1717
1718 spin_lock_irqsave(&info->lock,flags);
1719 tx_stop(info);
1720 spin_unlock_irqrestore(&info->lock,flags);
1721
1722 netif_wake_queue(dev);
1723 }
1724
1725 /**
1726 * called by device driver when transmit completes
1727 * reenable network layer transmit if stopped
1728 *
1729 * info pointer to device instance information
1730 */
1731 static void hdlcdev_tx_done(struct slgt_info *info)
1732 {
1733 if (netif_queue_stopped(info->netdev))
1734 netif_wake_queue(info->netdev);
1735 }
1736
1737 /**
1738 * called by device driver when frame received
1739 * pass frame to network layer
1740 *
1741 * info pointer to device instance information
1742 * buf pointer to buffer contianing frame data
1743 * size count of data bytes in buf
1744 */
1745 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1746 {
1747 struct sk_buff *skb = dev_alloc_skb(size);
1748 struct net_device *dev = info->netdev;
1749
1750 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1751
1752 if (skb == NULL) {
1753 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1754 dev->stats.rx_dropped++;
1755 return;
1756 }
1757
1758 memcpy(skb_put(skb, size), buf, size);
1759
1760 skb->protocol = hdlc_type_trans(skb, dev);
1761
1762 dev->stats.rx_packets++;
1763 dev->stats.rx_bytes += size;
1764
1765 netif_rx(skb);
1766 }
1767
1768 static const struct net_device_ops hdlcdev_ops = {
1769 .ndo_open = hdlcdev_open,
1770 .ndo_stop = hdlcdev_close,
1771 .ndo_change_mtu = hdlc_change_mtu,
1772 .ndo_start_xmit = hdlc_start_xmit,
1773 .ndo_do_ioctl = hdlcdev_ioctl,
1774 .ndo_tx_timeout = hdlcdev_tx_timeout,
1775 };
1776
1777 /**
1778 * called by device driver when adding device instance
1779 * do generic HDLC initialization
1780 *
1781 * info pointer to device instance information
1782 *
1783 * returns 0 if success, otherwise error code
1784 */
1785 static int hdlcdev_init(struct slgt_info *info)
1786 {
1787 int rc;
1788 struct net_device *dev;
1789 hdlc_device *hdlc;
1790
1791 /* allocate and initialize network and HDLC layer objects */
1792
1793 if (!(dev = alloc_hdlcdev(info))) {
1794 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1795 return -ENOMEM;
1796 }
1797
1798 /* for network layer reporting purposes only */
1799 dev->mem_start = info->phys_reg_addr;
1800 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1801 dev->irq = info->irq_level;
1802
1803 /* network layer callbacks and settings */
1804 dev->netdev_ops = &hdlcdev_ops;
1805 dev->watchdog_timeo = 10 * HZ;
1806 dev->tx_queue_len = 50;
1807
1808 /* generic HDLC layer callbacks and settings */
1809 hdlc = dev_to_hdlc(dev);
1810 hdlc->attach = hdlcdev_attach;
1811 hdlc->xmit = hdlcdev_xmit;
1812
1813 /* register objects with HDLC layer */
1814 if ((rc = register_hdlc_device(dev))) {
1815 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1816 free_netdev(dev);
1817 return rc;
1818 }
1819
1820 info->netdev = dev;
1821 return 0;
1822 }
1823
1824 /**
1825 * called by device driver when removing device instance
1826 * do generic HDLC cleanup
1827 *
1828 * info pointer to device instance information
1829 */
1830 static void hdlcdev_exit(struct slgt_info *info)
1831 {
1832 unregister_hdlc_device(info->netdev);
1833 free_netdev(info->netdev);
1834 info->netdev = NULL;
1835 }
1836
1837 #endif /* ifdef CONFIG_HDLC */
1838
1839 /*
1840 * get async data from rx DMA buffers
1841 */
1842 static void rx_async(struct slgt_info *info)
1843 {
1844 struct tty_struct *tty = info->port.tty;
1845 struct mgsl_icount *icount = &info->icount;
1846 unsigned int start, end;
1847 unsigned char *p;
1848 unsigned char status;
1849 struct slgt_desc *bufs = info->rbufs;
1850 int i, count;
1851 int chars = 0;
1852 int stat;
1853 unsigned char ch;
1854
1855 start = end = info->rbuf_current;
1856
1857 while(desc_complete(bufs[end])) {
1858 count = desc_count(bufs[end]) - info->rbuf_index;
1859 p = bufs[end].buf + info->rbuf_index;
1860
1861 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1862 DBGDATA(info, p, count, "rx");
1863
1864 for(i=0 ; i < count; i+=2, p+=2) {
1865 ch = *p;
1866 icount->rx++;
1867
1868 stat = 0;
1869
1870 if ((status = *(p+1) & (BIT1 + BIT0))) {
1871 if (status & BIT1)
1872 icount->parity++;
1873 else if (status & BIT0)
1874 icount->frame++;
1875 /* discard char if tty control flags say so */
1876 if (status & info->ignore_status_mask)
1877 continue;
1878 if (status & BIT1)
1879 stat = TTY_PARITY;
1880 else if (status & BIT0)
1881 stat = TTY_FRAME;
1882 }
1883 if (tty) {
1884 tty_insert_flip_char(tty, ch, stat);
1885 chars++;
1886 }
1887 }
1888
1889 if (i < count) {
1890 /* receive buffer not completed */
1891 info->rbuf_index += i;
1892 mod_timer(&info->rx_timer, jiffies + 1);
1893 break;
1894 }
1895
1896 info->rbuf_index = 0;
1897 free_rbufs(info, end, end);
1898
1899 if (++end == info->rbuf_count)
1900 end = 0;
1901
1902 /* if entire list searched then no frame available */
1903 if (end == start)
1904 break;
1905 }
1906
1907 if (tty && chars)
1908 tty_flip_buffer_push(tty);
1909 }
1910
1911 /*
1912 * return next bottom half action to perform
1913 */
1914 static int bh_action(struct slgt_info *info)
1915 {
1916 unsigned long flags;
1917 int rc;
1918
1919 spin_lock_irqsave(&info->lock,flags);
1920
1921 if (info->pending_bh & BH_RECEIVE) {
1922 info->pending_bh &= ~BH_RECEIVE;
1923 rc = BH_RECEIVE;
1924 } else if (info->pending_bh & BH_TRANSMIT) {
1925 info->pending_bh &= ~BH_TRANSMIT;
1926 rc = BH_TRANSMIT;
1927 } else if (info->pending_bh & BH_STATUS) {
1928 info->pending_bh &= ~BH_STATUS;
1929 rc = BH_STATUS;
1930 } else {
1931 /* Mark BH routine as complete */
1932 info->bh_running = false;
1933 info->bh_requested = false;
1934 rc = 0;
1935 }
1936
1937 spin_unlock_irqrestore(&info->lock,flags);
1938
1939 return rc;
1940 }
1941
1942 /*
1943 * perform bottom half processing
1944 */
1945 static void bh_handler(struct work_struct *work)
1946 {
1947 struct slgt_info *info = container_of(work, struct slgt_info, task);
1948 int action;
1949
1950 if (!info)
1951 return;
1952 info->bh_running = true;
1953
1954 while((action = bh_action(info))) {
1955 switch (action) {
1956 case BH_RECEIVE:
1957 DBGBH(("%s bh receive\n", info->device_name));
1958 switch(info->params.mode) {
1959 case MGSL_MODE_ASYNC:
1960 rx_async(info);
1961 break;
1962 case MGSL_MODE_HDLC:
1963 while(rx_get_frame(info));
1964 break;
1965 case MGSL_MODE_RAW:
1966 case MGSL_MODE_MONOSYNC:
1967 case MGSL_MODE_BISYNC:
1968 while(rx_get_buf(info));
1969 break;
1970 }
1971 /* restart receiver if rx DMA buffers exhausted */
1972 if (info->rx_restart)
1973 rx_start(info);
1974 break;
1975 case BH_TRANSMIT:
1976 bh_transmit(info);
1977 break;
1978 case BH_STATUS:
1979 DBGBH(("%s bh status\n", info->device_name));
1980 info->ri_chkcount = 0;
1981 info->dsr_chkcount = 0;
1982 info->dcd_chkcount = 0;
1983 info->cts_chkcount = 0;
1984 break;
1985 default:
1986 DBGBH(("%s unknown action\n", info->device_name));
1987 break;
1988 }
1989 }
1990 DBGBH(("%s bh_handler exit\n", info->device_name));
1991 }
1992
1993 static void bh_transmit(struct slgt_info *info)
1994 {
1995 struct tty_struct *tty = info->port.tty;
1996
1997 DBGBH(("%s bh_transmit\n", info->device_name));
1998 if (tty)
1999 tty_wakeup(tty);
2000 }
2001
2002 static void dsr_change(struct slgt_info *info, unsigned short status)
2003 {
2004 if (status & BIT3) {
2005 info->signals |= SerialSignal_DSR;
2006 info->input_signal_events.dsr_up++;
2007 } else {
2008 info->signals &= ~SerialSignal_DSR;
2009 info->input_signal_events.dsr_down++;
2010 }
2011 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2012 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2013 slgt_irq_off(info, IRQ_DSR);
2014 return;
2015 }
2016 info->icount.dsr++;
2017 wake_up_interruptible(&info->status_event_wait_q);
2018 wake_up_interruptible(&info->event_wait_q);
2019 info->pending_bh |= BH_STATUS;
2020 }
2021
2022 static void cts_change(struct slgt_info *info, unsigned short status)
2023 {
2024 if (status & BIT2) {
2025 info->signals |= SerialSignal_CTS;
2026 info->input_signal_events.cts_up++;
2027 } else {
2028 info->signals &= ~SerialSignal_CTS;
2029 info->input_signal_events.cts_down++;
2030 }
2031 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2032 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2033 slgt_irq_off(info, IRQ_CTS);
2034 return;
2035 }
2036 info->icount.cts++;
2037 wake_up_interruptible(&info->status_event_wait_q);
2038 wake_up_interruptible(&info->event_wait_q);
2039 info->pending_bh |= BH_STATUS;
2040
2041 if (info->port.flags & ASYNC_CTS_FLOW) {
2042 if (info->port.tty) {
2043 if (info->port.tty->hw_stopped) {
2044 if (info->signals & SerialSignal_CTS) {
2045 info->port.tty->hw_stopped = 0;
2046 info->pending_bh |= BH_TRANSMIT;
2047 return;
2048 }
2049 } else {
2050 if (!(info->signals & SerialSignal_CTS))
2051 info->port.tty->hw_stopped = 1;
2052 }
2053 }
2054 }
2055 }
2056
2057 static void dcd_change(struct slgt_info *info, unsigned short status)
2058 {
2059 if (status & BIT1) {
2060 info->signals |= SerialSignal_DCD;
2061 info->input_signal_events.dcd_up++;
2062 } else {
2063 info->signals &= ~SerialSignal_DCD;
2064 info->input_signal_events.dcd_down++;
2065 }
2066 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2067 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2068 slgt_irq_off(info, IRQ_DCD);
2069 return;
2070 }
2071 info->icount.dcd++;
2072 #if SYNCLINK_GENERIC_HDLC
2073 if (info->netcount) {
2074 if (info->signals & SerialSignal_DCD)
2075 netif_carrier_on(info->netdev);
2076 else
2077 netif_carrier_off(info->netdev);
2078 }
2079 #endif
2080 wake_up_interruptible(&info->status_event_wait_q);
2081 wake_up_interruptible(&info->event_wait_q);
2082 info->pending_bh |= BH_STATUS;
2083
2084 if (info->port.flags & ASYNC_CHECK_CD) {
2085 if (info->signals & SerialSignal_DCD)
2086 wake_up_interruptible(&info->port.open_wait);
2087 else {
2088 if (info->port.tty)
2089 tty_hangup(info->port.tty);
2090 }
2091 }
2092 }
2093
2094 static void ri_change(struct slgt_info *info, unsigned short status)
2095 {
2096 if (status & BIT0) {
2097 info->signals |= SerialSignal_RI;
2098 info->input_signal_events.ri_up++;
2099 } else {
2100 info->signals &= ~SerialSignal_RI;
2101 info->input_signal_events.ri_down++;
2102 }
2103 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2104 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2105 slgt_irq_off(info, IRQ_RI);
2106 return;
2107 }
2108 info->icount.rng++;
2109 wake_up_interruptible(&info->status_event_wait_q);
2110 wake_up_interruptible(&info->event_wait_q);
2111 info->pending_bh |= BH_STATUS;
2112 }
2113
2114 static void isr_serial(struct slgt_info *info)
2115 {
2116 unsigned short status = rd_reg16(info, SSR);
2117
2118 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2119
2120 wr_reg16(info, SSR, status); /* clear pending */
2121
2122 info->irq_occurred = true;
2123
2124 if (info->params.mode == MGSL_MODE_ASYNC) {
2125 if (status & IRQ_TXIDLE) {
2126 if (info->tx_count)
2127 isr_txeom(info, status);
2128 }
2129 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2130 info->icount.brk++;
2131 /* process break detection if tty control allows */
2132 if (info->port.tty) {
2133 if (!(status & info->ignore_status_mask)) {
2134 if (info->read_status_mask & MASK_BREAK) {
2135 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2136 if (info->port.flags & ASYNC_SAK)
2137 do_SAK(info->port.tty);
2138 }
2139 }
2140 }
2141 }
2142 } else {
2143 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2144 isr_txeom(info, status);
2145
2146 if (status & IRQ_RXIDLE) {
2147 if (status & RXIDLE)
2148 info->icount.rxidle++;
2149 else
2150 info->icount.exithunt++;
2151 wake_up_interruptible(&info->event_wait_q);
2152 }
2153
2154 if (status & IRQ_RXOVER)
2155 rx_start(info);
2156 }
2157
2158 if (status & IRQ_DSR)
2159 dsr_change(info, status);
2160 if (status & IRQ_CTS)
2161 cts_change(info, status);
2162 if (status & IRQ_DCD)
2163 dcd_change(info, status);
2164 if (status & IRQ_RI)
2165 ri_change(info, status);
2166 }
2167
2168 static void isr_rdma(struct slgt_info *info)
2169 {
2170 unsigned int status = rd_reg32(info, RDCSR);
2171
2172 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2173
2174 /* RDCSR (rx DMA control/status)
2175 *
2176 * 31..07 reserved
2177 * 06 save status byte to DMA buffer
2178 * 05 error
2179 * 04 eol (end of list)
2180 * 03 eob (end of buffer)
2181 * 02 IRQ enable
2182 * 01 reset
2183 * 00 enable
2184 */
2185 wr_reg32(info, RDCSR, status); /* clear pending */
2186
2187 if (status & (BIT5 + BIT4)) {
2188 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2189 info->rx_restart = true;
2190 }
2191 info->pending_bh |= BH_RECEIVE;
2192 }
2193
2194 static void isr_tdma(struct slgt_info *info)
2195 {
2196 unsigned int status = rd_reg32(info, TDCSR);
2197
2198 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2199
2200 /* TDCSR (tx DMA control/status)
2201 *
2202 * 31..06 reserved
2203 * 05 error
2204 * 04 eol (end of list)
2205 * 03 eob (end of buffer)
2206 * 02 IRQ enable
2207 * 01 reset
2208 * 00 enable
2209 */
2210 wr_reg32(info, TDCSR, status); /* clear pending */
2211
2212 if (status & (BIT5 + BIT4 + BIT3)) {
2213 // another transmit buffer has completed
2214 // run bottom half to get more send data from user
2215 info->pending_bh |= BH_TRANSMIT;
2216 }
2217 }
2218
2219 static void isr_txeom(struct slgt_info *info, unsigned short status)
2220 {
2221 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2222
2223 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2224 tdma_reset(info);
2225 reset_tbufs(info);
2226 if (status & IRQ_TXUNDER) {
2227 unsigned short val = rd_reg16(info, TCR);
2228 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2229 wr_reg16(info, TCR, val); /* clear reset bit */
2230 }
2231
2232 if (info->tx_active) {
2233 if (info->params.mode != MGSL_MODE_ASYNC) {
2234 if (status & IRQ_TXUNDER)
2235 info->icount.txunder++;
2236 else if (status & IRQ_TXIDLE)
2237 info->icount.txok++;
2238 }
2239
2240 info->tx_active = false;
2241 info->tx_count = 0;
2242
2243 del_timer(&info->tx_timer);
2244
2245 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2246 info->signals &= ~SerialSignal_RTS;
2247 info->drop_rts_on_tx_done = false;
2248 set_signals(info);
2249 }
2250
2251 #if SYNCLINK_GENERIC_HDLC
2252 if (info->netcount)
2253 hdlcdev_tx_done(info);
2254 else
2255 #endif
2256 {
2257 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2258 tx_stop(info);
2259 return;
2260 }
2261 info->pending_bh |= BH_TRANSMIT;
2262 }
2263 }
2264 }
2265
2266 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2267 {
2268 struct cond_wait *w, *prev;
2269
2270 /* wake processes waiting for specific transitions */
2271 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2272 if (w->data & changed) {
2273 w->data = state;
2274 wake_up_interruptible(&w->q);
2275 if (prev != NULL)
2276 prev->next = w->next;
2277 else
2278 info->gpio_wait_q = w->next;
2279 } else
2280 prev = w;
2281 }
2282 }
2283
2284 /* interrupt service routine
2285 *
2286 * irq interrupt number
2287 * dev_id device ID supplied during interrupt registration
2288 */
2289 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2290 {
2291 struct slgt_info *info = dev_id;
2292 unsigned int gsr;
2293 unsigned int i;
2294
2295 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2296
2297 spin_lock(&info->lock);
2298
2299 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2300 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2301 info->irq_occurred = true;
2302 for(i=0; i < info->port_count ; i++) {
2303 if (info->port_array[i] == NULL)
2304 continue;
2305 if (gsr & (BIT8 << i))
2306 isr_serial(info->port_array[i]);
2307 if (gsr & (BIT16 << (i*2)))
2308 isr_rdma(info->port_array[i]);
2309 if (gsr & (BIT17 << (i*2)))
2310 isr_tdma(info->port_array[i]);
2311 }
2312 }
2313
2314 if (info->gpio_present) {
2315 unsigned int state;
2316 unsigned int changed;
2317 while ((changed = rd_reg32(info, IOSR)) != 0) {
2318 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2319 /* read latched state of GPIO signals */
2320 state = rd_reg32(info, IOVR);
2321 /* clear pending GPIO interrupt bits */
2322 wr_reg32(info, IOSR, changed);
2323 for (i=0 ; i < info->port_count ; i++) {
2324 if (info->port_array[i] != NULL)
2325 isr_gpio(info->port_array[i], changed, state);
2326 }
2327 }
2328 }
2329
2330 for(i=0; i < info->port_count ; i++) {
2331 struct slgt_info *port = info->port_array[i];
2332
2333 if (port && (port->port.count || port->netcount) &&
2334 port->pending_bh && !port->bh_running &&
2335 !port->bh_requested) {
2336 DBGISR(("%s bh queued\n", port->device_name));
2337 schedule_work(&port->task);
2338 port->bh_requested = true;
2339 }
2340 }
2341
2342 spin_unlock(&info->lock);
2343
2344 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2345 return IRQ_HANDLED;
2346 }
2347
2348 static int startup(struct slgt_info *info)
2349 {
2350 DBGINFO(("%s startup\n", info->device_name));
2351
2352 if (info->port.flags & ASYNC_INITIALIZED)
2353 return 0;
2354
2355 if (!info->tx_buf) {
2356 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2357 if (!info->tx_buf) {
2358 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2359 return -ENOMEM;
2360 }
2361 }
2362
2363 info->pending_bh = 0;
2364
2365 memset(&info->icount, 0, sizeof(info->icount));
2366
2367 /* program hardware for current parameters */
2368 change_params(info);
2369
2370 if (info->port.tty)
2371 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2372
2373 info->port.flags |= ASYNC_INITIALIZED;
2374
2375 return 0;
2376 }
2377
2378 /*
2379 * called by close() and hangup() to shutdown hardware
2380 */
2381 static void shutdown(struct slgt_info *info)
2382 {
2383 unsigned long flags;
2384
2385 if (!(info->port.flags & ASYNC_INITIALIZED))
2386 return;
2387
2388 DBGINFO(("%s shutdown\n", info->device_name));
2389
2390 /* clear status wait queue because status changes */
2391 /* can't happen after shutting down the hardware */
2392 wake_up_interruptible(&info->status_event_wait_q);
2393 wake_up_interruptible(&info->event_wait_q);
2394
2395 del_timer_sync(&info->tx_timer);
2396 del_timer_sync(&info->rx_timer);
2397
2398 kfree(info->tx_buf);
2399 info->tx_buf = NULL;
2400
2401 spin_lock_irqsave(&info->lock,flags);
2402
2403 tx_stop(info);
2404 rx_stop(info);
2405
2406 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2407
2408 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2409 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2410 set_signals(info);
2411 }
2412
2413 flush_cond_wait(&info->gpio_wait_q);
2414
2415 spin_unlock_irqrestore(&info->lock,flags);
2416
2417 if (info->port.tty)
2418 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2419
2420 info->port.flags &= ~ASYNC_INITIALIZED;
2421 }
2422
2423 static void program_hw(struct slgt_info *info)
2424 {
2425 unsigned long flags;
2426
2427 spin_lock_irqsave(&info->lock,flags);
2428
2429 rx_stop(info);
2430 tx_stop(info);
2431
2432 if (info->params.mode != MGSL_MODE_ASYNC ||
2433 info->netcount)
2434 sync_mode(info);
2435 else
2436 async_mode(info);
2437
2438 set_signals(info);
2439
2440 info->dcd_chkcount = 0;
2441 info->cts_chkcount = 0;
2442 info->ri_chkcount = 0;
2443 info->dsr_chkcount = 0;
2444
2445 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2446 get_signals(info);
2447
2448 if (info->netcount ||
2449 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2450 rx_start(info);
2451
2452 spin_unlock_irqrestore(&info->lock,flags);
2453 }
2454
2455 /*
2456 * reconfigure adapter based on new parameters
2457 */
2458 static void change_params(struct slgt_info *info)
2459 {
2460 unsigned cflag;
2461 int bits_per_char;
2462
2463 if (!info->port.tty || !info->port.tty->termios)
2464 return;
2465 DBGINFO(("%s change_params\n", info->device_name));
2466
2467 cflag = info->port.tty->termios->c_cflag;
2468
2469 /* if B0 rate (hangup) specified then negate DTR and RTS */
2470 /* otherwise assert DTR and RTS */
2471 if (cflag & CBAUD)
2472 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2473 else
2474 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2475
2476 /* byte size and parity */
2477
2478 switch (cflag & CSIZE) {
2479 case CS5: info->params.data_bits = 5; break;
2480 case CS6: info->params.data_bits = 6; break;
2481 case CS7: info->params.data_bits = 7; break;
2482 case CS8: info->params.data_bits = 8; break;
2483 default: info->params.data_bits = 7; break;
2484 }
2485
2486 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2487
2488 if (cflag & PARENB)
2489 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2490 else
2491 info->params.parity = ASYNC_PARITY_NONE;
2492
2493 /* calculate number of jiffies to transmit a full
2494 * FIFO (32 bytes) at specified data rate
2495 */
2496 bits_per_char = info->params.data_bits +
2497 info->params.stop_bits + 1;
2498
2499 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2500
2501 if (info->params.data_rate) {
2502 info->timeout = (32*HZ*bits_per_char) /
2503 info->params.data_rate;
2504 }
2505 info->timeout += HZ/50; /* Add .02 seconds of slop */
2506
2507 if (cflag & CRTSCTS)
2508 info->port.flags |= ASYNC_CTS_FLOW;
2509 else
2510 info->port.flags &= ~ASYNC_CTS_FLOW;
2511
2512 if (cflag & CLOCAL)
2513 info->port.flags &= ~ASYNC_CHECK_CD;
2514 else
2515 info->port.flags |= ASYNC_CHECK_CD;
2516
2517 /* process tty input control flags */
2518
2519 info->read_status_mask = IRQ_RXOVER;
2520 if (I_INPCK(info->port.tty))
2521 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2522 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2523 info->read_status_mask |= MASK_BREAK;
2524 if (I_IGNPAR(info->port.tty))
2525 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2526 if (I_IGNBRK(info->port.tty)) {
2527 info->ignore_status_mask |= MASK_BREAK;
2528 /* If ignoring parity and break indicators, ignore
2529 * overruns too. (For real raw support).
2530 */
2531 if (I_IGNPAR(info->port.tty))
2532 info->ignore_status_mask |= MASK_OVERRUN;
2533 }
2534
2535 program_hw(info);
2536 }
2537
2538 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2539 {
2540 DBGINFO(("%s get_stats\n", info->device_name));
2541 if (!user_icount) {
2542 memset(&info->icount, 0, sizeof(info->icount));
2543 } else {
2544 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2545 return -EFAULT;
2546 }
2547 return 0;
2548 }
2549
2550 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2551 {
2552 DBGINFO(("%s get_params\n", info->device_name));
2553 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2554 return -EFAULT;
2555 return 0;
2556 }
2557
2558 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2559 {
2560 unsigned long flags;
2561 MGSL_PARAMS tmp_params;
2562
2563 DBGINFO(("%s set_params\n", info->device_name));
2564 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2565 return -EFAULT;
2566
2567 spin_lock_irqsave(&info->lock, flags);
2568 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2569 spin_unlock_irqrestore(&info->lock, flags);
2570
2571 change_params(info);
2572
2573 return 0;
2574 }
2575
2576 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2577 {
2578 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2579 if (put_user(info->idle_mode, idle_mode))
2580 return -EFAULT;
2581 return 0;
2582 }
2583
2584 static int set_txidle(struct slgt_info *info, int idle_mode)
2585 {
2586 unsigned long flags;
2587 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2588 spin_lock_irqsave(&info->lock,flags);
2589 info->idle_mode = idle_mode;
2590 if (info->params.mode != MGSL_MODE_ASYNC)
2591 tx_set_idle(info);
2592 spin_unlock_irqrestore(&info->lock,flags);
2593 return 0;
2594 }
2595
2596 static int tx_enable(struct slgt_info *info, int enable)
2597 {
2598 unsigned long flags;
2599 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2600 spin_lock_irqsave(&info->lock,flags);
2601 if (enable) {
2602 if (!info->tx_enabled)
2603 tx_start(info);
2604 } else {
2605 if (info->tx_enabled)
2606 tx_stop(info);
2607 }
2608 spin_unlock_irqrestore(&info->lock,flags);
2609 return 0;
2610 }
2611
2612 /*
2613 * abort transmit HDLC frame
2614 */
2615 static int tx_abort(struct slgt_info *info)
2616 {
2617 unsigned long flags;
2618 DBGINFO(("%s tx_abort\n", info->device_name));
2619 spin_lock_irqsave(&info->lock,flags);
2620 tdma_reset(info);
2621 spin_unlock_irqrestore(&info->lock,flags);
2622 return 0;
2623 }
2624
2625 static int rx_enable(struct slgt_info *info, int enable)
2626 {
2627 unsigned long flags;
2628 unsigned int rbuf_fill_level;
2629 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2630 spin_lock_irqsave(&info->lock,flags);
2631 /*
2632 * enable[31..16] = receive DMA buffer fill level
2633 * 0 = noop (leave fill level unchanged)
2634 * fill level must be multiple of 4 and <= buffer size
2635 */
2636 rbuf_fill_level = ((unsigned int)enable) >> 16;
2637 if (rbuf_fill_level) {
2638 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2639 spin_unlock_irqrestore(&info->lock, flags);
2640 return -EINVAL;
2641 }
2642 info->rbuf_fill_level = rbuf_fill_level;
2643 rx_stop(info); /* restart receiver to use new fill level */
2644 }
2645
2646 /*
2647 * enable[1..0] = receiver enable command
2648 * 0 = disable
2649 * 1 = enable
2650 * 2 = enable or force hunt mode if already enabled
2651 */
2652 enable &= 3;
2653 if (enable) {
2654 if (!info->rx_enabled)
2655 rx_start(info);
2656 else if (enable == 2) {
2657 /* force hunt mode (write 1 to RCR[3]) */
2658 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2659 }
2660 } else {
2661 if (info->rx_enabled)
2662 rx_stop(info);
2663 }
2664 spin_unlock_irqrestore(&info->lock,flags);
2665 return 0;
2666 }
2667
2668 /*
2669 * wait for specified event to occur
2670 */
2671 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2672 {
2673 unsigned long flags;
2674 int s;
2675 int rc=0;
2676 struct mgsl_icount cprev, cnow;
2677 int events;
2678 int mask;
2679 struct _input_signal_events oldsigs, newsigs;
2680 DECLARE_WAITQUEUE(wait, current);
2681
2682 if (get_user(mask, mask_ptr))
2683 return -EFAULT;
2684
2685 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2686
2687 spin_lock_irqsave(&info->lock,flags);
2688
2689 /* return immediately if state matches requested events */
2690 get_signals(info);
2691 s = info->signals;
2692
2693 events = mask &
2694 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2695 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2696 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2697 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2698 if (events) {
2699 spin_unlock_irqrestore(&info->lock,flags);
2700 goto exit;
2701 }
2702
2703 /* save current irq counts */
2704 cprev = info->icount;
2705 oldsigs = info->input_signal_events;
2706
2707 /* enable hunt and idle irqs if needed */
2708 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2709 unsigned short val = rd_reg16(info, SCR);
2710 if (!(val & IRQ_RXIDLE))
2711 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2712 }
2713
2714 set_current_state(TASK_INTERRUPTIBLE);
2715 add_wait_queue(&info->event_wait_q, &wait);
2716
2717 spin_unlock_irqrestore(&info->lock,flags);
2718
2719 for(;;) {
2720 schedule();
2721 if (signal_pending(current)) {
2722 rc = -ERESTARTSYS;
2723 break;
2724 }
2725
2726 /* get current irq counts */
2727 spin_lock_irqsave(&info->lock,flags);
2728 cnow = info->icount;
2729 newsigs = info->input_signal_events;
2730 set_current_state(TASK_INTERRUPTIBLE);
2731 spin_unlock_irqrestore(&info->lock,flags);
2732
2733 /* if no change, wait aborted for some reason */
2734 if (newsigs.dsr_up == oldsigs.dsr_up &&
2735 newsigs.dsr_down == oldsigs.dsr_down &&
2736 newsigs.dcd_up == oldsigs.dcd_up &&
2737 newsigs.dcd_down == oldsigs.dcd_down &&
2738 newsigs.cts_up == oldsigs.cts_up &&
2739 newsigs.cts_down == oldsigs.cts_down &&
2740 newsigs.ri_up == oldsigs.ri_up &&
2741 newsigs.ri_down == oldsigs.ri_down &&
2742 cnow.exithunt == cprev.exithunt &&
2743 cnow.rxidle == cprev.rxidle) {
2744 rc = -EIO;
2745 break;
2746 }
2747
2748 events = mask &
2749 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2750 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2751 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2752 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2753 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2754 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2755 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2756 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2757 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2758 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2759 if (events)
2760 break;
2761
2762 cprev = cnow;
2763 oldsigs = newsigs;
2764 }
2765
2766 remove_wait_queue(&info->event_wait_q, &wait);
2767 set_current_state(TASK_RUNNING);
2768
2769
2770 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2771 spin_lock_irqsave(&info->lock,flags);
2772 if (!waitqueue_active(&info->event_wait_q)) {
2773 /* disable enable exit hunt mode/idle rcvd IRQs */
2774 wr_reg16(info, SCR,
2775 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2776 }
2777 spin_unlock_irqrestore(&info->lock,flags);
2778 }
2779 exit:
2780 if (rc == 0)
2781 rc = put_user(events, mask_ptr);
2782 return rc;
2783 }
2784
2785 static int get_interface(struct slgt_info *info, int __user *if_mode)
2786 {
2787 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2788 if (put_user(info->if_mode, if_mode))
2789 return -EFAULT;
2790 return 0;
2791 }
2792
2793 static int set_interface(struct slgt_info *info, int if_mode)
2794 {
2795 unsigned long flags;
2796 unsigned short val;
2797
2798 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2799 spin_lock_irqsave(&info->lock,flags);
2800 info->if_mode = if_mode;
2801
2802 msc_set_vcr(info);
2803
2804 /* TCR (tx control) 07 1=RTS driver control */
2805 val = rd_reg16(info, TCR);
2806 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2807 val |= BIT7;
2808 else
2809 val &= ~BIT7;
2810 wr_reg16(info, TCR, val);
2811
2812 spin_unlock_irqrestore(&info->lock,flags);
2813 return 0;
2814 }
2815
2816 /*
2817 * set general purpose IO pin state and direction
2818 *
2819 * user_gpio fields:
2820 * state each bit indicates a pin state
2821 * smask set bit indicates pin state to set
2822 * dir each bit indicates a pin direction (0=input, 1=output)
2823 * dmask set bit indicates pin direction to set
2824 */
2825 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2826 {
2827 unsigned long flags;
2828 struct gpio_desc gpio;
2829 __u32 data;
2830
2831 if (!info->gpio_present)
2832 return -EINVAL;
2833 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2834 return -EFAULT;
2835 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2836 info->device_name, gpio.state, gpio.smask,
2837 gpio.dir, gpio.dmask));
2838
2839 spin_lock_irqsave(&info->lock,flags);
2840 if (gpio.dmask) {
2841 data = rd_reg32(info, IODR);
2842 data |= gpio.dmask & gpio.dir;
2843 data &= ~(gpio.dmask & ~gpio.dir);
2844 wr_reg32(info, IODR, data);
2845 }
2846 if (gpio.smask) {
2847 data = rd_reg32(info, IOVR);
2848 data |= gpio.smask & gpio.state;
2849 data &= ~(gpio.smask & ~gpio.state);
2850 wr_reg32(info, IOVR, data);
2851 }
2852 spin_unlock_irqrestore(&info->lock,flags);
2853
2854 return 0;
2855 }
2856
2857 /*
2858 * get general purpose IO pin state and direction
2859 */
2860 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2861 {
2862 struct gpio_desc gpio;
2863 if (!info->gpio_present)
2864 return -EINVAL;
2865 gpio.state = rd_reg32(info, IOVR);
2866 gpio.smask = 0xffffffff;
2867 gpio.dir = rd_reg32(info, IODR);
2868 gpio.dmask = 0xffffffff;
2869 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2870 return -EFAULT;
2871 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2872 info->device_name, gpio.state, gpio.dir));
2873 return 0;
2874 }
2875
2876 /*
2877 * conditional wait facility
2878 */
2879 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2880 {
2881 init_waitqueue_head(&w->q);
2882 init_waitqueue_entry(&w->wait, current);
2883 w->data = data;
2884 }
2885
2886 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2887 {
2888 set_current_state(TASK_INTERRUPTIBLE);
2889 add_wait_queue(&w->q, &w->wait);
2890 w->next = *head;
2891 *head = w;
2892 }
2893
2894 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2895 {
2896 struct cond_wait *w, *prev;
2897 remove_wait_queue(&cw->q, &cw->wait);
2898 set_current_state(TASK_RUNNING);
2899 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2900 if (w == cw) {
2901 if (prev != NULL)
2902 prev->next = w->next;
2903 else
2904 *head = w->next;
2905 break;
2906 }
2907 }
2908 }
2909
2910 static void flush_cond_wait(struct cond_wait **head)
2911 {
2912 while (*head != NULL) {
2913 wake_up_interruptible(&(*head)->q);
2914 *head = (*head)->next;
2915 }
2916 }
2917
2918 /*
2919 * wait for general purpose I/O pin(s) to enter specified state
2920 *
2921 * user_gpio fields:
2922 * state - bit indicates target pin state
2923 * smask - set bit indicates watched pin
2924 *
2925 * The wait ends when at least one watched pin enters the specified
2926 * state. When 0 (no error) is returned, user_gpio->state is set to the
2927 * state of all GPIO pins when the wait ends.
2928 *
2929 * Note: Each pin may be a dedicated input, dedicated output, or
2930 * configurable input/output. The number and configuration of pins
2931 * varies with the specific adapter model. Only input pins (dedicated
2932 * or configured) can be monitored with this function.
2933 */
2934 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2935 {
2936 unsigned long flags;
2937 int rc = 0;
2938 struct gpio_desc gpio;
2939 struct cond_wait wait;
2940 u32 state;
2941
2942 if (!info->gpio_present)
2943 return -EINVAL;
2944 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2945 return -EFAULT;
2946 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2947 info->device_name, gpio.state, gpio.smask));
2948 /* ignore output pins identified by set IODR bit */
2949 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2950 return -EINVAL;
2951 init_cond_wait(&wait, gpio.smask);
2952
2953 spin_lock_irqsave(&info->lock, flags);
2954 /* enable interrupts for watched pins */
2955 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2956 /* get current pin states */
2957 state = rd_reg32(info, IOVR);
2958
2959 if (gpio.smask & ~(state ^ gpio.state)) {
2960 /* already in target state */
2961 gpio.state = state;
2962 } else {
2963 /* wait for target state */
2964 add_cond_wait(&info->gpio_wait_q, &wait);
2965 spin_unlock_irqrestore(&info->lock, flags);
2966 schedule();
2967 if (signal_pending(current))
2968 rc = -ERESTARTSYS;
2969 else
2970 gpio.state = wait.data;
2971 spin_lock_irqsave(&info->lock, flags);
2972 remove_cond_wait(&info->gpio_wait_q, &wait);
2973 }
2974
2975 /* disable all GPIO interrupts if no waiting processes */
2976 if (info->gpio_wait_q == NULL)
2977 wr_reg32(info, IOER, 0);
2978 spin_unlock_irqrestore(&info->lock,flags);
2979
2980 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2981 rc = -EFAULT;
2982 return rc;
2983 }
2984
2985 static int modem_input_wait(struct slgt_info *info,int arg)
2986 {
2987 unsigned long flags;
2988 int rc;
2989 struct mgsl_icount cprev, cnow;
2990 DECLARE_WAITQUEUE(wait, current);
2991
2992 /* save current irq counts */
2993 spin_lock_irqsave(&info->lock,flags);
2994 cprev = info->icount;
2995 add_wait_queue(&info->status_event_wait_q, &wait);
2996 set_current_state(TASK_INTERRUPTIBLE);
2997 spin_unlock_irqrestore(&info->lock,flags);
2998
2999 for(;;) {
3000 schedule();
3001 if (signal_pending(current)) {
3002 rc = -ERESTARTSYS;
3003 break;
3004 }
3005
3006 /* get new irq counts */
3007 spin_lock_irqsave(&info->lock,flags);
3008 cnow = info->icount;
3009 set_current_state(TASK_INTERRUPTIBLE);
3010 spin_unlock_irqrestore(&info->lock,flags);
3011
3012 /* if no change, wait aborted for some reason */
3013 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3014 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3015 rc = -EIO;
3016 break;
3017 }
3018
3019 /* check for change in caller specified modem input */
3020 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3021 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3022 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3023 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3024 rc = 0;
3025 break;
3026 }
3027
3028 cprev = cnow;
3029 }
3030 remove_wait_queue(&info->status_event_wait_q, &wait);
3031 set_current_state(TASK_RUNNING);
3032 return rc;
3033 }
3034
3035 /*
3036 * return state of serial control and status signals
3037 */
3038 static int tiocmget(struct tty_struct *tty, struct file *file)
3039 {
3040 struct slgt_info *info = tty->driver_data;
3041 unsigned int result;
3042 unsigned long flags;
3043
3044 spin_lock_irqsave(&info->lock,flags);
3045 get_signals(info);
3046 spin_unlock_irqrestore(&info->lock,flags);
3047
3048 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3049 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3050 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3051 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3052 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3053 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3054
3055 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3056 return result;
3057 }
3058
3059 /*
3060 * set modem control signals (DTR/RTS)
3061 *
3062 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3063 * TIOCMSET = set/clear signal values
3064 * value bit mask for command
3065 */
3066 static int tiocmset(struct tty_struct *tty, struct file *file,
3067 unsigned int set, unsigned int clear)
3068 {
3069 struct slgt_info *info = tty->driver_data;
3070 unsigned long flags;
3071
3072 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3073
3074 if (set & TIOCM_RTS)
3075 info->signals |= SerialSignal_RTS;
3076 if (set & TIOCM_DTR)
3077 info->signals |= SerialSignal_DTR;
3078 if (clear & TIOCM_RTS)
3079 info->signals &= ~SerialSignal_RTS;
3080 if (clear & TIOCM_DTR)
3081 info->signals &= ~SerialSignal_DTR;
3082
3083 spin_lock_irqsave(&info->lock,flags);
3084 set_signals(info);
3085 spin_unlock_irqrestore(&info->lock,flags);
3086 return 0;
3087 }
3088
3089 static int carrier_raised(struct tty_port *port)
3090 {
3091 unsigned long flags;
3092 struct slgt_info *info = container_of(port, struct slgt_info, port);
3093
3094 spin_lock_irqsave(&info->lock,flags);
3095 get_signals(info);
3096 spin_unlock_irqrestore(&info->lock,flags);
3097 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3098 }
3099
3100 static void raise_dtr_rts(struct tty_port *port)
3101 {
3102 unsigned long flags;
3103 struct slgt_info *info = container_of(port, struct slgt_info, port);
3104
3105 spin_lock_irqsave(&info->lock,flags);
3106 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3107 set_signals(info);
3108 spin_unlock_irqrestore(&info->lock,flags);
3109 }
3110
3111
3112 /*
3113 * block current process until the device is ready to open
3114 */
3115 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3116 struct slgt_info *info)
3117 {
3118 DECLARE_WAITQUEUE(wait, current);
3119 int retval;
3120 bool do_clocal = false;
3121 bool extra_count = false;
3122 unsigned long flags;
3123 int cd;
3124 struct tty_port *port = &info->port;
3125
3126 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3127
3128 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3129 /* nonblock mode is set or port is not enabled */
3130 port->flags |= ASYNC_NORMAL_ACTIVE;
3131 return 0;
3132 }
3133
3134 if (tty->termios->c_cflag & CLOCAL)
3135 do_clocal = true;
3136
3137 /* Wait for carrier detect and the line to become
3138 * free (i.e., not in use by the callout). While we are in
3139 * this loop, port->count is dropped by one, so that
3140 * close() knows when to free things. We restore it upon
3141 * exit, either normal or abnormal.
3142 */
3143
3144 retval = 0;
3145 add_wait_queue(&port->open_wait, &wait);
3146
3147 spin_lock_irqsave(&info->lock, flags);
3148 if (!tty_hung_up_p(filp)) {
3149 extra_count = true;
3150 port->count--;
3151 }
3152 spin_unlock_irqrestore(&info->lock, flags);
3153 port->blocked_open++;
3154
3155 while (1) {
3156 if ((tty->termios->c_cflag & CBAUD))
3157 tty_port_raise_dtr_rts(port);
3158
3159 set_current_state(TASK_INTERRUPTIBLE);
3160
3161 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3162 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3163 -EAGAIN : -ERESTARTSYS;
3164 break;
3165 }
3166
3167 cd = tty_port_carrier_raised(port);
3168
3169 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3170 break;
3171
3172 if (signal_pending(current)) {
3173 retval = -ERESTARTSYS;
3174 break;
3175 }
3176
3177 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3178 schedule();
3179 }
3180
3181 set_current_state(TASK_RUNNING);
3182 remove_wait_queue(&port->open_wait, &wait);
3183
3184 if (extra_count)
3185 port->count++;
3186 port->blocked_open--;
3187
3188 if (!retval)
3189 port->flags |= ASYNC_NORMAL_ACTIVE;
3190
3191 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3192 return retval;
3193 }
3194
3195 static int alloc_tmp_rbuf(struct slgt_info *info)
3196 {
3197 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3198 if (info->tmp_rbuf == NULL)
3199 return -ENOMEM;
3200 return 0;
3201 }
3202
3203 static void free_tmp_rbuf(struct slgt_info *info)
3204 {
3205 kfree(info->tmp_rbuf);
3206 info->tmp_rbuf = NULL;
3207 }
3208
3209 /*
3210 * allocate DMA descriptor lists.
3211 */
3212 static int alloc_desc(struct slgt_info *info)
3213 {
3214 unsigned int i;
3215 unsigned int pbufs;
3216
3217 /* allocate memory to hold descriptor lists */
3218 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3219 if (info->bufs == NULL)
3220 return -ENOMEM;
3221
3222 memset(info->bufs, 0, DESC_LIST_SIZE);
3223
3224 info->rbufs = (struct slgt_desc*)info->bufs;
3225 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3226
3227 pbufs = (unsigned int)info->bufs_dma_addr;
3228
3229 /*
3230 * Build circular lists of descriptors
3231 */
3232
3233 for (i=0; i < info->rbuf_count; i++) {
3234 /* physical address of this descriptor */
3235 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3236
3237 /* physical address of next descriptor */
3238 if (i == info->rbuf_count - 1)
3239 info->rbufs[i].next = cpu_to_le32(pbufs);
3240 else
3241 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3242 set_desc_count(info->rbufs[i], DMABUFSIZE);
3243 }
3244
3245 for (i=0; i < info->tbuf_count; i++) {
3246 /* physical address of this descriptor */
3247 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3248
3249 /* physical address of next descriptor */
3250 if (i == info->tbuf_count - 1)
3251 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3252 else
3253 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3254 }
3255
3256 return 0;
3257 }
3258
3259 static void free_desc(struct slgt_info *info)
3260 {
3261 if (info->bufs != NULL) {
3262 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3263 info->bufs = NULL;
3264 info->rbufs = NULL;
3265 info->tbufs = NULL;
3266 }
3267 }
3268
3269 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3270 {
3271 int i;
3272 for (i=0; i < count; i++) {
3273 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3274 return -ENOMEM;
3275 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3276 }
3277 return 0;
3278 }
3279
3280 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3281 {
3282 int i;
3283 for (i=0; i < count; i++) {
3284 if (bufs[i].buf == NULL)
3285 continue;
3286 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3287 bufs[i].buf = NULL;
3288 }
3289 }
3290
3291 static int alloc_dma_bufs(struct slgt_info *info)
3292 {
3293 info->rbuf_count = 32;
3294 info->tbuf_count = 32;
3295
3296 if (alloc_desc(info) < 0 ||
3297 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3298 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3299 alloc_tmp_rbuf(info) < 0) {
3300 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3301 return -ENOMEM;
3302 }
3303 reset_rbufs(info);
3304 return 0;
3305 }
3306
3307 static void free_dma_bufs(struct slgt_info *info)
3308 {
3309 if (info->bufs) {
3310 free_bufs(info, info->rbufs, info->rbuf_count);
3311 free_bufs(info, info->tbufs, info->tbuf_count);
3312 free_desc(info);
3313 }
3314 free_tmp_rbuf(info);
3315 }
3316
3317 static int claim_resources(struct slgt_info *info)
3318 {
3319 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3320 DBGERR(("%s reg addr conflict, addr=%08X\n",
3321 info->device_name, info->phys_reg_addr));
3322 info->init_error = DiagStatus_AddressConflict;
3323 goto errout;
3324 }
3325 else
3326 info->reg_addr_requested = true;
3327
3328 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3329 if (!info->reg_addr) {
3330 DBGERR(("%s cant map device registers, addr=%08X\n",
3331 info->device_name, info->phys_reg_addr));
3332 info->init_error = DiagStatus_CantAssignPciResources;
3333 goto errout;
3334 }
3335 return 0;
3336
3337 errout:
3338 release_resources(info);
3339 return -ENODEV;
3340 }
3341
3342 static void release_resources(struct slgt_info *info)
3343 {
3344 if (info->irq_requested) {
3345 free_irq(info->irq_level, info);
3346 info->irq_requested = false;
3347 }
3348
3349 if (info->reg_addr_requested) {
3350 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3351 info->reg_addr_requested = false;
3352 }
3353
3354 if (info->reg_addr) {
3355 iounmap(info->reg_addr);
3356 info->reg_addr = NULL;
3357 }
3358 }
3359
3360 /* Add the specified device instance data structure to the
3361 * global linked list of devices and increment the device count.
3362 */
3363 static void add_device(struct slgt_info *info)
3364 {
3365 char *devstr;
3366
3367 info->next_device = NULL;
3368 info->line = slgt_device_count;
3369 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3370
3371 if (info->line < MAX_DEVICES) {
3372 if (maxframe[info->line])
3373 info->max_frame_size = maxframe[info->line];
3374 }
3375
3376 slgt_device_count++;
3377
3378 if (!slgt_device_list)
3379 slgt_device_list = info;
3380 else {
3381 struct slgt_info *current_dev = slgt_device_list;
3382 while(current_dev->next_device)
3383 current_dev = current_dev->next_device;
3384 current_dev->next_device = info;
3385 }
3386
3387 if (info->max_frame_size < 4096)
3388 info->max_frame_size = 4096;
3389 else if (info->max_frame_size > 65535)
3390 info->max_frame_size = 65535;
3391
3392 switch(info->pdev->device) {
3393 case SYNCLINK_GT_DEVICE_ID:
3394 devstr = "GT";
3395 break;
3396 case SYNCLINK_GT2_DEVICE_ID:
3397 devstr = "GT2";
3398 break;
3399 case SYNCLINK_GT4_DEVICE_ID:
3400 devstr = "GT4";
3401 break;
3402 case SYNCLINK_AC_DEVICE_ID:
3403 devstr = "AC";
3404 info->params.mode = MGSL_MODE_ASYNC;
3405 break;
3406 default:
3407 devstr = "(unknown model)";
3408 }
3409 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3410 devstr, info->device_name, info->phys_reg_addr,
3411 info->irq_level, info->max_frame_size);
3412
3413 #if SYNCLINK_GENERIC_HDLC
3414 hdlcdev_init(info);
3415 #endif
3416 }
3417
3418 static const struct tty_port_operations slgt_port_ops = {
3419 .carrier_raised = carrier_raised,
3420 .raise_dtr_rts = raise_dtr_rts,
3421 };
3422
3423 /*
3424 * allocate device instance structure, return NULL on failure
3425 */
3426 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3427 {
3428 struct slgt_info *info;
3429
3430 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3431
3432 if (!info) {
3433 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3434 driver_name, adapter_num, port_num));
3435 } else {
3436 tty_port_init(&info->port);
3437 info->port.ops = &slgt_port_ops;
3438 info->magic = MGSL_MAGIC;
3439 INIT_WORK(&info->task, bh_handler);
3440 info->max_frame_size = 4096;
3441 info->rbuf_fill_level = DMABUFSIZE;
3442 info->port.close_delay = 5*HZ/10;
3443 info->port.closing_wait = 30*HZ;
3444 init_waitqueue_head(&info->status_event_wait_q);
3445 init_waitqueue_head(&info->event_wait_q);
3446 spin_lock_init(&info->netlock);
3447 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3448 info->idle_mode = HDLC_TXIDLE_FLAGS;
3449 info->adapter_num = adapter_num;
3450 info->port_num = port_num;
3451
3452 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3453 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3454
3455 /* Copy configuration info to device instance data */
3456 info->pdev = pdev;
3457 info->irq_level = pdev->irq;
3458 info->phys_reg_addr = pci_resource_start(pdev,0);
3459
3460 info->bus_type = MGSL_BUS_TYPE_PCI;
3461 info->irq_flags = IRQF_SHARED;
3462
3463 info->init_error = -1; /* assume error, set to 0 on successful init */
3464 }
3465
3466 return info;
3467 }
3468
3469 static void device_init(int adapter_num, struct pci_dev *pdev)
3470 {
3471 struct slgt_info *port_array[SLGT_MAX_PORTS];
3472 int i;
3473 int port_count = 1;
3474
3475 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3476 port_count = 2;
3477 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3478 port_count = 4;
3479
3480 /* allocate device instances for all ports */
3481 for (i=0; i < port_count; ++i) {
3482 port_array[i] = alloc_dev(adapter_num, i, pdev);
3483 if (port_array[i] == NULL) {
3484 for (--i; i >= 0; --i)
3485 kfree(port_array[i]);
3486 return;
3487 }
3488 }
3489
3490 /* give copy of port_array to all ports and add to device list */
3491 for (i=0; i < port_count; ++i) {
3492 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3493 add_device(port_array[i]);
3494 port_array[i]->port_count = port_count;
3495 spin_lock_init(&port_array[i]->lock);
3496 }
3497
3498 /* Allocate and claim adapter resources */
3499 if (!claim_resources(port_array[0])) {
3500
3501 alloc_dma_bufs(port_array[0]);
3502
3503 /* copy resource information from first port to others */
3504 for (i = 1; i < port_count; ++i) {
3505 port_array[i]->lock = port_array[0]->lock;
3506 port_array[i]->irq_level = port_array[0]->irq_level;
3507 port_array[i]->reg_addr = port_array[0]->reg_addr;
3508 alloc_dma_bufs(port_array[i]);
3509 }
3510
3511 if (request_irq(port_array[0]->irq_level,
3512 slgt_interrupt,
3513 port_array[0]->irq_flags,
3514 port_array[0]->device_name,
3515 port_array[0]) < 0) {
3516 DBGERR(("%s request_irq failed IRQ=%d\n",
3517 port_array[0]->device_name,
3518 port_array[0]->irq_level));
3519 } else {
3520 port_array[0]->irq_requested = true;
3521 adapter_test(port_array[0]);
3522 for (i=1 ; i < port_count ; i++) {
3523 port_array[i]->init_error = port_array[0]->init_error;
3524 port_array[i]->gpio_present = port_array[0]->gpio_present;
3525 }
3526 }
3527 }
3528
3529 for (i=0; i < port_count; ++i)
3530 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3531 }
3532
3533 static int __devinit init_one(struct pci_dev *dev,
3534 const struct pci_device_id *ent)
3535 {
3536 if (pci_enable_device(dev)) {
3537 printk("error enabling pci device %p\n", dev);
3538 return -EIO;
3539 }
3540 pci_set_master(dev);
3541 device_init(slgt_device_count, dev);
3542 return 0;
3543 }
3544
3545 static void __devexit remove_one(struct pci_dev *dev)
3546 {
3547 }
3548
3549 static const struct tty_operations ops = {
3550 .open = open,
3551 .close = close,
3552 .write = write,
3553 .put_char = put_char,
3554 .flush_chars = flush_chars,
3555 .write_room = write_room,
3556 .chars_in_buffer = chars_in_buffer,
3557 .flush_buffer = flush_buffer,
3558 .ioctl = ioctl,
3559 .compat_ioctl = slgt_compat_ioctl,
3560 .throttle = throttle,
3561 .unthrottle = unthrottle,
3562 .send_xchar = send_xchar,
3563 .break_ctl = set_break,
3564 .wait_until_sent = wait_until_sent,
3565 .read_proc = read_proc,
3566 .set_termios = set_termios,
3567 .stop = tx_hold,
3568 .start = tx_release,
3569 .hangup = hangup,
3570 .tiocmget = tiocmget,
3571 .tiocmset = tiocmset,
3572 };
3573
3574 static void slgt_cleanup(void)
3575 {
3576 int rc;
3577 struct slgt_info *info;
3578 struct slgt_info *tmp;
3579
3580 printk(KERN_INFO "unload %s\n", driver_name);
3581
3582 if (serial_driver) {
3583 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3584 tty_unregister_device(serial_driver, info->line);
3585 if ((rc = tty_unregister_driver(serial_driver)))
3586 DBGERR(("tty_unregister_driver error=%d\n", rc));
3587 put_tty_driver(serial_driver);
3588 }
3589
3590 /* reset devices */
3591 info = slgt_device_list;
3592 while(info) {
3593 reset_port(info);
3594 info = info->next_device;
3595 }
3596
3597 /* release devices */
3598 info = slgt_device_list;
3599 while(info) {
3600 #if SYNCLINK_GENERIC_HDLC
3601 hdlcdev_exit(info);
3602 #endif
3603 free_dma_bufs(info);
3604 free_tmp_rbuf(info);
3605 if (info->port_num == 0)
3606 release_resources(info);
3607 tmp = info;
3608 info = info->next_device;
3609 kfree(tmp);
3610 }
3611
3612 if (pci_registered)
3613 pci_unregister_driver(&pci_driver);
3614 }
3615
3616 /*
3617 * Driver initialization entry point.
3618 */
3619 static int __init slgt_init(void)
3620 {
3621 int rc;
3622
3623 printk(KERN_INFO "%s\n", driver_name);
3624
3625 serial_driver = alloc_tty_driver(MAX_DEVICES);
3626 if (!serial_driver) {
3627 printk("%s can't allocate tty driver\n", driver_name);
3628 return -ENOMEM;
3629 }
3630
3631 /* Initialize the tty_driver structure */
3632
3633 serial_driver->owner = THIS_MODULE;
3634 serial_driver->driver_name = tty_driver_name;
3635 serial_driver->name = tty_dev_prefix;
3636 serial_driver->major = ttymajor;
3637 serial_driver->minor_start = 64;
3638 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3639 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3640 serial_driver->init_termios = tty_std_termios;
3641 serial_driver->init_termios.c_cflag =
3642 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3643 serial_driver->init_termios.c_ispeed = 9600;
3644 serial_driver->init_termios.c_ospeed = 9600;
3645 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3646 tty_set_operations(serial_driver, &ops);
3647 if ((rc = tty_register_driver(serial_driver)) < 0) {
3648 DBGERR(("%s can't register serial driver\n", driver_name));
3649 put_tty_driver(serial_driver);
3650 serial_driver = NULL;
3651 goto error;
3652 }
3653
3654 printk(KERN_INFO "%s, tty major#%d\n",
3655 driver_name, serial_driver->major);
3656
3657 slgt_device_count = 0;
3658 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3659 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3660 goto error;
3661 }
3662 pci_registered = true;
3663
3664 if (!slgt_device_list)
3665 printk("%s no devices found\n",driver_name);
3666
3667 return 0;
3668
3669 error:
3670 slgt_cleanup();
3671 return rc;
3672 }
3673
3674 static void __exit slgt_exit(void)
3675 {
3676 slgt_cleanup();
3677 }
3678
3679 module_init(slgt_init);
3680 module_exit(slgt_exit);
3681
3682 /*
3683 * register access routines
3684 */
3685
3686 #define CALC_REGADDR() \
3687 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3688 if (addr >= 0x80) \
3689 reg_addr += (info->port_num) * 32;
3690
3691 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3692 {
3693 CALC_REGADDR();
3694 return readb((void __iomem *)reg_addr);
3695 }
3696
3697 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3698 {
3699 CALC_REGADDR();
3700 writeb(value, (void __iomem *)reg_addr);
3701 }
3702
3703 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3704 {
3705 CALC_REGADDR();
3706 return readw((void __iomem *)reg_addr);
3707 }
3708
3709 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3710 {
3711 CALC_REGADDR();
3712 writew(value, (void __iomem *)reg_addr);
3713 }
3714
3715 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3716 {
3717 CALC_REGADDR();
3718 return readl((void __iomem *)reg_addr);
3719 }
3720
3721 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3722 {
3723 CALC_REGADDR();
3724 writel(value, (void __iomem *)reg_addr);
3725 }
3726
3727 static void rdma_reset(struct slgt_info *info)
3728 {
3729 unsigned int i;
3730
3731 /* set reset bit */
3732 wr_reg32(info, RDCSR, BIT1);
3733
3734 /* wait for enable bit cleared */
3735 for(i=0 ; i < 1000 ; i++)
3736 if (!(rd_reg32(info, RDCSR) & BIT0))
3737 break;
3738 }
3739
3740 static void tdma_reset(struct slgt_info *info)
3741 {
3742 unsigned int i;
3743
3744 /* set reset bit */
3745 wr_reg32(info, TDCSR, BIT1);
3746
3747 /* wait for enable bit cleared */
3748 for(i=0 ; i < 1000 ; i++)
3749 if (!(rd_reg32(info, TDCSR) & BIT0))
3750 break;
3751 }
3752
3753 /*
3754 * enable internal loopback
3755 * TxCLK and RxCLK are generated from BRG
3756 * and TxD is looped back to RxD internally.
3757 */
3758 static void enable_loopback(struct slgt_info *info)
3759 {
3760 /* SCR (serial control) BIT2=looopback enable */
3761 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3762
3763 if (info->params.mode != MGSL_MODE_ASYNC) {
3764 /* CCR (clock control)
3765 * 07..05 tx clock source (010 = BRG)
3766 * 04..02 rx clock source (010 = BRG)
3767 * 01 auxclk enable (0 = disable)
3768 * 00 BRG enable (1 = enable)
3769 *
3770 * 0100 1001
3771 */
3772 wr_reg8(info, CCR, 0x49);
3773
3774 /* set speed if available, otherwise use default */
3775 if (info->params.clock_speed)
3776 set_rate(info, info->params.clock_speed);
3777 else
3778 set_rate(info, 3686400);
3779 }
3780 }
3781
3782 /*
3783 * set baud rate generator to specified rate
3784 */
3785 static void set_rate(struct slgt_info *info, u32 rate)
3786 {
3787 unsigned int div;
3788 static unsigned int osc = 14745600;
3789
3790 /* div = osc/rate - 1
3791 *
3792 * Round div up if osc/rate is not integer to
3793 * force to next slowest rate.
3794 */
3795
3796 if (rate) {
3797 div = osc/rate;
3798 if (!(osc % rate) && div)
3799 div--;
3800 wr_reg16(info, BDR, (unsigned short)div);
3801 }
3802 }
3803
3804 static void rx_stop(struct slgt_info *info)
3805 {
3806 unsigned short val;
3807
3808 /* disable and reset receiver */
3809 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3810 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3811 wr_reg16(info, RCR, val); /* clear reset bit */
3812
3813 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3814
3815 /* clear pending rx interrupts */
3816 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3817
3818 rdma_reset(info);
3819
3820 info->rx_enabled = false;
3821 info->rx_restart = false;
3822 }
3823
3824 static void rx_start(struct slgt_info *info)
3825 {
3826 unsigned short val;
3827
3828 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3829
3830 /* clear pending rx overrun IRQ */
3831 wr_reg16(info, SSR, IRQ_RXOVER);
3832
3833 /* reset and disable receiver */
3834 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3835 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3836 wr_reg16(info, RCR, val); /* clear reset bit */
3837
3838 rdma_reset(info);
3839 reset_rbufs(info);
3840
3841 /* set 1st descriptor address */
3842 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3843
3844 if (info->params.mode != MGSL_MODE_ASYNC) {
3845 /* enable rx DMA and DMA interrupt */
3846 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3847 } else {
3848 /* enable saving of rx status, rx DMA and DMA interrupt */
3849 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3850 }
3851
3852 slgt_irq_on(info, IRQ_RXOVER);
3853
3854 /* enable receiver */
3855 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3856
3857 info->rx_restart = false;
3858 info->rx_enabled = true;
3859 }
3860
3861 static void tx_start(struct slgt_info *info)
3862 {
3863 if (!info->tx_enabled) {
3864 wr_reg16(info, TCR,
3865 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3866 info->tx_enabled = true;
3867 }
3868
3869 if (info->tx_count) {
3870 info->drop_rts_on_tx_done = false;
3871
3872 if (info->params.mode != MGSL_MODE_ASYNC) {
3873 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3874 get_signals(info);
3875 if (!(info->signals & SerialSignal_RTS)) {
3876 info->signals |= SerialSignal_RTS;
3877 set_signals(info);
3878 info->drop_rts_on_tx_done = true;
3879 }
3880 }
3881
3882 slgt_irq_off(info, IRQ_TXDATA);
3883 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3884 /* clear tx idle and underrun status bits */
3885 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3886 if (info->params.mode == MGSL_MODE_HDLC)
3887 mod_timer(&info->tx_timer, jiffies +
3888 msecs_to_jiffies(5000));
3889 } else {
3890 slgt_irq_off(info, IRQ_TXDATA);
3891 slgt_irq_on(info, IRQ_TXIDLE);
3892 /* clear tx idle status bit */
3893 wr_reg16(info, SSR, IRQ_TXIDLE);
3894 }
3895 tdma_start(info);
3896 info->tx_active = true;
3897 }
3898 }
3899
3900 /*
3901 * start transmit DMA if inactive and there are unsent buffers
3902 */
3903 static void tdma_start(struct slgt_info *info)
3904 {
3905 unsigned int i;
3906
3907 if (rd_reg32(info, TDCSR) & BIT0)
3908 return;
3909
3910 /* transmit DMA inactive, check for unsent buffers */
3911 i = info->tbuf_start;
3912 while (!desc_count(info->tbufs[i])) {
3913 if (++i == info->tbuf_count)
3914 i = 0;
3915 if (i == info->tbuf_current)
3916 return;
3917 }
3918 info->tbuf_start = i;
3919
3920 /* there are unsent buffers, start transmit DMA */
3921
3922 /* reset needed if previous error condition */
3923 tdma_reset(info);
3924
3925 /* set 1st descriptor address */
3926 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3927 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3928 }
3929
3930 static void tx_stop(struct slgt_info *info)
3931 {
3932 unsigned short val;
3933
3934 del_timer(&info->tx_timer);
3935
3936 tdma_reset(info);
3937
3938 /* reset and disable transmitter */
3939 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3940 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3941
3942 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3943
3944 /* clear tx idle and underrun status bit */
3945 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3946
3947 reset_tbufs(info);
3948
3949 info->tx_enabled = false;
3950 info->tx_active = false;
3951 }
3952
3953 static void reset_port(struct slgt_info *info)
3954 {
3955 if (!info->reg_addr)
3956 return;
3957
3958 tx_stop(info);
3959 rx_stop(info);
3960
3961 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3962 set_signals(info);
3963
3964 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3965 }
3966
3967 static void reset_adapter(struct slgt_info *info)
3968 {
3969 int i;
3970 for (i=0; i < info->port_count; ++i) {
3971 if (info->port_array[i])
3972 reset_port(info->port_array[i]);
3973 }
3974 }
3975
3976 static void async_mode(struct slgt_info *info)
3977 {
3978 unsigned short val;
3979
3980 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3981 tx_stop(info);
3982 rx_stop(info);
3983
3984 /* TCR (tx control)
3985 *
3986 * 15..13 mode, 010=async
3987 * 12..10 encoding, 000=NRZ
3988 * 09 parity enable
3989 * 08 1=odd parity, 0=even parity
3990 * 07 1=RTS driver control
3991 * 06 1=break enable
3992 * 05..04 character length
3993 * 00=5 bits
3994 * 01=6 bits
3995 * 10=7 bits
3996 * 11=8 bits
3997 * 03 0=1 stop bit, 1=2 stop bits
3998 * 02 reset
3999 * 01 enable
4000 * 00 auto-CTS enable
4001 */
4002 val = 0x4000;
4003
4004 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4005 val |= BIT7;
4006
4007 if (info->params.parity != ASYNC_PARITY_NONE) {
4008 val |= BIT9;
4009 if (info->params.parity == ASYNC_PARITY_ODD)
4010 val |= BIT8;
4011 }
4012
4013 switch (info->params.data_bits)
4014 {
4015 case 6: val |= BIT4; break;
4016 case 7: val |= BIT5; break;
4017 case 8: val |= BIT5 + BIT4; break;
4018 }
4019
4020 if (info->params.stop_bits != 1)
4021 val |= BIT3;
4022
4023 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4024 val |= BIT0;
4025
4026 wr_reg16(info, TCR, val);
4027
4028 /* RCR (rx control)
4029 *
4030 * 15..13 mode, 010=async
4031 * 12..10 encoding, 000=NRZ
4032 * 09 parity enable
4033 * 08 1=odd parity, 0=even parity
4034 * 07..06 reserved, must be 0
4035 * 05..04 character length
4036 * 00=5 bits
4037 * 01=6 bits
4038 * 10=7 bits
4039 * 11=8 bits
4040 * 03 reserved, must be zero
4041 * 02 reset
4042 * 01 enable
4043 * 00 auto-DCD enable
4044 */
4045 val = 0x4000;
4046
4047 if (info->params.parity != ASYNC_PARITY_NONE) {
4048 val |= BIT9;
4049 if (info->params.parity == ASYNC_PARITY_ODD)
4050 val |= BIT8;
4051 }
4052
4053 switch (info->params.data_bits)
4054 {
4055 case 6: val |= BIT4; break;
4056 case 7: val |= BIT5; break;
4057 case 8: val |= BIT5 + BIT4; break;
4058 }
4059
4060 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4061 val |= BIT0;
4062
4063 wr_reg16(info, RCR, val);
4064
4065 /* CCR (clock control)
4066 *
4067 * 07..05 011 = tx clock source is BRG/16
4068 * 04..02 010 = rx clock source is BRG
4069 * 01 0 = auxclk disabled
4070 * 00 1 = BRG enabled
4071 *
4072 * 0110 1001
4073 */
4074 wr_reg8(info, CCR, 0x69);
4075
4076 msc_set_vcr(info);
4077
4078 /* SCR (serial control)
4079 *
4080 * 15 1=tx req on FIFO half empty
4081 * 14 1=rx req on FIFO half full
4082 * 13 tx data IRQ enable
4083 * 12 tx idle IRQ enable
4084 * 11 rx break on IRQ enable
4085 * 10 rx data IRQ enable
4086 * 09 rx break off IRQ enable
4087 * 08 overrun IRQ enable
4088 * 07 DSR IRQ enable
4089 * 06 CTS IRQ enable
4090 * 05 DCD IRQ enable
4091 * 04 RI IRQ enable
4092 * 03 reserved, must be zero
4093 * 02 1=txd->rxd internal loopback enable
4094 * 01 reserved, must be zero
4095 * 00 1=master IRQ enable
4096 */
4097 val = BIT15 + BIT14 + BIT0;
4098 wr_reg16(info, SCR, val);
4099
4100 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4101
4102 set_rate(info, info->params.data_rate * 16);
4103
4104 if (info->params.loopback)
4105 enable_loopback(info);
4106 }
4107
4108 static void sync_mode(struct slgt_info *info)
4109 {
4110 unsigned short val;
4111
4112 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4113 tx_stop(info);
4114 rx_stop(info);
4115
4116 /* TCR (tx control)
4117 *
4118 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4119 * 12..10 encoding
4120 * 09 CRC enable
4121 * 08 CRC32
4122 * 07 1=RTS driver control
4123 * 06 preamble enable
4124 * 05..04 preamble length
4125 * 03 share open/close flag
4126 * 02 reset
4127 * 01 enable
4128 * 00 auto-CTS enable
4129 */
4130 val = BIT2;
4131
4132 switch(info->params.mode) {
4133 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4134 case MGSL_MODE_BISYNC: val |= BIT15; break;
4135 case MGSL_MODE_RAW: val |= BIT13; break;
4136 }
4137 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4138 val |= BIT7;
4139
4140 switch(info->params.encoding)
4141 {
4142 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4143 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4144 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4145 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4146 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4147 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4148 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4149 }
4150
4151 switch (info->params.crc_type & HDLC_CRC_MASK)
4152 {
4153 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4154 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4155 }
4156
4157 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4158 val |= BIT6;
4159
4160 switch (info->params.preamble_length)
4161 {
4162 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4163 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4164 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4165 }
4166
4167 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4168 val |= BIT0;
4169
4170 wr_reg16(info, TCR, val);
4171
4172 /* TPR (transmit preamble) */
4173
4174 switch (info->params.preamble)
4175 {
4176 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4177 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4178 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4179 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4180 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4181 default: val = 0x7e; break;
4182 }
4183 wr_reg8(info, TPR, (unsigned char)val);
4184
4185 /* RCR (rx control)
4186 *
4187 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4188 * 12..10 encoding
4189 * 09 CRC enable
4190 * 08 CRC32
4191 * 07..03 reserved, must be 0
4192 * 02 reset
4193 * 01 enable
4194 * 00 auto-DCD enable
4195 */
4196 val = 0;
4197
4198 switch(info->params.mode) {
4199 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4200 case MGSL_MODE_BISYNC: val |= BIT15; break;
4201 case MGSL_MODE_RAW: val |= BIT13; break;
4202 }
4203
4204 switch(info->params.encoding)
4205 {
4206 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4207 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4208 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4209 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4210 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4211 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4212 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4213 }
4214
4215 switch (info->params.crc_type & HDLC_CRC_MASK)
4216 {
4217 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4218 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4219 }
4220
4221 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4222 val |= BIT0;
4223
4224 wr_reg16(info, RCR, val);
4225
4226 /* CCR (clock control)
4227 *
4228 * 07..05 tx clock source
4229 * 04..02 rx clock source
4230 * 01 auxclk enable
4231 * 00 BRG enable
4232 */
4233 val = 0;
4234
4235 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4236 {
4237 // when RxC source is DPLL, BRG generates 16X DPLL
4238 // reference clock, so take TxC from BRG/16 to get
4239 // transmit clock at actual data rate
4240 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4241 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4242 else
4243 val |= BIT6; /* 010, txclk = BRG */
4244 }
4245 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4246 val |= BIT7; /* 100, txclk = DPLL Input */
4247 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4248 val |= BIT5; /* 001, txclk = RXC Input */
4249
4250 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4251 val |= BIT3; /* 010, rxclk = BRG */
4252 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4253 val |= BIT4; /* 100, rxclk = DPLL */
4254 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4255 val |= BIT2; /* 001, rxclk = TXC Input */
4256
4257 if (info->params.clock_speed)
4258 val |= BIT1 + BIT0;
4259
4260 wr_reg8(info, CCR, (unsigned char)val);
4261
4262 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4263 {
4264 // program DPLL mode
4265 switch(info->params.encoding)
4266 {
4267 case HDLC_ENCODING_BIPHASE_MARK:
4268 case HDLC_ENCODING_BIPHASE_SPACE:
4269 val = BIT7; break;
4270 case HDLC_ENCODING_BIPHASE_LEVEL:
4271 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4272 val = BIT7 + BIT6; break;
4273 default: val = BIT6; // NRZ encodings
4274 }
4275 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4276
4277 // DPLL requires a 16X reference clock from BRG
4278 set_rate(info, info->params.clock_speed * 16);
4279 }
4280 else
4281 set_rate(info, info->params.clock_speed);
4282
4283 tx_set_idle(info);
4284
4285 msc_set_vcr(info);
4286
4287 /* SCR (serial control)
4288 *
4289 * 15 1=tx req on FIFO half empty
4290 * 14 1=rx req on FIFO half full
4291 * 13 tx data IRQ enable
4292 * 12 tx idle IRQ enable
4293 * 11 underrun IRQ enable
4294 * 10 rx data IRQ enable
4295 * 09 rx idle IRQ enable
4296 * 08 overrun IRQ enable
4297 * 07 DSR IRQ enable
4298 * 06 CTS IRQ enable
4299 * 05 DCD IRQ enable
4300 * 04 RI IRQ enable
4301 * 03 reserved, must be zero
4302 * 02 1=txd->rxd internal loopback enable
4303 * 01 reserved, must be zero
4304 * 00 1=master IRQ enable
4305 */
4306 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4307
4308 if (info->params.loopback)
4309 enable_loopback(info);
4310 }
4311
4312 /*
4313 * set transmit idle mode
4314 */
4315 static void tx_set_idle(struct slgt_info *info)
4316 {
4317 unsigned char val;
4318 unsigned short tcr;
4319
4320 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4321 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4322 */
4323 tcr = rd_reg16(info, TCR);
4324 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4325 /* disable preamble, set idle size to 16 bits */
4326 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4327 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4328 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4329 } else if (!(tcr & BIT6)) {
4330 /* preamble is disabled, set idle size to 8 bits */
4331 tcr &= ~(BIT5 + BIT4);
4332 }
4333 wr_reg16(info, TCR, tcr);
4334
4335 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4336 /* LSB of custom tx idle specified in tx idle register */
4337 val = (unsigned char)(info->idle_mode & 0xff);
4338 } else {
4339 /* standard 8 bit idle patterns */
4340 switch(info->idle_mode)
4341 {
4342 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4343 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4344 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4345 case HDLC_TXIDLE_ZEROS:
4346 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4347 default: val = 0xff;
4348 }
4349 }
4350
4351 wr_reg8(info, TIR, val);
4352 }
4353
4354 /*
4355 * get state of V24 status (input) signals
4356 */
4357 static void get_signals(struct slgt_info *info)
4358 {
4359 unsigned short status = rd_reg16(info, SSR);
4360
4361 /* clear all serial signals except DTR and RTS */
4362 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4363
4364 if (status & BIT3)
4365 info->signals |= SerialSignal_DSR;
4366 if (status & BIT2)
4367 info->signals |= SerialSignal_CTS;
4368 if (status & BIT1)
4369 info->signals |= SerialSignal_DCD;
4370 if (status & BIT0)
4371 info->signals |= SerialSignal_RI;
4372 }
4373
4374 /*
4375 * set V.24 Control Register based on current configuration
4376 */
4377 static void msc_set_vcr(struct slgt_info *info)
4378 {
4379 unsigned char val = 0;
4380
4381 /* VCR (V.24 control)
4382 *
4383 * 07..04 serial IF select
4384 * 03 DTR
4385 * 02 RTS
4386 * 01 LL
4387 * 00 RL
4388 */
4389
4390 switch(info->if_mode & MGSL_INTERFACE_MASK)
4391 {
4392 case MGSL_INTERFACE_RS232:
4393 val |= BIT5; /* 0010 */
4394 break;
4395 case MGSL_INTERFACE_V35:
4396 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4397 break;
4398 case MGSL_INTERFACE_RS422:
4399 val |= BIT6; /* 0100 */
4400 break;
4401 }
4402
4403 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4404 val |= BIT4;
4405 if (info->signals & SerialSignal_DTR)
4406 val |= BIT3;
4407 if (info->signals & SerialSignal_RTS)
4408 val |= BIT2;
4409 if (info->if_mode & MGSL_INTERFACE_LL)
4410 val |= BIT1;
4411 if (info->if_mode & MGSL_INTERFACE_RL)
4412 val |= BIT0;
4413 wr_reg8(info, VCR, val);
4414 }
4415
4416 /*
4417 * set state of V24 control (output) signals
4418 */
4419 static void set_signals(struct slgt_info *info)
4420 {
4421 unsigned char val = rd_reg8(info, VCR);
4422 if (info->signals & SerialSignal_DTR)
4423 val |= BIT3;
4424 else
4425 val &= ~BIT3;
4426 if (info->signals & SerialSignal_RTS)
4427 val |= BIT2;
4428 else
4429 val &= ~BIT2;
4430 wr_reg8(info, VCR, val);
4431 }
4432
4433 /*
4434 * free range of receive DMA buffers (i to last)
4435 */
4436 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4437 {
4438 int done = 0;
4439
4440 while(!done) {
4441 /* reset current buffer for reuse */
4442 info->rbufs[i].status = 0;
4443 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4444 if (i == last)
4445 done = 1;
4446 if (++i == info->rbuf_count)
4447 i = 0;
4448 }
4449 info->rbuf_current = i;
4450 }
4451
4452 /*
4453 * mark all receive DMA buffers as free
4454 */
4455 static void reset_rbufs(struct slgt_info *info)
4456 {
4457 free_rbufs(info, 0, info->rbuf_count - 1);
4458 }
4459
4460 /*
4461 * pass receive HDLC frame to upper layer
4462 *
4463 * return true if frame available, otherwise false
4464 */
4465 static bool rx_get_frame(struct slgt_info *info)
4466 {
4467 unsigned int start, end;
4468 unsigned short status;
4469 unsigned int framesize = 0;
4470 unsigned long flags;
4471 struct tty_struct *tty = info->port.tty;
4472 unsigned char addr_field = 0xff;
4473 unsigned int crc_size = 0;
4474
4475 switch (info->params.crc_type & HDLC_CRC_MASK) {
4476 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4477 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4478 }
4479
4480 check_again:
4481
4482 framesize = 0;
4483 addr_field = 0xff;
4484 start = end = info->rbuf_current;
4485
4486 for (;;) {
4487 if (!desc_complete(info->rbufs[end]))
4488 goto cleanup;
4489
4490 if (framesize == 0 && info->params.addr_filter != 0xff)
4491 addr_field = info->rbufs[end].buf[0];
4492
4493 framesize += desc_count(info->rbufs[end]);
4494
4495 if (desc_eof(info->rbufs[end]))
4496 break;
4497
4498 if (++end == info->rbuf_count)
4499 end = 0;
4500
4501 if (end == info->rbuf_current) {
4502 if (info->rx_enabled){
4503 spin_lock_irqsave(&info->lock,flags);
4504 rx_start(info);
4505 spin_unlock_irqrestore(&info->lock,flags);
4506 }
4507 goto cleanup;
4508 }
4509 }
4510
4511 /* status
4512 *
4513 * 15 buffer complete
4514 * 14..06 reserved
4515 * 05..04 residue
4516 * 02 eof (end of frame)
4517 * 01 CRC error
4518 * 00 abort
4519 */
4520 status = desc_status(info->rbufs[end]);
4521
4522 /* ignore CRC bit if not using CRC (bit is undefined) */
4523 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4524 status &= ~BIT1;
4525
4526 if (framesize == 0 ||
4527 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4528 free_rbufs(info, start, end);
4529 goto check_again;
4530 }
4531
4532 if (framesize < (2 + crc_size) || status & BIT0) {
4533 info->icount.rxshort++;
4534 framesize = 0;
4535 } else if (status & BIT1) {
4536 info->icount.rxcrc++;
4537 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4538 framesize = 0;
4539 }
4540
4541 #if SYNCLINK_GENERIC_HDLC
4542 if (framesize == 0) {
4543 info->netdev->stats.rx_errors++;
4544 info->netdev->stats.rx_frame_errors++;
4545 }
4546 #endif
4547
4548 DBGBH(("%s rx frame status=%04X size=%d\n",
4549 info->device_name, status, framesize));
4550 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4551
4552 if (framesize) {
4553 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4554 framesize -= crc_size;
4555 crc_size = 0;
4556 }
4557
4558 if (framesize > info->max_frame_size + crc_size)
4559 info->icount.rxlong++;
4560 else {
4561 /* copy dma buffer(s) to contiguous temp buffer */
4562 int copy_count = framesize;
4563 int i = start;
4564 unsigned char *p = info->tmp_rbuf;
4565 info->tmp_rbuf_count = framesize;
4566
4567 info->icount.rxok++;
4568
4569 while(copy_count) {
4570 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4571 memcpy(p, info->rbufs[i].buf, partial_count);
4572 p += partial_count;
4573 copy_count -= partial_count;
4574 if (++i == info->rbuf_count)
4575 i = 0;
4576 }
4577
4578 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4579 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4580 framesize++;
4581 }
4582
4583 #if SYNCLINK_GENERIC_HDLC
4584 if (info->netcount)
4585 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4586 else
4587 #endif
4588 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4589 }
4590 }
4591 free_rbufs(info, start, end);
4592 return true;
4593
4594 cleanup:
4595 return false;
4596 }
4597
4598 /*
4599 * pass receive buffer (RAW synchronous mode) to tty layer
4600 * return true if buffer available, otherwise false
4601 */
4602 static bool rx_get_buf(struct slgt_info *info)
4603 {
4604 unsigned int i = info->rbuf_current;
4605 unsigned int count;
4606
4607 if (!desc_complete(info->rbufs[i]))
4608 return false;
4609 count = desc_count(info->rbufs[i]);
4610 switch(info->params.mode) {
4611 case MGSL_MODE_MONOSYNC:
4612 case MGSL_MODE_BISYNC:
4613 /* ignore residue in byte synchronous modes */
4614 if (desc_residue(info->rbufs[i]))
4615 count--;
4616 break;
4617 }
4618 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4619 DBGINFO(("rx_get_buf size=%d\n", count));
4620 if (count)
4621 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4622 info->flag_buf, count);
4623 free_rbufs(info, i, i);
4624 return true;
4625 }
4626
4627 static void reset_tbufs(struct slgt_info *info)
4628 {
4629 unsigned int i;
4630 info->tbuf_current = 0;
4631 for (i=0 ; i < info->tbuf_count ; i++) {
4632 info->tbufs[i].status = 0;
4633 info->tbufs[i].count = 0;
4634 }
4635 }
4636
4637 /*
4638 * return number of free transmit DMA buffers
4639 */
4640 static unsigned int free_tbuf_count(struct slgt_info *info)
4641 {
4642 unsigned int count = 0;
4643 unsigned int i = info->tbuf_current;
4644
4645 do
4646 {
4647 if (desc_count(info->tbufs[i]))
4648 break; /* buffer in use */
4649 ++count;
4650 if (++i == info->tbuf_count)
4651 i=0;
4652 } while (i != info->tbuf_current);
4653
4654 /* if tx DMA active, last zero count buffer is in use */
4655 if (count && (rd_reg32(info, TDCSR) & BIT0))
4656 --count;
4657
4658 return count;
4659 }
4660
4661 /*
4662 * return number of bytes in unsent transmit DMA buffers
4663 * and the serial controller tx FIFO
4664 */
4665 static unsigned int tbuf_bytes(struct slgt_info *info)
4666 {
4667 unsigned int total_count = 0;
4668 unsigned int i = info->tbuf_current;
4669 unsigned int reg_value;
4670 unsigned int count;
4671 unsigned int active_buf_count = 0;
4672
4673 /*
4674 * Add descriptor counts for all tx DMA buffers.
4675 * If count is zero (cleared by DMA controller after read),
4676 * the buffer is complete or is actively being read from.
4677 *
4678 * Record buf_count of last buffer with zero count starting
4679 * from current ring position. buf_count is mirror
4680 * copy of count and is not cleared by serial controller.
4681 * If DMA controller is active, that buffer is actively
4682 * being read so add to total.
4683 */
4684 do {
4685 count = desc_count(info->tbufs[i]);
4686 if (count)
4687 total_count += count;
4688 else if (!total_count)
4689 active_buf_count = info->tbufs[i].buf_count;
4690 if (++i == info->tbuf_count)
4691 i = 0;
4692 } while (i != info->tbuf_current);
4693
4694 /* read tx DMA status register */
4695 reg_value = rd_reg32(info, TDCSR);
4696
4697 /* if tx DMA active, last zero count buffer is in use */
4698 if (reg_value & BIT0)
4699 total_count += active_buf_count;
4700
4701 /* add tx FIFO count = reg_value[15..8] */
4702 total_count += (reg_value >> 8) & 0xff;
4703
4704 /* if transmitter active add one byte for shift register */
4705 if (info->tx_active)
4706 total_count++;
4707
4708 return total_count;
4709 }
4710
4711 /*
4712 * load transmit DMA buffer(s) with data
4713 */
4714 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4715 {
4716 unsigned short count;
4717 unsigned int i;
4718 struct slgt_desc *d;
4719
4720 if (size == 0)
4721 return;
4722
4723 DBGDATA(info, buf, size, "tx");
4724
4725 info->tbuf_start = i = info->tbuf_current;
4726
4727 while (size) {
4728 d = &info->tbufs[i];
4729 if (++i == info->tbuf_count)
4730 i = 0;
4731
4732 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4733 memcpy(d->buf, buf, count);
4734
4735 size -= count;
4736 buf += count;
4737
4738 /*
4739 * set EOF bit for last buffer of HDLC frame or
4740 * for every buffer in raw mode
4741 */
4742 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4743 info->params.mode == MGSL_MODE_RAW)
4744 set_desc_eof(*d, 1);
4745 else
4746 set_desc_eof(*d, 0);
4747
4748 set_desc_count(*d, count);
4749 d->buf_count = count;
4750 }
4751
4752 info->tbuf_current = i;
4753 }
4754
4755 static int register_test(struct slgt_info *info)
4756 {
4757 static unsigned short patterns[] =
4758 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4759 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4760 unsigned int i;
4761 int rc = 0;
4762
4763 for (i=0 ; i < count ; i++) {
4764 wr_reg16(info, TIR, patterns[i]);
4765 wr_reg16(info, BDR, patterns[(i+1)%count]);
4766 if ((rd_reg16(info, TIR) != patterns[i]) ||
4767 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4768 rc = -ENODEV;
4769 break;
4770 }
4771 }
4772 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4773 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4774 return rc;
4775 }
4776
4777 static int irq_test(struct slgt_info *info)
4778 {
4779 unsigned long timeout;
4780 unsigned long flags;
4781 struct tty_struct *oldtty = info->port.tty;
4782 u32 speed = info->params.data_rate;
4783
4784 info->params.data_rate = 921600;
4785 info->port.tty = NULL;
4786
4787 spin_lock_irqsave(&info->lock, flags);
4788 async_mode(info);
4789 slgt_irq_on(info, IRQ_TXIDLE);
4790
4791 /* enable transmitter */
4792 wr_reg16(info, TCR,
4793 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4794
4795 /* write one byte and wait for tx idle */
4796 wr_reg16(info, TDR, 0);
4797
4798 /* assume failure */
4799 info->init_error = DiagStatus_IrqFailure;
4800 info->irq_occurred = false;
4801
4802 spin_unlock_irqrestore(&info->lock, flags);
4803
4804 timeout=100;
4805 while(timeout-- && !info->irq_occurred)
4806 msleep_interruptible(10);
4807
4808 spin_lock_irqsave(&info->lock,flags);
4809 reset_port(info);
4810 spin_unlock_irqrestore(&info->lock,flags);
4811
4812 info->params.data_rate = speed;
4813 info->port.tty = oldtty;
4814
4815 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4816 return info->irq_occurred ? 0 : -ENODEV;
4817 }
4818
4819 static int loopback_test_rx(struct slgt_info *info)
4820 {
4821 unsigned char *src, *dest;
4822 int count;
4823
4824 if (desc_complete(info->rbufs[0])) {
4825 count = desc_count(info->rbufs[0]);
4826 src = info->rbufs[0].buf;
4827 dest = info->tmp_rbuf;
4828
4829 for( ; count ; count-=2, src+=2) {
4830 /* src=data byte (src+1)=status byte */
4831 if (!(*(src+1) & (BIT9 + BIT8))) {
4832 *dest = *src;
4833 dest++;
4834 info->tmp_rbuf_count++;
4835 }
4836 }
4837 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4838 return 1;
4839 }
4840 return 0;
4841 }
4842
4843 static int loopback_test(struct slgt_info *info)
4844 {
4845 #define TESTFRAMESIZE 20
4846
4847 unsigned long timeout;
4848 u16 count = TESTFRAMESIZE;
4849 unsigned char buf[TESTFRAMESIZE];
4850 int rc = -ENODEV;
4851 unsigned long flags;
4852
4853 struct tty_struct *oldtty = info->port.tty;
4854 MGSL_PARAMS params;
4855
4856 memcpy(&params, &info->params, sizeof(params));
4857
4858 info->params.mode = MGSL_MODE_ASYNC;
4859 info->params.data_rate = 921600;
4860 info->params.loopback = 1;
4861 info->port.tty = NULL;
4862
4863 /* build and send transmit frame */
4864 for (count = 0; count < TESTFRAMESIZE; ++count)
4865 buf[count] = (unsigned char)count;
4866
4867 info->tmp_rbuf_count = 0;
4868 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4869
4870 /* program hardware for HDLC and enabled receiver */
4871 spin_lock_irqsave(&info->lock,flags);
4872 async_mode(info);
4873 rx_start(info);
4874 info->tx_count = count;
4875 tx_load(info, buf, count);
4876 tx_start(info);
4877 spin_unlock_irqrestore(&info->lock, flags);
4878
4879 /* wait for receive complete */
4880 for (timeout = 100; timeout; --timeout) {
4881 msleep_interruptible(10);
4882 if (loopback_test_rx(info)) {
4883 rc = 0;
4884 break;
4885 }
4886 }
4887
4888 /* verify received frame length and contents */
4889 if (!rc && (info->tmp_rbuf_count != count ||
4890 memcmp(buf, info->tmp_rbuf, count))) {
4891 rc = -ENODEV;
4892 }
4893
4894 spin_lock_irqsave(&info->lock,flags);
4895 reset_adapter(info);
4896 spin_unlock_irqrestore(&info->lock,flags);
4897
4898 memcpy(&info->params, &params, sizeof(info->params));
4899 info->port.tty = oldtty;
4900
4901 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4902 return rc;
4903 }
4904
4905 static int adapter_test(struct slgt_info *info)
4906 {
4907 DBGINFO(("testing %s\n", info->device_name));
4908 if (register_test(info) < 0) {
4909 printk("register test failure %s addr=%08X\n",
4910 info->device_name, info->phys_reg_addr);
4911 } else if (irq_test(info) < 0) {
4912 printk("IRQ test failure %s IRQ=%d\n",
4913 info->device_name, info->irq_level);
4914 } else if (loopback_test(info) < 0) {
4915 printk("loopback test failure %s\n", info->device_name);
4916 }
4917 return info->init_error;
4918 }
4919
4920 /*
4921 * transmit timeout handler
4922 */
4923 static void tx_timeout(unsigned long context)
4924 {
4925 struct slgt_info *info = (struct slgt_info*)context;
4926 unsigned long flags;
4927
4928 DBGINFO(("%s tx_timeout\n", info->device_name));
4929 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4930 info->icount.txtimeout++;
4931 }
4932 spin_lock_irqsave(&info->lock,flags);
4933 info->tx_active = false;
4934 info->tx_count = 0;
4935 spin_unlock_irqrestore(&info->lock,flags);
4936
4937 #if SYNCLINK_GENERIC_HDLC
4938 if (info->netcount)
4939 hdlcdev_tx_done(info);
4940 else
4941 #endif
4942 bh_transmit(info);
4943 }
4944
4945 /*
4946 * receive buffer polling timer
4947 */
4948 static void rx_timeout(unsigned long context)
4949 {
4950 struct slgt_info *info = (struct slgt_info*)context;
4951 unsigned long flags;
4952
4953 DBGINFO(("%s rx_timeout\n", info->device_name));
4954 spin_lock_irqsave(&info->lock, flags);
4955 info->pending_bh |= BH_RECEIVE;
4956 spin_unlock_irqrestore(&info->lock, flags);
4957 bh_handler(&info->task);
4958 }
4959
Linux with added FPC-III support