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iwlwifi: fix FAT channel config for 5000 series
[linux/fpc-iii.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
blobd49e48b9b037b7b74f5368639900d7ed24ea922d
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
40
41 #include "iwl-fh.h"
42 #include "iwl-3945-fh.h"
43 #include "iwl-commands.h"
44 #include "iwl-sta.h"
45 #include "iwl-3945.h"
46 #include "iwl-eeprom.h"
47 #include "iwl-helpers.h"
48 #include "iwl-core.h"
49 #include "iwl-agn-rs.h"
50
51 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
52 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX, \
60 IWL_RATE_##r##M_INDEX_TABLE, \
61 IWL_RATE_##ip##M_INDEX_TABLE }
62
63 /*
64 * Parameter order:
65 * rate, prev rate, next rate, prev tgg rate, next tgg rate
66 *
67 * If there isn't a valid next or previous rate then INV is used which
68 * maps to IWL_RATE_INVALID
69 *
70 */
71 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
72 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
73 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
74 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
75 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
76 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
77 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
78 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
79 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
80 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
81 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
82 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
83 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
84 };
85
86 /* 1 = enable the iwl3945_disable_events() function */
87 #define IWL_EVT_DISABLE (0)
88 #define IWL_EVT_DISABLE_SIZE (1532/32)
89
90 /**
91 * iwl3945_disable_events - Disable selected events in uCode event log
92 *
93 * Disable an event by writing "1"s into "disable"
94 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
95 * Default values of 0 enable uCode events to be logged.
96 * Use for only special debugging. This function is just a placeholder as-is,
97 * you'll need to provide the special bits! ...
98 * ... and set IWL_EVT_DISABLE to 1. */
99 void iwl3945_disable_events(struct iwl_priv *priv)
100 {
101 int ret;
102 int i;
103 u32 base; /* SRAM address of event log header */
104 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
105 u32 array_size; /* # of u32 entries in array */
106 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
107 0x00000000, /* 31 - 0 Event id numbers */
108 0x00000000, /* 63 - 32 */
109 0x00000000, /* 95 - 64 */
110 0x00000000, /* 127 - 96 */
111 0x00000000, /* 159 - 128 */
112 0x00000000, /* 191 - 160 */
113 0x00000000, /* 223 - 192 */
114 0x00000000, /* 255 - 224 */
115 0x00000000, /* 287 - 256 */
116 0x00000000, /* 319 - 288 */
117 0x00000000, /* 351 - 320 */
118 0x00000000, /* 383 - 352 */
119 0x00000000, /* 415 - 384 */
120 0x00000000, /* 447 - 416 */
121 0x00000000, /* 479 - 448 */
122 0x00000000, /* 511 - 480 */
123 0x00000000, /* 543 - 512 */
124 0x00000000, /* 575 - 544 */
125 0x00000000, /* 607 - 576 */
126 0x00000000, /* 639 - 608 */
127 0x00000000, /* 671 - 640 */
128 0x00000000, /* 703 - 672 */
129 0x00000000, /* 735 - 704 */
130 0x00000000, /* 767 - 736 */
131 0x00000000, /* 799 - 768 */
132 0x00000000, /* 831 - 800 */
133 0x00000000, /* 863 - 832 */
134 0x00000000, /* 895 - 864 */
135 0x00000000, /* 927 - 896 */
136 0x00000000, /* 959 - 928 */
137 0x00000000, /* 991 - 960 */
138 0x00000000, /* 1023 - 992 */
139 0x00000000, /* 1055 - 1024 */
140 0x00000000, /* 1087 - 1056 */
141 0x00000000, /* 1119 - 1088 */
142 0x00000000, /* 1151 - 1120 */
143 0x00000000, /* 1183 - 1152 */
144 0x00000000, /* 1215 - 1184 */
145 0x00000000, /* 1247 - 1216 */
146 0x00000000, /* 1279 - 1248 */
147 0x00000000, /* 1311 - 1280 */
148 0x00000000, /* 1343 - 1312 */
149 0x00000000, /* 1375 - 1344 */
150 0x00000000, /* 1407 - 1376 */
151 0x00000000, /* 1439 - 1408 */
152 0x00000000, /* 1471 - 1440 */
153 0x00000000, /* 1503 - 1472 */
154 };
155
156 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
157 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
158 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
159 return;
160 }
161
162 ret = iwl_grab_nic_access(priv);
163 if (ret) {
164 IWL_WARN(priv, "Can not read from adapter at this time.\n");
165 return;
166 }
167
168 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
169 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
170 iwl_release_nic_access(priv);
171
172 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
173 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
174 disable_ptr);
175 ret = iwl_grab_nic_access(priv);
176 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
177 iwl_write_targ_mem(priv,
178 disable_ptr + (i * sizeof(u32)),
179 evt_disable[i]);
180
181 iwl_release_nic_access(priv);
182 } else {
183 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
184 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
185 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
186 disable_ptr, array_size);
187 }
188
189 }
190
191 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
192 {
193 int idx;
194
195 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
196 if (iwl3945_rates[idx].plcp == plcp)
197 return idx;
198 return -1;
199 }
200
201 #ifdef CONFIG_IWLWIFI_DEBUG
202 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
203
204 static const char *iwl3945_get_tx_fail_reason(u32 status)
205 {
206 switch (status & TX_STATUS_MSK) {
207 case TX_STATUS_SUCCESS:
208 return "SUCCESS";
209 TX_STATUS_ENTRY(SHORT_LIMIT);
210 TX_STATUS_ENTRY(LONG_LIMIT);
211 TX_STATUS_ENTRY(FIFO_UNDERRUN);
212 TX_STATUS_ENTRY(MGMNT_ABORT);
213 TX_STATUS_ENTRY(NEXT_FRAG);
214 TX_STATUS_ENTRY(LIFE_EXPIRE);
215 TX_STATUS_ENTRY(DEST_PS);
216 TX_STATUS_ENTRY(ABORTED);
217 TX_STATUS_ENTRY(BT_RETRY);
218 TX_STATUS_ENTRY(STA_INVALID);
219 TX_STATUS_ENTRY(FRAG_DROPPED);
220 TX_STATUS_ENTRY(TID_DISABLE);
221 TX_STATUS_ENTRY(FRAME_FLUSHED);
222 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
223 TX_STATUS_ENTRY(TX_LOCKED);
224 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
225 }
226
227 return "UNKNOWN";
228 }
229 #else
230 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
231 {
232 return "";
233 }
234 #endif
235
236 /*
237 * get ieee prev rate from rate scale table.
238 * for A and B mode we need to overright prev
239 * value
240 */
241 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
242 {
243 int next_rate = iwl3945_get_prev_ieee_rate(rate);
244
245 switch (priv->band) {
246 case IEEE80211_BAND_5GHZ:
247 if (rate == IWL_RATE_12M_INDEX)
248 next_rate = IWL_RATE_9M_INDEX;
249 else if (rate == IWL_RATE_6M_INDEX)
250 next_rate = IWL_RATE_6M_INDEX;
251 break;
252 case IEEE80211_BAND_2GHZ:
253 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
254 iwl_is_associated(priv)) {
255 if (rate == IWL_RATE_11M_INDEX)
256 next_rate = IWL_RATE_5M_INDEX;
257 }
258 break;
259
260 default:
261 break;
262 }
263
264 return next_rate;
265 }
266
267
268 /**
269 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
270 *
271 * When FW advances 'R' index, all entries between old and new 'R' index
272 * need to be reclaimed. As result, some free space forms. If there is
273 * enough free space (> low mark), wake the stack that feeds us.
274 */
275 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
276 int txq_id, int index)
277 {
278 struct iwl_tx_queue *txq = &priv->txq[txq_id];
279 struct iwl_queue *q = &txq->q;
280 struct iwl_tx_info *tx_info;
281
282 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
283
284 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
285 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
286
287 tx_info = &txq->txb[txq->q.read_ptr];
288 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
289 tx_info->skb[0] = NULL;
290 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
291 }
292
293 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
294 (txq_id != IWL_CMD_QUEUE_NUM) &&
295 priv->mac80211_registered)
296 ieee80211_wake_queue(priv->hw, txq_id);
297 }
298
299 /**
300 * iwl3945_rx_reply_tx - Handle Tx response
301 */
302 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
303 struct iwl_rx_mem_buffer *rxb)
304 {
305 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
306 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
307 int txq_id = SEQ_TO_QUEUE(sequence);
308 int index = SEQ_TO_INDEX(sequence);
309 struct iwl_tx_queue *txq = &priv->txq[txq_id];
310 struct ieee80211_tx_info *info;
311 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
312 u32 status = le32_to_cpu(tx_resp->status);
313 int rate_idx;
314 int fail;
315
316 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
317 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
318 "is out of range [0-%d] %d %d\n", txq_id,
319 index, txq->q.n_bd, txq->q.write_ptr,
320 txq->q.read_ptr);
321 return;
322 }
323
324 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
325 ieee80211_tx_info_clear_status(info);
326
327 /* Fill the MRR chain with some info about on-chip retransmissions */
328 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
329 if (info->band == IEEE80211_BAND_5GHZ)
330 rate_idx -= IWL_FIRST_OFDM_RATE;
331
332 fail = tx_resp->failure_frame;
333
334 info->status.rates[0].idx = rate_idx;
335 info->status.rates[0].count = fail + 1; /* add final attempt */
336
337 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
338 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
339 IEEE80211_TX_STAT_ACK : 0;
340
341 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
342 txq_id, iwl3945_get_tx_fail_reason(status), status,
343 tx_resp->rate, tx_resp->failure_frame);
344
345 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
346 iwl3945_tx_queue_reclaim(priv, txq_id, index);
347
348 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
349 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
350 }
351
352
353
354 /*****************************************************************************
355 *
356 * Intel PRO/Wireless 3945ABG/BG Network Connection
357 *
358 * RX handler implementations
359 *
360 *****************************************************************************/
361
362 void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
363 {
364 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
365 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
366 (int)sizeof(struct iwl3945_notif_statistics),
367 le32_to_cpu(pkt->len));
368
369 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
370
371 iwl3945_led_background(priv);
372
373 priv->last_statistics_time = jiffies;
374 }
375
376 /******************************************************************************
377 *
378 * Misc. internal state and helper functions
379 *
380 ******************************************************************************/
381 #ifdef CONFIG_IWLWIFI_DEBUG
382
383 /**
384 * iwl3945_report_frame - dump frame to syslog during debug sessions
385 *
386 * You may hack this function to show different aspects of received frames,
387 * including selective frame dumps.
388 * group100 parameter selects whether to show 1 out of 100 good frames.
389 */
390 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
391 struct iwl_rx_packet *pkt,
392 struct ieee80211_hdr *header, int group100)
393 {
394 u32 to_us;
395 u32 print_summary = 0;
396 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
397 u32 hundred = 0;
398 u32 dataframe = 0;
399 __le16 fc;
400 u16 seq_ctl;
401 u16 channel;
402 u16 phy_flags;
403 u16 length;
404 u16 status;
405 u16 bcn_tmr;
406 u32 tsf_low;
407 u64 tsf;
408 u8 rssi;
409 u8 agc;
410 u16 sig_avg;
411 u16 noise_diff;
412 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
413 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
414 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
415 u8 *data = IWL_RX_DATA(pkt);
416
417 /* MAC header */
418 fc = header->frame_control;
419 seq_ctl = le16_to_cpu(header->seq_ctrl);
420
421 /* metadata */
422 channel = le16_to_cpu(rx_hdr->channel);
423 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
424 length = le16_to_cpu(rx_hdr->len);
425
426 /* end-of-frame status and timestamp */
427 status = le32_to_cpu(rx_end->status);
428 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
429 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
430 tsf = le64_to_cpu(rx_end->timestamp);
431
432 /* signal statistics */
433 rssi = rx_stats->rssi;
434 agc = rx_stats->agc;
435 sig_avg = le16_to_cpu(rx_stats->sig_avg);
436 noise_diff = le16_to_cpu(rx_stats->noise_diff);
437
438 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
439
440 /* if data frame is to us and all is good,
441 * (optionally) print summary for only 1 out of every 100 */
442 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
443 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
444 dataframe = 1;
445 if (!group100)
446 print_summary = 1; /* print each frame */
447 else if (priv->framecnt_to_us < 100) {
448 priv->framecnt_to_us++;
449 print_summary = 0;
450 } else {
451 priv->framecnt_to_us = 0;
452 print_summary = 1;
453 hundred = 1;
454 }
455 } else {
456 /* print summary for all other frames */
457 print_summary = 1;
458 }
459
460 if (print_summary) {
461 char *title;
462 int rate;
463
464 if (hundred)
465 title = "100Frames";
466 else if (ieee80211_has_retry(fc))
467 title = "Retry";
468 else if (ieee80211_is_assoc_resp(fc))
469 title = "AscRsp";
470 else if (ieee80211_is_reassoc_resp(fc))
471 title = "RasRsp";
472 else if (ieee80211_is_probe_resp(fc)) {
473 title = "PrbRsp";
474 print_dump = 1; /* dump frame contents */
475 } else if (ieee80211_is_beacon(fc)) {
476 title = "Beacon";
477 print_dump = 1; /* dump frame contents */
478 } else if (ieee80211_is_atim(fc))
479 title = "ATIM";
480 else if (ieee80211_is_auth(fc))
481 title = "Auth";
482 else if (ieee80211_is_deauth(fc))
483 title = "DeAuth";
484 else if (ieee80211_is_disassoc(fc))
485 title = "DisAssoc";
486 else
487 title = "Frame";
488
489 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
490 if (rate == -1)
491 rate = 0;
492 else
493 rate = iwl3945_rates[rate].ieee / 2;
494
495 /* print frame summary.
496 * MAC addresses show just the last byte (for brevity),
497 * but you can hack it to show more, if you'd like to. */
498 if (dataframe)
499 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
500 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
501 title, le16_to_cpu(fc), header->addr1[5],
502 length, rssi, channel, rate);
503 else {
504 /* src/dst addresses assume managed mode */
505 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
506 "src=0x%02x, rssi=%u, tim=%lu usec, "
507 "phy=0x%02x, chnl=%d\n",
508 title, le16_to_cpu(fc), header->addr1[5],
509 header->addr3[5], rssi,
510 tsf_low - priv->scan_start_tsf,
511 phy_flags, channel);
512 }
513 }
514 if (print_dump)
515 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
516 }
517
518 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
519 struct iwl_rx_packet *pkt,
520 struct ieee80211_hdr *header, int group100)
521 {
522 if (priv->debug_level & IWL_DL_RX)
523 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
524 }
525
526 #else
527 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
528 struct iwl_rx_packet *pkt,
529 struct ieee80211_hdr *header, int group100)
530 {
531 }
532 #endif
533
534 /* This is necessary only for a number of statistics, see the caller. */
535 static int iwl3945_is_network_packet(struct iwl_priv *priv,
536 struct ieee80211_hdr *header)
537 {
538 /* Filter incoming packets to determine if they are targeted toward
539 * this network, discarding packets coming from ourselves */
540 switch (priv->iw_mode) {
541 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
542 /* packets to our IBSS update information */
543 return !compare_ether_addr(header->addr3, priv->bssid);
544 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
545 /* packets to our IBSS update information */
546 return !compare_ether_addr(header->addr2, priv->bssid);
547 default:
548 return 1;
549 }
550 }
551
552 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
553 struct iwl_rx_mem_buffer *rxb,
554 struct ieee80211_rx_status *stats)
555 {
556 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
557 #ifdef CONFIG_IWL3945_LEDS
558 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
559 #endif
560 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
561 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
562 short len = le16_to_cpu(rx_hdr->len);
563
564 /* We received data from the HW, so stop the watchdog */
565 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
566 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
567 return;
568 }
569
570 /* We only process data packets if the interface is open */
571 if (unlikely(!priv->is_open)) {
572 IWL_DEBUG_DROP_LIMIT(priv,
573 "Dropping packet while interface is not open.\n");
574 return;
575 }
576
577 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
578 /* Set the size of the skb to the size of the frame */
579 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
580
581 if (!iwl3945_mod_params.sw_crypto)
582 iwl_set_decrypted_flag(priv,
583 (struct ieee80211_hdr *)rxb->skb->data,
584 le32_to_cpu(rx_end->status), stats);
585
586 #ifdef CONFIG_IWL3945_LEDS
587 if (ieee80211_is_data(hdr->frame_control))
588 priv->rxtxpackets += len;
589 #endif
590 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
591 rxb->skb = NULL;
592 }
593
594 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
595
596 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
597 struct iwl_rx_mem_buffer *rxb)
598 {
599 struct ieee80211_hdr *header;
600 struct ieee80211_rx_status rx_status;
601 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
602 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
603 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
604 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
605 int snr;
606 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
607 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
608 u8 network_packet;
609
610 rx_status.flag = 0;
611 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
612 rx_status.freq =
613 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
614 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
615 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
616
617 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
618 if (rx_status.band == IEEE80211_BAND_5GHZ)
619 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
620
621 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
622 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
623
624 /* set the preamble flag if appropriate */
625 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
626 rx_status.flag |= RX_FLAG_SHORTPRE;
627
628 if ((unlikely(rx_stats->phy_count > 20))) {
629 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
630 rx_stats->phy_count);
631 return;
632 }
633
634 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
635 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
636 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
637 return;
638 }
639
640
641
642 /* Convert 3945's rssi indicator to dBm */
643 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
644
645 /* Set default noise value to -127 */
646 if (priv->last_rx_noise == 0)
647 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
648
649 /* 3945 provides noise info for OFDM frames only.
650 * sig_avg and noise_diff are measured by the 3945's digital signal
651 * processor (DSP), and indicate linear levels of signal level and
652 * distortion/noise within the packet preamble after
653 * automatic gain control (AGC). sig_avg should stay fairly
654 * constant if the radio's AGC is working well.
655 * Since these values are linear (not dB or dBm), linear
656 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
657 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
658 * to obtain noise level in dBm.
659 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
660 if (rx_stats_noise_diff) {
661 snr = rx_stats_sig_avg / rx_stats_noise_diff;
662 rx_status.noise = rx_status.signal -
663 iwl3945_calc_db_from_ratio(snr);
664 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
665 rx_status.noise);
666
667 /* If noise info not available, calculate signal quality indicator (%)
668 * using just the dBm signal level. */
669 } else {
670 rx_status.noise = priv->last_rx_noise;
671 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
672 }
673
674
675 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
676 rx_status.signal, rx_status.noise, rx_status.qual,
677 rx_stats_sig_avg, rx_stats_noise_diff);
678
679 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
680
681 network_packet = iwl3945_is_network_packet(priv, header);
682
683 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
684 network_packet ? '*' : ' ',
685 le16_to_cpu(rx_hdr->channel),
686 rx_status.signal, rx_status.signal,
687 rx_status.noise, rx_status.rate_idx);
688
689 /* Set "1" to report good data frames in groups of 100 */
690 iwl3945_dbg_report_frame(priv, pkt, header, 1);
691
692 if (network_packet) {
693 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
694 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
695 priv->last_rx_rssi = rx_status.signal;
696 priv->last_rx_noise = rx_status.noise;
697 }
698
699 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
700 }
701
702 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
703 struct iwl_tx_queue *txq,
704 dma_addr_t addr, u16 len, u8 reset, u8 pad)
705 {
706 int count;
707 struct iwl_queue *q;
708 struct iwl3945_tfd *tfd, *tfd_tmp;
709
710 q = &txq->q;
711 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
712 tfd = &tfd_tmp[q->write_ptr];
713
714 if (reset)
715 memset(tfd, 0, sizeof(*tfd));
716
717 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
718
719 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
720 IWL_ERR(priv, "Error can not send more than %d chunks\n",
721 NUM_TFD_CHUNKS);
722 return -EINVAL;
723 }
724
725 tfd->tbs[count].addr = cpu_to_le32(addr);
726 tfd->tbs[count].len = cpu_to_le32(len);
727
728 count++;
729
730 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
731 TFD_CTL_PAD_SET(pad));
732
733 return 0;
734 }
735
736 /**
737 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
738 *
739 * Does NOT advance any indexes
740 */
741 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
742 {
743 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
744 struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
745 struct pci_dev *dev = priv->pci_dev;
746 int i;
747 int counter;
748
749 /* classify bd */
750 if (txq->q.id == IWL_CMD_QUEUE_NUM)
751 /* nothing to cleanup after for host commands */
752 return;
753
754 /* sanity check */
755 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
756 if (counter > NUM_TFD_CHUNKS) {
757 IWL_ERR(priv, "Too many chunks: %i\n", counter);
758 /* @todo issue fatal error, it is quite serious situation */
759 return;
760 }
761
762 /* unmap chunks if any */
763
764 for (i = 1; i < counter; i++) {
765 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
766 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
767 if (txq->txb[txq->q.read_ptr].skb[0]) {
768 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
769 if (txq->txb[txq->q.read_ptr].skb[0]) {
770 /* Can be called from interrupt context */
771 dev_kfree_skb_any(skb);
772 txq->txb[txq->q.read_ptr].skb[0] = NULL;
773 }
774 }
775 }
776 return ;
777 }
778
779 u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
780 {
781 int i, start = IWL_AP_ID;
782 int ret = IWL_INVALID_STATION;
783 unsigned long flags;
784
785 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
786 (priv->iw_mode == NL80211_IFTYPE_AP))
787 start = IWL_STA_ID;
788
789 if (is_broadcast_ether_addr(addr))
790 return priv->hw_params.bcast_sta_id;
791
792 spin_lock_irqsave(&priv->sta_lock, flags);
793 for (i = start; i < priv->hw_params.max_stations; i++)
794 if ((priv->stations_39[i].used) &&
795 (!compare_ether_addr
796 (priv->stations_39[i].sta.sta.addr, addr))) {
797 ret = i;
798 goto out;
799 }
800
801 IWL_DEBUG_INFO(priv, "can not find STA %pM (total %d)\n",
802 addr, priv->num_stations);
803 out:
804 spin_unlock_irqrestore(&priv->sta_lock, flags);
805 return ret;
806 }
807
808 /**
809 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
810 *
811 */
812 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
813 struct ieee80211_tx_info *info,
814 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
815 {
816 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
817 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
818 u16 rate_mask;
819 int rate;
820 u8 rts_retry_limit;
821 u8 data_retry_limit;
822 __le32 tx_flags;
823 __le16 fc = hdr->frame_control;
824 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
825
826 rate = iwl3945_rates[rate_index].plcp;
827 tx_flags = tx->tx_flags;
828
829 /* We need to figure out how to get the sta->supp_rates while
830 * in this running context */
831 rate_mask = IWL_RATES_MASK;
832
833 if (tx_id >= IWL_CMD_QUEUE_NUM)
834 rts_retry_limit = 3;
835 else
836 rts_retry_limit = 7;
837
838 if (ieee80211_is_probe_resp(fc)) {
839 data_retry_limit = 3;
840 if (data_retry_limit < rts_retry_limit)
841 rts_retry_limit = data_retry_limit;
842 } else
843 data_retry_limit = IWL_DEFAULT_TX_RETRY;
844
845 if (priv->data_retry_limit != -1)
846 data_retry_limit = priv->data_retry_limit;
847
848 if (ieee80211_is_mgmt(fc)) {
849 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
850 case cpu_to_le16(IEEE80211_STYPE_AUTH):
851 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
852 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
853 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
854 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
855 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
856 tx_flags |= TX_CMD_FLG_CTS_MSK;
857 }
858 break;
859 default:
860 break;
861 }
862 }
863
864 tx->rts_retry_limit = rts_retry_limit;
865 tx->data_retry_limit = data_retry_limit;
866 tx->rate = rate;
867 tx->tx_flags = tx_flags;
868
869 /* OFDM */
870 tx->supp_rates[0] =
871 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
872
873 /* CCK */
874 tx->supp_rates[1] = (rate_mask & 0xF);
875
876 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
877 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
878 tx->rate, le32_to_cpu(tx->tx_flags),
879 tx->supp_rates[1], tx->supp_rates[0]);
880 }
881
882 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
883 {
884 unsigned long flags_spin;
885 struct iwl3945_station_entry *station;
886
887 if (sta_id == IWL_INVALID_STATION)
888 return IWL_INVALID_STATION;
889
890 spin_lock_irqsave(&priv->sta_lock, flags_spin);
891 station = &priv->stations_39[sta_id];
892
893 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
894 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
895 station->sta.mode = STA_CONTROL_MODIFY_MSK;
896
897 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
898
899 iwl_send_add_sta(priv,
900 (struct iwl_addsta_cmd *)&station->sta, flags);
901 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
902 sta_id, tx_rate);
903 return sta_id;
904 }
905
906 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
907 {
908 int ret;
909 unsigned long flags;
910
911 spin_lock_irqsave(&priv->lock, flags);
912 ret = iwl_grab_nic_access(priv);
913 if (ret) {
914 spin_unlock_irqrestore(&priv->lock, flags);
915 return ret;
916 }
917
918 if (src == IWL_PWR_SRC_VAUX) {
919 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
920 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
921 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
922 ~APMG_PS_CTRL_MSK_PWR_SRC);
923 iwl_release_nic_access(priv);
924
925 iwl_poll_bit(priv, CSR_GPIO_IN,
926 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
927 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
928 } else {
929 iwl_release_nic_access(priv);
930 }
931 } else {
932 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
933 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
934 ~APMG_PS_CTRL_MSK_PWR_SRC);
935
936 iwl_release_nic_access(priv);
937 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
938 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
939 }
940 spin_unlock_irqrestore(&priv->lock, flags);
941
942 return ret;
943 }
944
945 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
946 {
947 int rc;
948 unsigned long flags;
949
950 spin_lock_irqsave(&priv->lock, flags);
951 rc = iwl_grab_nic_access(priv);
952 if (rc) {
953 spin_unlock_irqrestore(&priv->lock, flags);
954 return rc;
955 }
956
957 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
958 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
959 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
960 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
961 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
962 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
963 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
964 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
965 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
966 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
967 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
968 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
969
970 /* fake read to flush all prev I/O */
971 iwl_read_direct32(priv, FH39_RSSR_CTRL);
972
973 iwl_release_nic_access(priv);
974 spin_unlock_irqrestore(&priv->lock, flags);
975
976 return 0;
977 }
978
979 static int iwl3945_tx_reset(struct iwl_priv *priv)
980 {
981 int rc;
982 unsigned long flags;
983
984 spin_lock_irqsave(&priv->lock, flags);
985 rc = iwl_grab_nic_access(priv);
986 if (rc) {
987 spin_unlock_irqrestore(&priv->lock, flags);
988 return rc;
989 }
990
991 /* bypass mode */
992 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
993
994 /* RA 0 is active */
995 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
996
997 /* all 6 fifo are active */
998 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
999
1000 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1001 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1002 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1003 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1004
1005 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1006 priv->shared_phys);
1007
1008 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1009 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1010 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1011 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1012 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1013 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1014 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1015 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1016
1017 iwl_release_nic_access(priv);
1018 spin_unlock_irqrestore(&priv->lock, flags);
1019
1020 return 0;
1021 }
1022
1023 /**
1024 * iwl3945_txq_ctx_reset - Reset TX queue context
1025 *
1026 * Destroys all DMA structures and initialize them again
1027 */
1028 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1029 {
1030 int rc;
1031 int txq_id, slots_num;
1032
1033 iwl3945_hw_txq_ctx_free(priv);
1034
1035 /* Tx CMD queue */
1036 rc = iwl3945_tx_reset(priv);
1037 if (rc)
1038 goto error;
1039
1040 /* Tx queue(s) */
1041 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1042 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1043 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1044 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1045 txq_id);
1046 if (rc) {
1047 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1048 goto error;
1049 }
1050 }
1051
1052 return rc;
1053
1054 error:
1055 iwl3945_hw_txq_ctx_free(priv);
1056 return rc;
1057 }
1058
1059 static int iwl3945_apm_init(struct iwl_priv *priv)
1060 {
1061 int ret = 0;
1062
1063 iwl_power_initialize(priv);
1064
1065 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1066 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1067
1068 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1069 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1070 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1071
1072 /* set "initialization complete" bit to move adapter
1073 * D0U* --> D0A* state */
1074 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1075
1076 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1077 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1078 if (ret < 0) {
1079 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1080 goto out;
1081 }
1082
1083 ret = iwl_grab_nic_access(priv);
1084 if (ret)
1085 goto out;
1086
1087 /* enable DMA */
1088 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1089 APMG_CLK_VAL_BSM_CLK_RQT);
1090
1091 udelay(20);
1092
1093 /* disable L1-Active */
1094 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1095 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1096
1097 iwl_release_nic_access(priv);
1098 out:
1099 return ret;
1100 }
1101
1102 static void iwl3945_nic_config(struct iwl_priv *priv)
1103 {
1104 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1105 unsigned long flags;
1106 u8 rev_id = 0;
1107
1108 spin_lock_irqsave(&priv->lock, flags);
1109
1110 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1111 IWL_DEBUG_INFO(priv, "RTP type \n");
1112 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1113 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1114 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1115 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1116 } else {
1117 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1118 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1119 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1120 }
1121
1122 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1123 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1124 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1125 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1126 } else
1127 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1128
1129 if ((eeprom->board_revision & 0xF0) == 0xD0) {
1130 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1131 eeprom->board_revision);
1132 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1133 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1134 } else {
1135 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1136 eeprom->board_revision);
1137 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1138 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1139 }
1140
1141 if (eeprom->almgor_m_version <= 1) {
1142 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1143 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1144 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1145 eeprom->almgor_m_version);
1146 } else {
1147 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1148 eeprom->almgor_m_version);
1149 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1150 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1151 }
1152 spin_unlock_irqrestore(&priv->lock, flags);
1153
1154 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1155 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1156
1157 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1158 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1159 }
1160
1161 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1162 {
1163 u8 rev_id;
1164 int rc;
1165 unsigned long flags;
1166 struct iwl_rx_queue *rxq = &priv->rxq;
1167
1168 spin_lock_irqsave(&priv->lock, flags);
1169 priv->cfg->ops->lib->apm_ops.init(priv);
1170 spin_unlock_irqrestore(&priv->lock, flags);
1171
1172 /* Determine HW type */
1173 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1174 if (rc)
1175 return rc;
1176 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1177
1178 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1179 if(rc)
1180 return rc;
1181
1182 priv->cfg->ops->lib->apm_ops.config(priv);
1183
1184 /* Allocate the RX queue, or reset if it is already allocated */
1185 if (!rxq->bd) {
1186 rc = iwl_rx_queue_alloc(priv);
1187 if (rc) {
1188 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1189 return -ENOMEM;
1190 }
1191 } else
1192 iwl_rx_queue_reset(priv, rxq);
1193
1194 iwl3945_rx_replenish(priv);
1195
1196 iwl3945_rx_init(priv, rxq);
1197
1198 spin_lock_irqsave(&priv->lock, flags);
1199
1200 /* Look at using this instead:
1201 rxq->need_update = 1;
1202 iwl_rx_queue_update_write_ptr(priv, rxq);
1203 */
1204
1205 rc = iwl_grab_nic_access(priv);
1206 if (rc) {
1207 spin_unlock_irqrestore(&priv->lock, flags);
1208 return rc;
1209 }
1210 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1211 iwl_release_nic_access(priv);
1212
1213 spin_unlock_irqrestore(&priv->lock, flags);
1214
1215 rc = iwl3945_txq_ctx_reset(priv);
1216 if (rc)
1217 return rc;
1218
1219 set_bit(STATUS_INIT, &priv->status);
1220
1221 return 0;
1222 }
1223
1224 /**
1225 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1226 *
1227 * Destroy all TX DMA queues and structures
1228 */
1229 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1230 {
1231 int txq_id;
1232
1233 /* Tx queues */
1234 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1235 iwl_tx_queue_free(priv, txq_id);
1236 }
1237
1238 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1239 {
1240 int txq_id;
1241 unsigned long flags;
1242
1243 spin_lock_irqsave(&priv->lock, flags);
1244 if (iwl_grab_nic_access(priv)) {
1245 spin_unlock_irqrestore(&priv->lock, flags);
1246 iwl3945_hw_txq_ctx_free(priv);
1247 return;
1248 }
1249
1250 /* stop SCD */
1251 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1252
1253 /* reset TFD queues */
1254 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1255 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1256 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1257 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1258 1000);
1259 }
1260
1261 iwl_release_nic_access(priv);
1262 spin_unlock_irqrestore(&priv->lock, flags);
1263
1264 iwl3945_hw_txq_ctx_free(priv);
1265 }
1266
1267 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1268 {
1269 int ret = 0;
1270 unsigned long flags;
1271
1272 spin_lock_irqsave(&priv->lock, flags);
1273
1274 /* set stop master bit */
1275 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1276
1277 iwl_poll_direct_bit(priv, CSR_RESET,
1278 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1279
1280 if (ret < 0)
1281 goto out;
1282
1283 out:
1284 spin_unlock_irqrestore(&priv->lock, flags);
1285 IWL_DEBUG_INFO(priv, "stop master\n");
1286
1287 return ret;
1288 }
1289
1290 static void iwl3945_apm_stop(struct iwl_priv *priv)
1291 {
1292 unsigned long flags;
1293
1294 iwl3945_apm_stop_master(priv);
1295
1296 spin_lock_irqsave(&priv->lock, flags);
1297
1298 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1299
1300 udelay(10);
1301 /* clear "init complete" move adapter D0A* --> D0U state */
1302 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1303 spin_unlock_irqrestore(&priv->lock, flags);
1304 }
1305
1306 static int iwl3945_apm_reset(struct iwl_priv *priv)
1307 {
1308 int rc;
1309 unsigned long flags;
1310
1311 iwl3945_apm_stop_master(priv);
1312
1313 spin_lock_irqsave(&priv->lock, flags);
1314
1315 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1316 udelay(10);
1317
1318 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1319
1320 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1321 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1322
1323 rc = iwl_grab_nic_access(priv);
1324 if (!rc) {
1325 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1326 APMG_CLK_VAL_BSM_CLK_RQT);
1327
1328 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1329 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1330 0xFFFFFFFF);
1331
1332 /* enable DMA */
1333 iwl_write_prph(priv, APMG_CLK_EN_REG,
1334 APMG_CLK_VAL_DMA_CLK_RQT |
1335 APMG_CLK_VAL_BSM_CLK_RQT);
1336 udelay(10);
1337
1338 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1339 APMG_PS_CTRL_VAL_RESET_REQ);
1340 udelay(5);
1341 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1342 APMG_PS_CTRL_VAL_RESET_REQ);
1343 iwl_release_nic_access(priv);
1344 }
1345
1346 /* Clear the 'host command active' bit... */
1347 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1348
1349 wake_up_interruptible(&priv->wait_command_queue);
1350 spin_unlock_irqrestore(&priv->lock, flags);
1351
1352 return rc;
1353 }
1354
1355 /**
1356 * iwl3945_hw_reg_adjust_power_by_temp
1357 * return index delta into power gain settings table
1358 */
1359 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1360 {
1361 return (new_reading - old_reading) * (-11) / 100;
1362 }
1363
1364 /**
1365 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1366 */
1367 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1368 {
1369 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1370 }
1371
1372 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1373 {
1374 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1375 }
1376
1377 /**
1378 * iwl3945_hw_reg_txpower_get_temperature
1379 * get the current temperature by reading from NIC
1380 */
1381 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1382 {
1383 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1384 int temperature;
1385
1386 temperature = iwl3945_hw_get_temperature(priv);
1387
1388 /* driver's okay range is -260 to +25.
1389 * human readable okay range is 0 to +285 */
1390 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1391
1392 /* handle insane temp reading */
1393 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1394 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1395
1396 /* if really really hot(?),
1397 * substitute the 3rd band/group's temp measured at factory */
1398 if (priv->last_temperature > 100)
1399 temperature = eeprom->groups[2].temperature;
1400 else /* else use most recent "sane" value from driver */
1401 temperature = priv->last_temperature;
1402 }
1403
1404 return temperature; /* raw, not "human readable" */
1405 }
1406
1407 /* Adjust Txpower only if temperature variance is greater than threshold.
1408 *
1409 * Both are lower than older versions' 9 degrees */
1410 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1411
1412 /**
1413 * is_temp_calib_needed - determines if new calibration is needed
1414 *
1415 * records new temperature in tx_mgr->temperature.
1416 * replaces tx_mgr->last_temperature *only* if calib needed
1417 * (assumes caller will actually do the calibration!). */
1418 static int is_temp_calib_needed(struct iwl_priv *priv)
1419 {
1420 int temp_diff;
1421
1422 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1423 temp_diff = priv->temperature - priv->last_temperature;
1424
1425 /* get absolute value */
1426 if (temp_diff < 0) {
1427 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1428 temp_diff = -temp_diff;
1429 } else if (temp_diff == 0)
1430 IWL_DEBUG_POWER(priv, "Same temp,\n");
1431 else
1432 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1433
1434 /* if we don't need calibration, *don't* update last_temperature */
1435 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1436 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1437 return 0;
1438 }
1439
1440 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1441
1442 /* assume that caller will actually do calib ...
1443 * update the "last temperature" value */
1444 priv->last_temperature = priv->temperature;
1445 return 1;
1446 }
1447
1448 #define IWL_MAX_GAIN_ENTRIES 78
1449 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1450 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1451
1452 /* radio and DSP power table, each step is 1/2 dB.
1453 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1454 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1455 {
1456 {251, 127}, /* 2.4 GHz, highest power */
1457 {251, 127},
1458 {251, 127},
1459 {251, 127},
1460 {251, 125},
1461 {251, 110},
1462 {251, 105},
1463 {251, 98},
1464 {187, 125},
1465 {187, 115},
1466 {187, 108},
1467 {187, 99},
1468 {243, 119},
1469 {243, 111},
1470 {243, 105},
1471 {243, 97},
1472 {243, 92},
1473 {211, 106},
1474 {211, 100},
1475 {179, 120},
1476 {179, 113},
1477 {179, 107},
1478 {147, 125},
1479 {147, 119},
1480 {147, 112},
1481 {147, 106},
1482 {147, 101},
1483 {147, 97},
1484 {147, 91},
1485 {115, 107},
1486 {235, 121},
1487 {235, 115},
1488 {235, 109},
1489 {203, 127},
1490 {203, 121},
1491 {203, 115},
1492 {203, 108},
1493 {203, 102},
1494 {203, 96},
1495 {203, 92},
1496 {171, 110},
1497 {171, 104},
1498 {171, 98},
1499 {139, 116},
1500 {227, 125},
1501 {227, 119},
1502 {227, 113},
1503 {227, 107},
1504 {227, 101},
1505 {227, 96},
1506 {195, 113},
1507 {195, 106},
1508 {195, 102},
1509 {195, 95},
1510 {163, 113},
1511 {163, 106},
1512 {163, 102},
1513 {163, 95},
1514 {131, 113},
1515 {131, 106},
1516 {131, 102},
1517 {131, 95},
1518 {99, 113},
1519 {99, 106},
1520 {99, 102},
1521 {99, 95},
1522 {67, 113},
1523 {67, 106},
1524 {67, 102},
1525 {67, 95},
1526 {35, 113},
1527 {35, 106},
1528 {35, 102},
1529 {35, 95},
1530 {3, 113},
1531 {3, 106},
1532 {3, 102},
1533 {3, 95} }, /* 2.4 GHz, lowest power */
1534 {
1535 {251, 127}, /* 5.x GHz, highest power */
1536 {251, 120},
1537 {251, 114},
1538 {219, 119},
1539 {219, 101},
1540 {187, 113},
1541 {187, 102},
1542 {155, 114},
1543 {155, 103},
1544 {123, 117},
1545 {123, 107},
1546 {123, 99},
1547 {123, 92},
1548 {91, 108},
1549 {59, 125},
1550 {59, 118},
1551 {59, 109},
1552 {59, 102},
1553 {59, 96},
1554 {59, 90},
1555 {27, 104},
1556 {27, 98},
1557 {27, 92},
1558 {115, 118},
1559 {115, 111},
1560 {115, 104},
1561 {83, 126},
1562 {83, 121},
1563 {83, 113},
1564 {83, 105},
1565 {83, 99},
1566 {51, 118},
1567 {51, 111},
1568 {51, 104},
1569 {51, 98},
1570 {19, 116},
1571 {19, 109},
1572 {19, 102},
1573 {19, 98},
1574 {19, 93},
1575 {171, 113},
1576 {171, 107},
1577 {171, 99},
1578 {139, 120},
1579 {139, 113},
1580 {139, 107},
1581 {139, 99},
1582 {107, 120},
1583 {107, 113},
1584 {107, 107},
1585 {107, 99},
1586 {75, 120},
1587 {75, 113},
1588 {75, 107},
1589 {75, 99},
1590 {43, 120},
1591 {43, 113},
1592 {43, 107},
1593 {43, 99},
1594 {11, 120},
1595 {11, 113},
1596 {11, 107},
1597 {11, 99},
1598 {131, 107},
1599 {131, 99},
1600 {99, 120},
1601 {99, 113},
1602 {99, 107},
1603 {99, 99},
1604 {67, 120},
1605 {67, 113},
1606 {67, 107},
1607 {67, 99},
1608 {35, 120},
1609 {35, 113},
1610 {35, 107},
1611 {35, 99},
1612 {3, 120} } /* 5.x GHz, lowest power */
1613 };
1614
1615 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1616 {
1617 if (index < 0)
1618 return 0;
1619 if (index >= IWL_MAX_GAIN_ENTRIES)
1620 return IWL_MAX_GAIN_ENTRIES - 1;
1621 return (u8) index;
1622 }
1623
1624 /* Kick off thermal recalibration check every 60 seconds */
1625 #define REG_RECALIB_PERIOD (60)
1626
1627 /**
1628 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1629 *
1630 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1631 * or 6 Mbit (OFDM) rates.
1632 */
1633 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1634 s32 rate_index, const s8 *clip_pwrs,
1635 struct iwl_channel_info *ch_info,
1636 int band_index)
1637 {
1638 struct iwl3945_scan_power_info *scan_power_info;
1639 s8 power;
1640 u8 power_index;
1641
1642 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1643
1644 /* use this channel group's 6Mbit clipping/saturation pwr,
1645 * but cap at regulatory scan power restriction (set during init
1646 * based on eeprom channel data) for this channel. */
1647 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1648
1649 /* further limit to user's max power preference.
1650 * FIXME: Other spectrum management power limitations do not
1651 * seem to apply?? */
1652 power = min(power, priv->tx_power_user_lmt);
1653 scan_power_info->requested_power = power;
1654
1655 /* find difference between new scan *power* and current "normal"
1656 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1657 * current "normal" temperature-compensated Tx power *index* for
1658 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1659 * *index*. */
1660 power_index = ch_info->power_info[rate_index].power_table_index
1661 - (power - ch_info->power_info
1662 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1663
1664 /* store reference index that we use when adjusting *all* scan
1665 * powers. So we can accommodate user (all channel) or spectrum
1666 * management (single channel) power changes "between" temperature
1667 * feedback compensation procedures.
1668 * don't force fit this reference index into gain table; it may be a
1669 * negative number. This will help avoid errors when we're at
1670 * the lower bounds (highest gains, for warmest temperatures)
1671 * of the table. */
1672
1673 /* don't exceed table bounds for "real" setting */
1674 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1675
1676 scan_power_info->power_table_index = power_index;
1677 scan_power_info->tpc.tx_gain =
1678 power_gain_table[band_index][power_index].tx_gain;
1679 scan_power_info->tpc.dsp_atten =
1680 power_gain_table[band_index][power_index].dsp_atten;
1681 }
1682
1683 /**
1684 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1685 *
1686 * Configures power settings for all rates for the current channel,
1687 * using values from channel info struct, and send to NIC
1688 */
1689 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1690 {
1691 int rate_idx, i;
1692 const struct iwl_channel_info *ch_info = NULL;
1693 struct iwl3945_txpowertable_cmd txpower = {
1694 .channel = priv->active_rxon.channel,
1695 };
1696
1697 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1698 ch_info = iwl_get_channel_info(priv,
1699 priv->band,
1700 le16_to_cpu(priv->active_rxon.channel));
1701 if (!ch_info) {
1702 IWL_ERR(priv,
1703 "Failed to get channel info for channel %d [%d]\n",
1704 le16_to_cpu(priv->active_rxon.channel), priv->band);
1705 return -EINVAL;
1706 }
1707
1708 if (!is_channel_valid(ch_info)) {
1709 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1710 "non-Tx channel.\n");
1711 return 0;
1712 }
1713
1714 /* fill cmd with power settings for all rates for current channel */
1715 /* Fill OFDM rate */
1716 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1717 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1718
1719 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1720 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1721
1722 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1723 le16_to_cpu(txpower.channel),
1724 txpower.band,
1725 txpower.power[i].tpc.tx_gain,
1726 txpower.power[i].tpc.dsp_atten,
1727 txpower.power[i].rate);
1728 }
1729 /* Fill CCK rates */
1730 for (rate_idx = IWL_FIRST_CCK_RATE;
1731 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1732 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1733 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1734
1735 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1736 le16_to_cpu(txpower.channel),
1737 txpower.band,
1738 txpower.power[i].tpc.tx_gain,
1739 txpower.power[i].tpc.dsp_atten,
1740 txpower.power[i].rate);
1741 }
1742
1743 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1744 sizeof(struct iwl3945_txpowertable_cmd),
1745 &txpower);
1746
1747 }
1748
1749 /**
1750 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1751 * @ch_info: Channel to update. Uses power_info.requested_power.
1752 *
1753 * Replace requested_power and base_power_index ch_info fields for
1754 * one channel.
1755 *
1756 * Called if user or spectrum management changes power preferences.
1757 * Takes into account h/w and modulation limitations (clip power).
1758 *
1759 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1760 *
1761 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1762 * properly fill out the scan powers, and actual h/w gain settings,
1763 * and send changes to NIC
1764 */
1765 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1766 struct iwl_channel_info *ch_info)
1767 {
1768 struct iwl3945_channel_power_info *power_info;
1769 int power_changed = 0;
1770 int i;
1771 const s8 *clip_pwrs;
1772 int power;
1773
1774 /* Get this chnlgrp's rate-to-max/clip-powers table */
1775 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1776
1777 /* Get this channel's rate-to-current-power settings table */
1778 power_info = ch_info->power_info;
1779
1780 /* update OFDM Txpower settings */
1781 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1782 i++, ++power_info) {
1783 int delta_idx;
1784
1785 /* limit new power to be no more than h/w capability */
1786 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1787 if (power == power_info->requested_power)
1788 continue;
1789
1790 /* find difference between old and new requested powers,
1791 * update base (non-temp-compensated) power index */
1792 delta_idx = (power - power_info->requested_power) * 2;
1793 power_info->base_power_index -= delta_idx;
1794
1795 /* save new requested power value */
1796 power_info->requested_power = power;
1797
1798 power_changed = 1;
1799 }
1800
1801 /* update CCK Txpower settings, based on OFDM 12M setting ...
1802 * ... all CCK power settings for a given channel are the *same*. */
1803 if (power_changed) {
1804 power =
1805 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1806 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1807
1808 /* do all CCK rates' iwl3945_channel_power_info structures */
1809 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1810 power_info->requested_power = power;
1811 power_info->base_power_index =
1812 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1813 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1814 ++power_info;
1815 }
1816 }
1817
1818 return 0;
1819 }
1820
1821 /**
1822 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1823 *
1824 * NOTE: Returned power limit may be less (but not more) than requested,
1825 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1826 * (no consideration for h/w clipping limitations).
1827 */
1828 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1829 {
1830 s8 max_power;
1831
1832 #if 0
1833 /* if we're using TGd limits, use lower of TGd or EEPROM */
1834 if (ch_info->tgd_data.max_power != 0)
1835 max_power = min(ch_info->tgd_data.max_power,
1836 ch_info->eeprom.max_power_avg);
1837
1838 /* else just use EEPROM limits */
1839 else
1840 #endif
1841 max_power = ch_info->eeprom.max_power_avg;
1842
1843 return min(max_power, ch_info->max_power_avg);
1844 }
1845
1846 /**
1847 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1848 *
1849 * Compensate txpower settings of *all* channels for temperature.
1850 * This only accounts for the difference between current temperature
1851 * and the factory calibration temperatures, and bases the new settings
1852 * on the channel's base_power_index.
1853 *
1854 * If RxOn is "associated", this sends the new Txpower to NIC!
1855 */
1856 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1857 {
1858 struct iwl_channel_info *ch_info = NULL;
1859 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1860 int delta_index;
1861 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1862 u8 a_band;
1863 u8 rate_index;
1864 u8 scan_tbl_index;
1865 u8 i;
1866 int ref_temp;
1867 int temperature = priv->temperature;
1868
1869 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1870 for (i = 0; i < priv->channel_count; i++) {
1871 ch_info = &priv->channel_info[i];
1872 a_band = is_channel_a_band(ch_info);
1873
1874 /* Get this chnlgrp's factory calibration temperature */
1875 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1876 temperature;
1877
1878 /* get power index adjustment based on current and factory
1879 * temps */
1880 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1881 ref_temp);
1882
1883 /* set tx power value for all rates, OFDM and CCK */
1884 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1885 rate_index++) {
1886 int power_idx =
1887 ch_info->power_info[rate_index].base_power_index;
1888
1889 /* temperature compensate */
1890 power_idx += delta_index;
1891
1892 /* stay within table range */
1893 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1894 ch_info->power_info[rate_index].
1895 power_table_index = (u8) power_idx;
1896 ch_info->power_info[rate_index].tpc =
1897 power_gain_table[a_band][power_idx];
1898 }
1899
1900 /* Get this chnlgrp's rate-to-max/clip-powers table */
1901 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1902
1903 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1904 for (scan_tbl_index = 0;
1905 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1906 s32 actual_index = (scan_tbl_index == 0) ?
1907 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1908 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1909 actual_index, clip_pwrs,
1910 ch_info, a_band);
1911 }
1912 }
1913
1914 /* send Txpower command for current channel to ucode */
1915 return priv->cfg->ops->lib->send_tx_power(priv);
1916 }
1917
1918 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1919 {
1920 struct iwl_channel_info *ch_info;
1921 s8 max_power;
1922 u8 a_band;
1923 u8 i;
1924
1925 if (priv->tx_power_user_lmt == power) {
1926 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1927 "limit: %ddBm.\n", power);
1928 return 0;
1929 }
1930
1931 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1932 priv->tx_power_user_lmt = power;
1933
1934 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1935
1936 for (i = 0; i < priv->channel_count; i++) {
1937 ch_info = &priv->channel_info[i];
1938 a_band = is_channel_a_band(ch_info);
1939
1940 /* find minimum power of all user and regulatory constraints
1941 * (does not consider h/w clipping limitations) */
1942 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1943 max_power = min(power, max_power);
1944 if (max_power != ch_info->curr_txpow) {
1945 ch_info->curr_txpow = max_power;
1946
1947 /* this considers the h/w clipping limitations */
1948 iwl3945_hw_reg_set_new_power(priv, ch_info);
1949 }
1950 }
1951
1952 /* update txpower settings for all channels,
1953 * send to NIC if associated. */
1954 is_temp_calib_needed(priv);
1955 iwl3945_hw_reg_comp_txpower_temp(priv);
1956
1957 return 0;
1958 }
1959
1960 /* will add 3945 channel switch cmd handling later */
1961 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1962 {
1963 return 0;
1964 }
1965
1966 /**
1967 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1968 *
1969 * -- reset periodic timer
1970 * -- see if temp has changed enough to warrant re-calibration ... if so:
1971 * -- correct coeffs for temp (can reset temp timer)
1972 * -- save this temp as "last",
1973 * -- send new set of gain settings to NIC
1974 * NOTE: This should continue working, even when we're not associated,
1975 * so we can keep our internal table of scan powers current. */
1976 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1977 {
1978 /* This will kick in the "brute force"
1979 * iwl3945_hw_reg_comp_txpower_temp() below */
1980 if (!is_temp_calib_needed(priv))
1981 goto reschedule;
1982
1983 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1984 * This is based *only* on current temperature,
1985 * ignoring any previous power measurements */
1986 iwl3945_hw_reg_comp_txpower_temp(priv);
1987
1988 reschedule:
1989 queue_delayed_work(priv->workqueue,
1990 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1991 }
1992
1993 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1994 {
1995 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1996 thermal_periodic.work);
1997
1998 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1999 return;
2000
2001 mutex_lock(&priv->mutex);
2002 iwl3945_reg_txpower_periodic(priv);
2003 mutex_unlock(&priv->mutex);
2004 }
2005
2006 /**
2007 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2008 * for the channel.
2009 *
2010 * This function is used when initializing channel-info structs.
2011 *
2012 * NOTE: These channel groups do *NOT* match the bands above!
2013 * These channel groups are based on factory-tested channels;
2014 * on A-band, EEPROM's "group frequency" entries represent the top
2015 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2016 */
2017 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2018 const struct iwl_channel_info *ch_info)
2019 {
2020 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2021 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2022 u8 group;
2023 u16 group_index = 0; /* based on factory calib frequencies */
2024 u8 grp_channel;
2025
2026 /* Find the group index for the channel ... don't use index 1(?) */
2027 if (is_channel_a_band(ch_info)) {
2028 for (group = 1; group < 5; group++) {
2029 grp_channel = ch_grp[group].group_channel;
2030 if (ch_info->channel <= grp_channel) {
2031 group_index = group;
2032 break;
2033 }
2034 }
2035 /* group 4 has a few channels *above* its factory cal freq */
2036 if (group == 5)
2037 group_index = 4;
2038 } else
2039 group_index = 0; /* 2.4 GHz, group 0 */
2040
2041 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2042 group_index);
2043 return group_index;
2044 }
2045
2046 /**
2047 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2048 *
2049 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2050 * into radio/DSP gain settings table for requested power.
2051 */
2052 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2053 s8 requested_power,
2054 s32 setting_index, s32 *new_index)
2055 {
2056 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2057 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2058 s32 index0, index1;
2059 s32 power = 2 * requested_power;
2060 s32 i;
2061 const struct iwl3945_eeprom_txpower_sample *samples;
2062 s32 gains0, gains1;
2063 s32 res;
2064 s32 denominator;
2065
2066 chnl_grp = &eeprom->groups[setting_index];
2067 samples = chnl_grp->samples;
2068 for (i = 0; i < 5; i++) {
2069 if (power == samples[i].power) {
2070 *new_index = samples[i].gain_index;
2071 return 0;
2072 }
2073 }
2074
2075 if (power > samples[1].power) {
2076 index0 = 0;
2077 index1 = 1;
2078 } else if (power > samples[2].power) {
2079 index0 = 1;
2080 index1 = 2;
2081 } else if (power > samples[3].power) {
2082 index0 = 2;
2083 index1 = 3;
2084 } else {
2085 index0 = 3;
2086 index1 = 4;
2087 }
2088
2089 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2090 if (denominator == 0)
2091 return -EINVAL;
2092 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2093 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2094 res = gains0 + (gains1 - gains0) *
2095 ((s32) power - (s32) samples[index0].power) / denominator +
2096 (1 << 18);
2097 *new_index = res >> 19;
2098 return 0;
2099 }
2100
2101 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2102 {
2103 u32 i;
2104 s32 rate_index;
2105 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2106 const struct iwl3945_eeprom_txpower_group *group;
2107
2108 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2109
2110 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2111 s8 *clip_pwrs; /* table of power levels for each rate */
2112 s8 satur_pwr; /* saturation power for each chnl group */
2113 group = &eeprom->groups[i];
2114
2115 /* sanity check on factory saturation power value */
2116 if (group->saturation_power < 40) {
2117 IWL_WARN(priv, "Error: saturation power is %d, "
2118 "less than minimum expected 40\n",
2119 group->saturation_power);
2120 return;
2121 }
2122
2123 /*
2124 * Derive requested power levels for each rate, based on
2125 * hardware capabilities (saturation power for band).
2126 * Basic value is 3dB down from saturation, with further
2127 * power reductions for highest 3 data rates. These
2128 * backoffs provide headroom for high rate modulation
2129 * power peaks, without too much distortion (clipping).
2130 */
2131 /* we'll fill in this array with h/w max power levels */
2132 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2133
2134 /* divide factory saturation power by 2 to find -3dB level */
2135 satur_pwr = (s8) (group->saturation_power >> 1);
2136
2137 /* fill in channel group's nominal powers for each rate */
2138 for (rate_index = 0;
2139 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2140 switch (rate_index) {
2141 case IWL_RATE_36M_INDEX_TABLE:
2142 if (i == 0) /* B/G */
2143 *clip_pwrs = satur_pwr;
2144 else /* A */
2145 *clip_pwrs = satur_pwr - 5;
2146 break;
2147 case IWL_RATE_48M_INDEX_TABLE:
2148 if (i == 0)
2149 *clip_pwrs = satur_pwr - 7;
2150 else
2151 *clip_pwrs = satur_pwr - 10;
2152 break;
2153 case IWL_RATE_54M_INDEX_TABLE:
2154 if (i == 0)
2155 *clip_pwrs = satur_pwr - 9;
2156 else
2157 *clip_pwrs = satur_pwr - 12;
2158 break;
2159 default:
2160 *clip_pwrs = satur_pwr;
2161 break;
2162 }
2163 }
2164 }
2165 }
2166
2167 /**
2168 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2169 *
2170 * Second pass (during init) to set up priv->channel_info
2171 *
2172 * Set up Tx-power settings in our channel info database for each VALID
2173 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2174 * and current temperature.
2175 *
2176 * Since this is based on current temperature (at init time), these values may
2177 * not be valid for very long, but it gives us a starting/default point,
2178 * and allows us to active (i.e. using Tx) scan.
2179 *
2180 * This does *not* write values to NIC, just sets up our internal table.
2181 */
2182 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2183 {
2184 struct iwl_channel_info *ch_info = NULL;
2185 struct iwl3945_channel_power_info *pwr_info;
2186 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2187 int delta_index;
2188 u8 rate_index;
2189 u8 scan_tbl_index;
2190 const s8 *clip_pwrs; /* array of power levels for each rate */
2191 u8 gain, dsp_atten;
2192 s8 power;
2193 u8 pwr_index, base_pwr_index, a_band;
2194 u8 i;
2195 int temperature;
2196
2197 /* save temperature reference,
2198 * so we can determine next time to calibrate */
2199 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2200 priv->last_temperature = temperature;
2201
2202 iwl3945_hw_reg_init_channel_groups(priv);
2203
2204 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2205 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2206 i++, ch_info++) {
2207 a_band = is_channel_a_band(ch_info);
2208 if (!is_channel_valid(ch_info))
2209 continue;
2210
2211 /* find this channel's channel group (*not* "band") index */
2212 ch_info->group_index =
2213 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2214
2215 /* Get this chnlgrp's rate->max/clip-powers table */
2216 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2217
2218 /* calculate power index *adjustment* value according to
2219 * diff between current temperature and factory temperature */
2220 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2221 eeprom->groups[ch_info->group_index].
2222 temperature);
2223
2224 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2225 ch_info->channel, delta_index, temperature +
2226 IWL_TEMP_CONVERT);
2227
2228 /* set tx power value for all OFDM rates */
2229 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2230 rate_index++) {
2231 s32 uninitialized_var(power_idx);
2232 int rc;
2233
2234 /* use channel group's clip-power table,
2235 * but don't exceed channel's max power */
2236 s8 pwr = min(ch_info->max_power_avg,
2237 clip_pwrs[rate_index]);
2238
2239 pwr_info = &ch_info->power_info[rate_index];
2240
2241 /* get base (i.e. at factory-measured temperature)
2242 * power table index for this rate's power */
2243 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2244 ch_info->group_index,
2245 &power_idx);
2246 if (rc) {
2247 IWL_ERR(priv, "Invalid power index\n");
2248 return rc;
2249 }
2250 pwr_info->base_power_index = (u8) power_idx;
2251
2252 /* temperature compensate */
2253 power_idx += delta_index;
2254
2255 /* stay within range of gain table */
2256 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2257
2258 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2259 pwr_info->requested_power = pwr;
2260 pwr_info->power_table_index = (u8) power_idx;
2261 pwr_info->tpc.tx_gain =
2262 power_gain_table[a_band][power_idx].tx_gain;
2263 pwr_info->tpc.dsp_atten =
2264 power_gain_table[a_band][power_idx].dsp_atten;
2265 }
2266
2267 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2268 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2269 power = pwr_info->requested_power +
2270 IWL_CCK_FROM_OFDM_POWER_DIFF;
2271 pwr_index = pwr_info->power_table_index +
2272 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2273 base_pwr_index = pwr_info->base_power_index +
2274 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2275
2276 /* stay within table range */
2277 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2278 gain = power_gain_table[a_band][pwr_index].tx_gain;
2279 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2280
2281 /* fill each CCK rate's iwl3945_channel_power_info structure
2282 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2283 * NOTE: CCK rates start at end of OFDM rates! */
2284 for (rate_index = 0;
2285 rate_index < IWL_CCK_RATES; rate_index++) {
2286 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2287 pwr_info->requested_power = power;
2288 pwr_info->power_table_index = pwr_index;
2289 pwr_info->base_power_index = base_pwr_index;
2290 pwr_info->tpc.tx_gain = gain;
2291 pwr_info->tpc.dsp_atten = dsp_atten;
2292 }
2293
2294 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2295 for (scan_tbl_index = 0;
2296 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2297 s32 actual_index = (scan_tbl_index == 0) ?
2298 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2299 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2300 actual_index, clip_pwrs, ch_info, a_band);
2301 }
2302 }
2303
2304 return 0;
2305 }
2306
2307 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2308 {
2309 int rc;
2310 unsigned long flags;
2311
2312 spin_lock_irqsave(&priv->lock, flags);
2313 rc = iwl_grab_nic_access(priv);
2314 if (rc) {
2315 spin_unlock_irqrestore(&priv->lock, flags);
2316 return rc;
2317 }
2318
2319 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2320 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2321 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2322 if (rc < 0)
2323 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2324
2325 iwl_release_nic_access(priv);
2326 spin_unlock_irqrestore(&priv->lock, flags);
2327
2328 return 0;
2329 }
2330
2331 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2332 {
2333 int rc;
2334 unsigned long flags;
2335 int txq_id = txq->q.id;
2336
2337 struct iwl3945_shared *shared_data = priv->shared_virt;
2338
2339 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2340
2341 spin_lock_irqsave(&priv->lock, flags);
2342 rc = iwl_grab_nic_access(priv);
2343 if (rc) {
2344 spin_unlock_irqrestore(&priv->lock, flags);
2345 return rc;
2346 }
2347 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2348 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2349
2350 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2351 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2352 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2353 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2354 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2355 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2356 iwl_release_nic_access(priv);
2357
2358 /* fake read to flush all prev. writes */
2359 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2360 spin_unlock_irqrestore(&priv->lock, flags);
2361
2362 return 0;
2363 }
2364
2365 /*
2366 * HCMD utils
2367 */
2368 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2369 {
2370 switch (cmd_id) {
2371 case REPLY_RXON:
2372 return sizeof(struct iwl3945_rxon_cmd);
2373 case POWER_TABLE_CMD:
2374 return sizeof(struct iwl3945_powertable_cmd);
2375 default:
2376 return len;
2377 }
2378 }
2379
2380 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2381 {
2382 u16 size = (u16)sizeof(struct iwl3945_addsta_cmd);
2383 memcpy(data, cmd, size);
2384 return size;
2385 }
2386
2387 /**
2388 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2389 */
2390 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2391 {
2392 int rc, i, index, prev_index;
2393 struct iwl3945_rate_scaling_cmd rate_cmd = {
2394 .reserved = {0, 0, 0},
2395 };
2396 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2397
2398 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2399 index = iwl3945_rates[i].table_rs_index;
2400
2401 table[index].rate_n_flags =
2402 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2403 table[index].try_cnt = priv->retry_rate;
2404 prev_index = iwl3945_get_prev_ieee_rate(i);
2405 table[index].next_rate_index =
2406 iwl3945_rates[prev_index].table_rs_index;
2407 }
2408
2409 switch (priv->band) {
2410 case IEEE80211_BAND_5GHZ:
2411 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2412 /* If one of the following CCK rates is used,
2413 * have it fall back to the 6M OFDM rate */
2414 for (i = IWL_RATE_1M_INDEX_TABLE;
2415 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2416 table[i].next_rate_index =
2417 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2418
2419 /* Don't fall back to CCK rates */
2420 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2421 IWL_RATE_9M_INDEX_TABLE;
2422
2423 /* Don't drop out of OFDM rates */
2424 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2425 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2426 break;
2427
2428 case IEEE80211_BAND_2GHZ:
2429 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2430 /* If an OFDM rate is used, have it fall back to the
2431 * 1M CCK rates */
2432
2433 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2434 iwl_is_associated(priv)) {
2435
2436 index = IWL_FIRST_CCK_RATE;
2437 for (i = IWL_RATE_6M_INDEX_TABLE;
2438 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2439 table[i].next_rate_index =
2440 iwl3945_rates[index].table_rs_index;
2441
2442 index = IWL_RATE_11M_INDEX_TABLE;
2443 /* CCK shouldn't fall back to OFDM... */
2444 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2445 }
2446 break;
2447
2448 default:
2449 WARN_ON(1);
2450 break;
2451 }
2452
2453 /* Update the rate scaling for control frame Tx */
2454 rate_cmd.table_id = 0;
2455 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2456 &rate_cmd);
2457 if (rc)
2458 return rc;
2459
2460 /* Update the rate scaling for data frame Tx */
2461 rate_cmd.table_id = 1;
2462 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2463 &rate_cmd);
2464 }
2465
2466 /* Called when initializing driver */
2467 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2468 {
2469 memset((void *)&priv->hw_params, 0,
2470 sizeof(struct iwl_hw_params));
2471
2472 priv->shared_virt =
2473 pci_alloc_consistent(priv->pci_dev,
2474 sizeof(struct iwl3945_shared),
2475 &priv->shared_phys);
2476
2477 if (!priv->shared_virt) {
2478 IWL_ERR(priv, "failed to allocate pci memory\n");
2479 mutex_unlock(&priv->mutex);
2480 return -ENOMEM;
2481 }
2482
2483 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2484 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2485 priv->hw_params.max_pkt_size = 2342;
2486 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2487 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2488 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2489 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2490
2491 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2492
2493 return 0;
2494 }
2495
2496 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2497 struct iwl3945_frame *frame, u8 rate)
2498 {
2499 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2500 unsigned int frame_size;
2501
2502 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2503 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2504
2505 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2506 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2507
2508 frame_size = iwl3945_fill_beacon_frame(priv,
2509 tx_beacon_cmd->frame,
2510 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2511
2512 BUG_ON(frame_size > MAX_MPDU_SIZE);
2513 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2514
2515 tx_beacon_cmd->tx.rate = rate;
2516 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2517 TX_CMD_FLG_TSF_MSK);
2518
2519 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2520 tx_beacon_cmd->tx.supp_rates[0] =
2521 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2522
2523 tx_beacon_cmd->tx.supp_rates[1] =
2524 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2525
2526 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2527 }
2528
2529 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2530 {
2531 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2532 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2533 }
2534
2535 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2536 {
2537 INIT_DELAYED_WORK(&priv->thermal_periodic,
2538 iwl3945_bg_reg_txpower_periodic);
2539 }
2540
2541 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2542 {
2543 cancel_delayed_work(&priv->thermal_periodic);
2544 }
2545
2546 /* check contents of special bootstrap uCode SRAM */
2547 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2548 {
2549 __le32 *image = priv->ucode_boot.v_addr;
2550 u32 len = priv->ucode_boot.len;
2551 u32 reg;
2552 u32 val;
2553
2554 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2555
2556 /* verify BSM SRAM contents */
2557 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2558 for (reg = BSM_SRAM_LOWER_BOUND;
2559 reg < BSM_SRAM_LOWER_BOUND + len;
2560 reg += sizeof(u32), image++) {
2561 val = iwl_read_prph(priv, reg);
2562 if (val != le32_to_cpu(*image)) {
2563 IWL_ERR(priv, "BSM uCode verification failed at "
2564 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2565 BSM_SRAM_LOWER_BOUND,
2566 reg - BSM_SRAM_LOWER_BOUND, len,
2567 val, le32_to_cpu(*image));
2568 return -EIO;
2569 }
2570 }
2571
2572 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2573
2574 return 0;
2575 }
2576
2577
2578 /******************************************************************************
2579 *
2580 * EEPROM related functions
2581 *
2582 ******************************************************************************/
2583
2584 /*
2585 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2586 * embedded controller) as EEPROM reader; each read is a series of pulses
2587 * to/from the EEPROM chip, not a single event, so even reads could conflict
2588 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2589 * simply claims ownership, which should be safe when this function is called
2590 * (i.e. before loading uCode!).
2591 */
2592 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2593 {
2594 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2595 return 0;
2596 }
2597
2598
2599 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2600 {
2601 return;
2602 }
2603
2604 /**
2605 * iwl3945_load_bsm - Load bootstrap instructions
2606 *
2607 * BSM operation:
2608 *
2609 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2610 * in special SRAM that does not power down during RFKILL. When powering back
2611 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2612 * the bootstrap program into the on-board processor, and starts it.
2613 *
2614 * The bootstrap program loads (via DMA) instructions and data for a new
2615 * program from host DRAM locations indicated by the host driver in the
2616 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2617 * automatically.
2618 *
2619 * When initializing the NIC, the host driver points the BSM to the
2620 * "initialize" uCode image. This uCode sets up some internal data, then
2621 * notifies host via "initialize alive" that it is complete.
2622 *
2623 * The host then replaces the BSM_DRAM_* pointer values to point to the
2624 * normal runtime uCode instructions and a backup uCode data cache buffer
2625 * (filled initially with starting data values for the on-board processor),
2626 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2627 * which begins normal operation.
2628 *
2629 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2630 * the backup data cache in DRAM before SRAM is powered down.
2631 *
2632 * When powering back up, the BSM loads the bootstrap program. This reloads
2633 * the runtime uCode instructions and the backup data cache into SRAM,
2634 * and re-launches the runtime uCode from where it left off.
2635 */
2636 static int iwl3945_load_bsm(struct iwl_priv *priv)
2637 {
2638 __le32 *image = priv->ucode_boot.v_addr;
2639 u32 len = priv->ucode_boot.len;
2640 dma_addr_t pinst;
2641 dma_addr_t pdata;
2642 u32 inst_len;
2643 u32 data_len;
2644 int rc;
2645 int i;
2646 u32 done;
2647 u32 reg_offset;
2648
2649 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2650
2651 /* make sure bootstrap program is no larger than BSM's SRAM size */
2652 if (len > IWL39_MAX_BSM_SIZE)
2653 return -EINVAL;
2654
2655 /* Tell bootstrap uCode where to find the "Initialize" uCode
2656 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2657 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2658 * after the "initialize" uCode has run, to point to
2659 * runtime/protocol instructions and backup data cache. */
2660 pinst = priv->ucode_init.p_addr;
2661 pdata = priv->ucode_init_data.p_addr;
2662 inst_len = priv->ucode_init.len;
2663 data_len = priv->ucode_init_data.len;
2664
2665 rc = iwl_grab_nic_access(priv);
2666 if (rc)
2667 return rc;
2668
2669 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2670 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2671 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2672 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2673
2674 /* Fill BSM memory with bootstrap instructions */
2675 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2676 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2677 reg_offset += sizeof(u32), image++)
2678 _iwl_write_prph(priv, reg_offset,
2679 le32_to_cpu(*image));
2680
2681 rc = iwl3945_verify_bsm(priv);
2682 if (rc) {
2683 iwl_release_nic_access(priv);
2684 return rc;
2685 }
2686
2687 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2688 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2689 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2690 IWL39_RTC_INST_LOWER_BOUND);
2691 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2692
2693 /* Load bootstrap code into instruction SRAM now,
2694 * to prepare to load "initialize" uCode */
2695 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2696 BSM_WR_CTRL_REG_BIT_START);
2697
2698 /* Wait for load of bootstrap uCode to finish */
2699 for (i = 0; i < 100; i++) {
2700 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2701 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2702 break;
2703 udelay(10);
2704 }
2705 if (i < 100)
2706 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2707 else {
2708 IWL_ERR(priv, "BSM write did not complete!\n");
2709 return -EIO;
2710 }
2711
2712 /* Enable future boot loads whenever power management unit triggers it
2713 * (e.g. when powering back up after power-save shutdown) */
2714 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2715 BSM_WR_CTRL_REG_BIT_START_EN);
2716
2717 iwl_release_nic_access(priv);
2718
2719 return 0;
2720 }
2721
2722 static struct iwl_lib_ops iwl3945_lib = {
2723 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2724 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2725 .txq_init = iwl3945_hw_tx_queue_init,
2726 .load_ucode = iwl3945_load_bsm,
2727 .apm_ops = {
2728 .init = iwl3945_apm_init,
2729 .reset = iwl3945_apm_reset,
2730 .stop = iwl3945_apm_stop,
2731 .config = iwl3945_nic_config,
2732 .set_pwr_src = iwl3945_set_pwr_src,
2733 },
2734 .eeprom_ops = {
2735 .regulatory_bands = {
2736 EEPROM_REGULATORY_BAND_1_CHANNELS,
2737 EEPROM_REGULATORY_BAND_2_CHANNELS,
2738 EEPROM_REGULATORY_BAND_3_CHANNELS,
2739 EEPROM_REGULATORY_BAND_4_CHANNELS,
2740 EEPROM_REGULATORY_BAND_5_CHANNELS,
2741 EEPROM_REGULATORY_BAND_NO_FAT,
2742 EEPROM_REGULATORY_BAND_NO_FAT,
2743 },
2744 .verify_signature = iwlcore_eeprom_verify_signature,
2745 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2746 .release_semaphore = iwl3945_eeprom_release_semaphore,
2747 .query_addr = iwlcore_eeprom_query_addr,
2748 },
2749 .send_tx_power = iwl3945_send_tx_power,
2750 };
2751
2752 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2753 .get_hcmd_size = iwl3945_get_hcmd_size,
2754 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2755 };
2756
2757 static struct iwl_ops iwl3945_ops = {
2758 .lib = &iwl3945_lib,
2759 .utils = &iwl3945_hcmd_utils,
2760 };
2761
2762 static struct iwl_cfg iwl3945_bg_cfg = {
2763 .name = "3945BG",
2764 .fw_name_pre = IWL3945_FW_PRE,
2765 .ucode_api_max = IWL3945_UCODE_API_MAX,
2766 .ucode_api_min = IWL3945_UCODE_API_MIN,
2767 .sku = IWL_SKU_G,
2768 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2769 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2770 .ops = &iwl3945_ops,
2771 .mod_params = &iwl3945_mod_params
2772 };
2773
2774 static struct iwl_cfg iwl3945_abg_cfg = {
2775 .name = "3945ABG",
2776 .fw_name_pre = IWL3945_FW_PRE,
2777 .ucode_api_max = IWL3945_UCODE_API_MAX,
2778 .ucode_api_min = IWL3945_UCODE_API_MIN,
2779 .sku = IWL_SKU_A|IWL_SKU_G,
2780 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2781 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2782 .ops = &iwl3945_ops,
2783 .mod_params = &iwl3945_mod_params
2784 };
2785
2786 struct pci_device_id iwl3945_hw_card_ids[] = {
2787 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2788 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2789 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2790 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2791 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2792 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2793 {0}
2794 };
2795
2796 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux with added FPC-III support