| blob | 1c9b0ccc2172e8480da768e953550f57b83dfd24 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * PowerPC version
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 *
13 * This file contains the system call entry code, context switch
14 * code, and exception/interrupt return code for PowerPC.
15 */
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/sys.h>
20 #include <linux/threads.h>
21 #include <asm/reg.h>
22 #include <asm/page.h>
23 #include <asm/mmu.h>
24 #include <asm/cputable.h>
25 #include <asm/thread_info.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/ptrace.h>
30 #include <asm/export.h>
31 #include <asm/feature-fixups.h>
32 #include <asm/barrier.h>
33 #include <asm/kup.h>
34 #include <asm/bug.h>
36 #include "head_32.h"
38 /*
39 * powerpc relies on return from interrupt/syscall being context synchronising
40 * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional
41 * synchronisation instructions.
42 */
44 /*
45 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
46 * fit into one page in order to not encounter a TLB miss between the
47 * modification of srr0/srr1 and the associated rfi.
48 */
49 .align 12
51 #ifdef CONFIG_BOOKE
52 .globl mcheck_transfer_to_handler
53 mcheck_transfer_to_handler:
54 mfspr r0,SPRN_DSRR0
55 stw r0,_DSRR0(r11)
56 mfspr r0,SPRN_DSRR1
57 stw r0,_DSRR1(r11)
58 /* fall through */
59 _ASM_NOKPROBE_SYMBOL(mcheck_transfer_to_handler)
61 .globl debug_transfer_to_handler
62 debug_transfer_to_handler:
63 mfspr r0,SPRN_CSRR0
64 stw r0,_CSRR0(r11)
65 mfspr r0,SPRN_CSRR1
66 stw r0,_CSRR1(r11)
67 /* fall through */
68 _ASM_NOKPROBE_SYMBOL(debug_transfer_to_handler)
70 .globl crit_transfer_to_handler
71 crit_transfer_to_handler:
72 #ifdef CONFIG_PPC_BOOK3E_MMU
73 mfspr r0,SPRN_MAS0
74 stw r0,MAS0(r11)
75 mfspr r0,SPRN_MAS1
76 stw r0,MAS1(r11)
77 mfspr r0,SPRN_MAS2
78 stw r0,MAS2(r11)
79 mfspr r0,SPRN_MAS3
80 stw r0,MAS3(r11)
81 mfspr r0,SPRN_MAS6
82 stw r0,MAS6(r11)
83 #ifdef CONFIG_PHYS_64BIT
84 mfspr r0,SPRN_MAS7
85 stw r0,MAS7(r11)
86 #endif /* CONFIG_PHYS_64BIT */
87 #endif /* CONFIG_PPC_BOOK3E_MMU */
88 #ifdef CONFIG_44x
89 mfspr r0,SPRN_MMUCR
90 stw r0,MMUCR(r11)
91 #endif
92 mfspr r0,SPRN_SRR0
93 stw r0,_SRR0(r11)
94 mfspr r0,SPRN_SRR1
95 stw r0,_SRR1(r11)
97 /* set the stack limit to the current stack */
98 mfspr r8,SPRN_SPRG_THREAD
99 lwz r0,KSP_LIMIT(r8)
100 stw r0,SAVED_KSP_LIMIT(r11)
101 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
102 stw r0,KSP_LIMIT(r8)
103 /* fall through */
104 _ASM_NOKPROBE_SYMBOL(crit_transfer_to_handler)
105 #endif
107 #ifdef CONFIG_40x
108 .globl crit_transfer_to_handler
109 crit_transfer_to_handler:
110 lwz r0,crit_r10@l(0)
111 stw r0,GPR10(r11)
112 lwz r0,crit_r11@l(0)
113 stw r0,GPR11(r11)
114 mfspr r0,SPRN_SRR0
115 stw r0,crit_srr0@l(0)
116 mfspr r0,SPRN_SRR1
117 stw r0,crit_srr1@l(0)
119 /* set the stack limit to the current stack */
120 mfspr r8,SPRN_SPRG_THREAD
121 lwz r0,KSP_LIMIT(r8)
122 stw r0,saved_ksp_limit@l(0)
123 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
124 stw r0,KSP_LIMIT(r8)
125 /* fall through */
126 _ASM_NOKPROBE_SYMBOL(crit_transfer_to_handler)
127 #endif
129 /*
130 * This code finishes saving the registers to the exception frame
131 * and jumps to the appropriate handler for the exception, turning
132 * on address translation.
133 * Note that we rely on the caller having set cr0.eq iff the exception
134 * occurred in kernel mode (i.e. MSR:PR = 0).
135 */
136 .globl transfer_to_handler_full
137 transfer_to_handler_full:
138 SAVE_NVGPRS(r11)
139 _ASM_NOKPROBE_SYMBOL(transfer_to_handler_full)
140 /* fall through */
142 .globl transfer_to_handler
143 transfer_to_handler:
144 stw r2,GPR2(r11)
145 stw r12,_NIP(r11)
146 stw r9,_MSR(r11)
147 andi. r2,r9,MSR_PR
148 mfctr r12
149 mfspr r2,SPRN_XER
150 stw r12,_CTR(r11)
151 stw r2,_XER(r11)
152 mfspr r12,SPRN_SPRG_THREAD
153 tovirt_vmstack r12, r12
154 beq 2f /* if from user, fix up THREAD.regs */
155 addi r2, r12, -THREAD
156 addi r11,r1,STACK_FRAME_OVERHEAD
157 stw r11,PT_REGS(r12)
158 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
159 /* Check to see if the dbcr0 register is set up to debug. Use the
160 internal debug mode bit to do this. */
161 lwz r12,THREAD_DBCR0(r12)
162 andis. r12,r12,DBCR0_IDM@h
163 #endif
164 ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
165 #ifdef CONFIG_PPC_BOOK3S_32
166 kuep_lock r11, r12
167 #endif
168 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
169 beq+ 3f
170 /* From user and task is ptraced - load up global dbcr0 */
171 li r12,-1 /* clear all pending debug events */
172 mtspr SPRN_DBSR,r12
173 lis r11,global_dbcr0@ha
174 tophys(r11,r11)
175 addi r11,r11,global_dbcr0@l
176 #ifdef CONFIG_SMP
177 lwz r9,TASK_CPU(r2)
178 slwi r9,r9,3
179 add r11,r11,r9
180 #endif
181 lwz r12,0(r11)
182 mtspr SPRN_DBCR0,r12
183 lwz r12,4(r11)
184 addi r12,r12,-1
185 stw r12,4(r11)
186 #endif
188 b 3f
190 2: /* if from kernel, check interrupted DOZE/NAP mode and
191 * check for stack overflow
192 */
193 kuap_save_and_lock r11, r12, r9, r2, r6
194 addi r2, r12, -THREAD
195 #ifndef CONFIG_VMAP_STACK
196 lwz r9,KSP_LIMIT(r12)
197 cmplw r1,r9 /* if r1 <= ksp_limit */
198 ble- stack_ovf /* then the kernel stack overflowed */
199 #endif
200 5:
201 #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
202 lwz r12,TI_LOCAL_FLAGS(r2)
203 mtcrf 0x01,r12
204 bt- 31-TLF_NAPPING,4f
205 bt- 31-TLF_SLEEPING,7f
206 #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */
207 .globl transfer_to_handler_cont
208 transfer_to_handler_cont:
209 3:
210 mflr r9
211 tovirt_novmstack r2, r2 /* set r2 to current */
212 tovirt_vmstack r9, r9
213 lwz r11,0(r9) /* virtual address of handler */
214 lwz r9,4(r9) /* where to go when done */
215 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
216 mtspr SPRN_NRI, r0
217 #endif
218 #ifdef CONFIG_TRACE_IRQFLAGS
219 /*
220 * When tracing IRQ state (lockdep) we enable the MMU before we call
221 * the IRQ tracing functions as they might access vmalloc space or
222 * perform IOs for console output.
223 *
224 * To speed up the syscall path where interrupts stay on, let's check
225 * first if we are changing the MSR value at all.
226 */
227 tophys_novmstack r12, r1
228 lwz r12,_MSR(r12)
229 andi. r12,r12,MSR_EE
230 bne 1f
232 /* MSR isn't changing, just transition directly */
233 #endif
234 mtspr SPRN_SRR0,r11
235 mtspr SPRN_SRR1,r10
236 mtlr r9
237 rfi /* jump to handler, enable MMU */
238 #ifdef CONFIG_40x
239 b . /* Prevent prefetch past rfi */
240 #endif
242 #if defined (CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
243 4: rlwinm r12,r12,0,~_TLF_NAPPING
244 stw r12,TI_LOCAL_FLAGS(r2)
245 b power_save_ppc32_restore
247 7: rlwinm r12,r12,0,~_TLF_SLEEPING
248 stw r12,TI_LOCAL_FLAGS(r2)
249 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
250 rlwinm r9,r9,0,~MSR_EE
251 lwz r12,_LINK(r11) /* and return to address in LR */
252 kuap_restore r11, r2, r3, r4, r5
253 lwz r2, GPR2(r11)
254 b fast_exception_return
255 #endif
256 _ASM_NOKPROBE_SYMBOL(transfer_to_handler)
257 _ASM_NOKPROBE_SYMBOL(transfer_to_handler_cont)
259 #ifdef CONFIG_TRACE_IRQFLAGS
260 1: /* MSR is changing, re-enable MMU so we can notify lockdep. We need to
261 * keep interrupts disabled at this point otherwise we might risk
262 * taking an interrupt before we tell lockdep they are enabled.
263 */
264 lis r12,reenable_mmu@h
265 ori r12,r12,reenable_mmu@l
266 LOAD_REG_IMMEDIATE(r0, MSR_KERNEL)
267 mtspr SPRN_SRR0,r12
268 mtspr SPRN_SRR1,r0
269 rfi
270 #ifdef CONFIG_40x
271 b . /* Prevent prefetch past rfi */
272 #endif
274 reenable_mmu:
275 /*
276 * We save a bunch of GPRs,
277 * r3 can be different from GPR3(r1) at this point, r9 and r11
278 * contains the old MSR and handler address respectively,
279 * r4 & r5 can contain page fault arguments that need to be passed
280 * along as well. r0, r6-r8, r12, CCR, CTR, XER etc... are left
281 * clobbered as they aren't useful past this point.
282 */
284 stwu r1,-32(r1)
285 stw r9,8(r1)
286 stw r11,12(r1)
287 stw r3,16(r1)
288 stw r4,20(r1)
289 stw r5,24(r1)
291 /* If we are disabling interrupts (normal case), simply log it with
292 * lockdep
293 */
294 1: bl trace_hardirqs_off
295 lwz r5,24(r1)
296 lwz r4,20(r1)
297 lwz r3,16(r1)
298 lwz r11,12(r1)
299 lwz r9,8(r1)
300 addi r1,r1,32
301 mtctr r11
302 mtlr r9
303 bctr /* jump to handler */
304 #endif /* CONFIG_TRACE_IRQFLAGS */
306 #ifndef CONFIG_VMAP_STACK
307 /*
308 * On kernel stack overflow, load up an initial stack pointer
309 * and call StackOverflow(regs), which should not return.
310 */
311 stack_ovf:
312 /* sometimes we use a statically-allocated stack, which is OK. */
313 lis r12,_end@h
314 ori r12,r12,_end@l
315 cmplw r1,r12
316 ble 5b /* r1 <= &_end is OK */
317 SAVE_NVGPRS(r11)
318 addi r3,r1,STACK_FRAME_OVERHEAD
319 lis r1,init_thread_union@ha
320 addi r1,r1,init_thread_union@l
321 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
322 lis r9,StackOverflow@ha
323 addi r9,r9,StackOverflow@l
324 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
325 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
326 mtspr SPRN_NRI, r0
327 #endif
328 mtspr SPRN_SRR0,r9
329 mtspr SPRN_SRR1,r10
330 rfi
331 #ifdef CONFIG_40x
332 b . /* Prevent prefetch past rfi */
333 #endif
334 _ASM_NOKPROBE_SYMBOL(stack_ovf)
335 #endif
337 #ifdef CONFIG_TRACE_IRQFLAGS
338 trace_syscall_entry_irq_off:
339 /*
340 * Syscall shouldn't happen while interrupts are disabled,
341 * so let's do a warning here.
342 */
343 0: trap
344 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
345 bl trace_hardirqs_on
347 /* Now enable for real */
348 LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE)
349 mtmsr r10
351 REST_GPR(0, r1)
352 REST_4GPRS(3, r1)
353 REST_2GPRS(7, r1)
354 b DoSyscall
355 #endif /* CONFIG_TRACE_IRQFLAGS */
357 .globl transfer_to_syscall
358 transfer_to_syscall:
359 #ifdef CONFIG_TRACE_IRQFLAGS
360 andi. r12,r9,MSR_EE
361 beq- trace_syscall_entry_irq_off
362 #endif /* CONFIG_TRACE_IRQFLAGS */
364 /*
365 * Handle a system call.
366 */
367 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
368 .stabs "entry_32.S",N_SO,0,0,0f
369 0:
371 _GLOBAL(DoSyscall)
372 stw r3,ORIG_GPR3(r1)
373 li r12,0
374 stw r12,RESULT(r1)
375 #ifdef CONFIG_TRACE_IRQFLAGS
376 /* Make sure interrupts are enabled */
377 mfmsr r11
378 andi. r12,r11,MSR_EE
379 /* We came in with interrupts disabled, we WARN and mark them enabled
380 * for lockdep now */
381 0: tweqi r12, 0
382 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
383 #endif /* CONFIG_TRACE_IRQFLAGS */
384 lwz r11,TI_FLAGS(r2)
385 andi. r11,r11,_TIF_SYSCALL_DOTRACE
386 bne- syscall_dotrace
387 syscall_dotrace_cont:
388 cmplwi 0,r0,NR_syscalls
389 lis r10,sys_call_table@h
390 ori r10,r10,sys_call_table@l
391 slwi r0,r0,2
392 bge- 66f
394 barrier_nospec_asm
395 /*
396 * Prevent the load of the handler below (based on the user-passed
397 * system call number) being speculatively executed until the test
398 * against NR_syscalls and branch to .66f above has
399 * committed.
400 */
402 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
403 mtlr r10
404 addi r9,r1,STACK_FRAME_OVERHEAD
405 PPC440EP_ERR42
406 blrl /* Call handler */
407 .globl ret_from_syscall
408 ret_from_syscall:
409 #ifdef CONFIG_DEBUG_RSEQ
410 /* Check whether the syscall is issued inside a restartable sequence */
411 stw r3,GPR3(r1)
412 addi r3,r1,STACK_FRAME_OVERHEAD
413 bl rseq_syscall
414 lwz r3,GPR3(r1)
415 #endif
416 mr r6,r3
417 /* disable interrupts so current_thread_info()->flags can't change */
418 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) /* doesn't include MSR_EE */
419 /* Note: We don't bother telling lockdep about it */
420 mtmsr r10
421 lwz r9,TI_FLAGS(r2)
422 li r8,-MAX_ERRNO
423 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
424 bne- syscall_exit_work
425 cmplw 0,r3,r8
426 blt+ syscall_exit_cont
427 lwz r11,_CCR(r1) /* Load CR */
428 neg r3,r3
429 oris r11,r11,0x1000 /* Set SO bit in CR */
430 stw r11,_CCR(r1)
431 syscall_exit_cont:
432 lwz r8,_MSR(r1)
433 #ifdef CONFIG_TRACE_IRQFLAGS
434 /* If we are going to return from the syscall with interrupts
435 * off, we trace that here. It shouldn't normally happen.
436 */
437 andi. r10,r8,MSR_EE
438 bne+ 1f
439 stw r3,GPR3(r1)
440 bl trace_hardirqs_off
441 lwz r3,GPR3(r1)
442 1:
443 #endif /* CONFIG_TRACE_IRQFLAGS */
444 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
445 /* If the process has its own DBCR0 value, load it up. The internal
446 debug mode bit tells us that dbcr0 should be loaded. */
447 lwz r0,THREAD+THREAD_DBCR0(r2)
448 andis. r10,r0,DBCR0_IDM@h
449 bnel- load_dbcr0
450 #endif
451 #ifdef CONFIG_PPC_47x
452 lis r4,icache_44x_need_flush@ha
453 lwz r5,icache_44x_need_flush@l(r4)
454 cmplwi cr0,r5,0
455 bne- 2f
456 #endif /* CONFIG_PPC_47x */
457 1:
458 BEGIN_FTR_SECTION
459 lwarx r7,0,r1
460 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
461 stwcx. r0,0,r1 /* to clear the reservation */
462 ACCOUNT_CPU_USER_EXIT(r2, r5, r7)
463 #ifdef CONFIG_PPC_BOOK3S_32
464 kuep_unlock r5, r7
465 #endif
466 kuap_check r2, r4
467 lwz r4,_LINK(r1)
468 lwz r5,_CCR(r1)
469 mtlr r4
470 mtcr r5
471 lwz r7,_NIP(r1)
472 lwz r2,GPR2(r1)
473 lwz r1,GPR1(r1)
474 syscall_exit_finish:
475 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
476 mtspr SPRN_NRI, r0
477 #endif
478 mtspr SPRN_SRR0,r7
479 mtspr SPRN_SRR1,r8
480 rfi
481 #ifdef CONFIG_40x
482 b . /* Prevent prefetch past rfi */
483 #endif
484 _ASM_NOKPROBE_SYMBOL(syscall_exit_finish)
485 #ifdef CONFIG_44x
486 2: li r7,0
487 iccci r0,r0
488 stw r7,icache_44x_need_flush@l(r4)
489 b 1b
490 #endif /* CONFIG_44x */
492 66: li r3,-ENOSYS
493 b ret_from_syscall
495 .globl ret_from_fork
496 ret_from_fork:
497 REST_NVGPRS(r1)
498 bl schedule_tail
499 li r3,0
500 b ret_from_syscall
502 .globl ret_from_kernel_thread
503 ret_from_kernel_thread:
504 REST_NVGPRS(r1)
505 bl schedule_tail
506 mtlr r14
507 mr r3,r15
508 PPC440EP_ERR42
509 blrl
510 li r3,0
511 b ret_from_syscall
513 /* Traced system call support */
514 syscall_dotrace:
515 SAVE_NVGPRS(r1)
516 li r0,0xc00
517 stw r0,_TRAP(r1)
518 addi r3,r1,STACK_FRAME_OVERHEAD
519 bl do_syscall_trace_enter
520 /*
521 * Restore argument registers possibly just changed.
522 * We use the return value of do_syscall_trace_enter
523 * for call number to look up in the table (r0).
524 */
525 mr r0,r3
526 lwz r3,GPR3(r1)
527 lwz r4,GPR4(r1)
528 lwz r5,GPR5(r1)
529 lwz r6,GPR6(r1)
530 lwz r7,GPR7(r1)
531 lwz r8,GPR8(r1)
532 REST_NVGPRS(r1)
534 cmplwi r0,NR_syscalls
535 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
536 bge- ret_from_syscall
537 b syscall_dotrace_cont
539 syscall_exit_work:
540 andi. r0,r9,_TIF_RESTOREALL
541 beq+ 0f
542 REST_NVGPRS(r1)
543 b 2f
544 0: cmplw 0,r3,r8
545 blt+ 1f
546 andi. r0,r9,_TIF_NOERROR
547 bne- 1f
548 lwz r11,_CCR(r1) /* Load CR */
549 neg r3,r3
550 oris r11,r11,0x1000 /* Set SO bit in CR */
551 stw r11,_CCR(r1)
553 1: stw r6,RESULT(r1) /* Save result */
554 stw r3,GPR3(r1) /* Update return value */
555 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
556 beq 4f
558 /* Clear per-syscall TIF flags if any are set. */
560 li r11,_TIF_PERSYSCALL_MASK
561 addi r12,r2,TI_FLAGS
562 3: lwarx r8,0,r12
563 andc r8,r8,r11
564 stwcx. r8,0,r12
565 bne- 3b
567 4: /* Anything which requires enabling interrupts? */
568 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
569 beq ret_from_except
571 /* Re-enable interrupts. There is no need to trace that with
572 * lockdep as we are supposed to have IRQs on at this point
573 */
574 ori r10,r10,MSR_EE
575 mtmsr r10
577 /* Save NVGPRS if they're not saved already */
578 lwz r4,_TRAP(r1)
579 andi. r4,r4,1
580 beq 5f
581 SAVE_NVGPRS(r1)
582 li r4,0xc00
583 stw r4,_TRAP(r1)
584 5:
585 addi r3,r1,STACK_FRAME_OVERHEAD
586 bl do_syscall_trace_leave
587 b ret_from_except_full
589 /*
590 * System call was called from kernel. We get here with SRR1 in r9.
591 * Mark the exception as recoverable once we have retrieved SRR0,
592 * trap a warning and return ENOSYS with CR[SO] set.
593 */
594 .globl ret_from_kernel_syscall
595 ret_from_kernel_syscall:
596 mfspr r9, SPRN_SRR0
597 mfspr r10, SPRN_SRR1
598 #if !defined(CONFIG_4xx) && !defined(CONFIG_BOOKE)
599 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_IR|MSR_DR))
600 mtmsr r11
601 #endif
603 0: trap
604 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
606 li r3, ENOSYS
607 crset so
608 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
609 mtspr SPRN_NRI, r0
610 #endif
611 mtspr SPRN_SRR0, r9
612 mtspr SPRN_SRR1, r10
613 rfi
614 #ifdef CONFIG_40x
615 b . /* Prevent prefetch past rfi */
616 #endif
617 _ASM_NOKPROBE_SYMBOL(ret_from_kernel_syscall)
619 /*
620 * The fork/clone functions need to copy the full register set into
621 * the child process. Therefore we need to save all the nonvolatile
622 * registers (r13 - r31) before calling the C code.
623 */
624 .globl ppc_fork
625 ppc_fork:
626 SAVE_NVGPRS(r1)
627 lwz r0,_TRAP(r1)
628 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
629 stw r0,_TRAP(r1) /* register set saved */
630 b sys_fork
632 .globl ppc_vfork
633 ppc_vfork:
634 SAVE_NVGPRS(r1)
635 lwz r0,_TRAP(r1)
636 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
637 stw r0,_TRAP(r1) /* register set saved */
638 b sys_vfork
640 .globl ppc_clone
641 ppc_clone:
642 SAVE_NVGPRS(r1)
643 lwz r0,_TRAP(r1)
644 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
645 stw r0,_TRAP(r1) /* register set saved */
646 b sys_clone
648 .globl ppc_clone3
649 ppc_clone3:
650 SAVE_NVGPRS(r1)
651 lwz r0,_TRAP(r1)
652 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
653 stw r0,_TRAP(r1) /* register set saved */
654 b sys_clone3
656 .globl ppc_swapcontext
657 ppc_swapcontext:
658 SAVE_NVGPRS(r1)
659 lwz r0,_TRAP(r1)
660 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
661 stw r0,_TRAP(r1) /* register set saved */
662 b sys_swapcontext
664 /*
665 * Top-level page fault handling.
666 * This is in assembler because if do_page_fault tells us that
667 * it is a bad kernel page fault, we want to save the non-volatile
668 * registers before calling bad_page_fault.
669 */
670 .globl handle_page_fault
671 handle_page_fault:
672 addi r3,r1,STACK_FRAME_OVERHEAD
673 #ifdef CONFIG_PPC_BOOK3S_32
674 andis. r0,r5,DSISR_DABRMATCH@h
675 bne- handle_dabr_fault
676 #endif
677 bl do_page_fault
678 cmpwi r3,0
679 beq+ ret_from_except
680 SAVE_NVGPRS(r1)
681 lwz r0,_TRAP(r1)
682 clrrwi r0,r0,1
683 stw r0,_TRAP(r1)
684 mr r5,r3
685 addi r3,r1,STACK_FRAME_OVERHEAD
686 lwz r4,_DAR(r1)
687 bl __bad_page_fault
688 b ret_from_except_full
690 #ifdef CONFIG_PPC_BOOK3S_32
691 /* We have a data breakpoint exception - handle it */
692 handle_dabr_fault:
693 SAVE_NVGPRS(r1)
694 lwz r0,_TRAP(r1)
695 clrrwi r0,r0,1
696 stw r0,_TRAP(r1)
697 bl do_break
698 b ret_from_except_full
699 #endif
701 /*
702 * This routine switches between two different tasks. The process
703 * state of one is saved on its kernel stack. Then the state
704 * of the other is restored from its kernel stack. The memory
705 * management hardware is updated to the second process's state.
706 * Finally, we can return to the second process.
707 * On entry, r3 points to the THREAD for the current task, r4
708 * points to the THREAD for the new task.
709 *
710 * This routine is always called with interrupts disabled.
711 *
712 * Note: there are two ways to get to the "going out" portion
713 * of this code; either by coming in via the entry (_switch)
714 * or via "fork" which must set up an environment equivalent
715 * to the "_switch" path. If you change this , you'll have to
716 * change the fork code also.
717 *
718 * The code which creates the new task context is in 'copy_thread'
719 * in arch/ppc/kernel/process.c
720 */
721 _GLOBAL(_switch)
722 stwu r1,-INT_FRAME_SIZE(r1)
723 mflr r0
724 stw r0,INT_FRAME_SIZE+4(r1)
725 /* r3-r12 are caller saved -- Cort */
726 SAVE_NVGPRS(r1)
727 stw r0,_NIP(r1) /* Return to switch caller */
728 mfmsr r11
729 li r0,MSR_FP /* Disable floating-point */
730 #ifdef CONFIG_ALTIVEC
731 BEGIN_FTR_SECTION
732 oris r0,r0,MSR_VEC@h /* Disable altivec */
733 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
734 stw r12,THREAD+THREAD_VRSAVE(r2)
735 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
736 #endif /* CONFIG_ALTIVEC */
737 #ifdef CONFIG_SPE
738 BEGIN_FTR_SECTION
739 oris r0,r0,MSR_SPE@h /* Disable SPE */
740 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
741 stw r12,THREAD+THREAD_SPEFSCR(r2)
742 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
743 #endif /* CONFIG_SPE */
744 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
745 beq+ 1f
746 andc r11,r11,r0
747 mtmsr r11
748 isync
749 1: stw r11,_MSR(r1)
750 mfcr r10
751 stw r10,_CCR(r1)
752 stw r1,KSP(r3) /* Set old stack pointer */
754 kuap_check r2, r0
755 #ifdef CONFIG_SMP
756 /* We need a sync somewhere here to make sure that if the
757 * previous task gets rescheduled on another CPU, it sees all
758 * stores it has performed on this one.
759 */
760 sync
761 #endif /* CONFIG_SMP */
763 tophys(r0,r4)
764 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
765 lwz r1,KSP(r4) /* Load new stack pointer */
767 /* save the old current 'last' for return value */
768 mr r3,r2
769 addi r2,r4,-THREAD /* Update current */
771 #ifdef CONFIG_ALTIVEC
772 BEGIN_FTR_SECTION
773 lwz r0,THREAD+THREAD_VRSAVE(r2)
774 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
775 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
776 #endif /* CONFIG_ALTIVEC */
777 #ifdef CONFIG_SPE
778 BEGIN_FTR_SECTION
779 lwz r0,THREAD+THREAD_SPEFSCR(r2)
780 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
781 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
782 #endif /* CONFIG_SPE */
784 lwz r0,_CCR(r1)
785 mtcrf 0xFF,r0
786 /* r3-r12 are destroyed -- Cort */
787 REST_NVGPRS(r1)
789 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
790 mtlr r4
791 addi r1,r1,INT_FRAME_SIZE
792 blr
794 .globl fast_exception_return
795 fast_exception_return:
796 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
797 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
798 beq 1f /* if not, we've got problems */
799 #endif
801 2: REST_4GPRS(3, r11)
802 lwz r10,_CCR(r11)
803 REST_GPR(1, r11)
804 mtcr r10
805 lwz r10,_LINK(r11)
806 mtlr r10
807 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
808 li r10, 0
809 stw r10, 8(r11)
810 REST_GPR(10, r11)
811 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
812 mtspr SPRN_NRI, r0
813 #endif
814 mtspr SPRN_SRR1,r9
815 mtspr SPRN_SRR0,r12
816 REST_GPR(9, r11)
817 REST_GPR(12, r11)
818 lwz r11,GPR11(r11)
819 rfi
820 #ifdef CONFIG_40x
821 b . /* Prevent prefetch past rfi */
822 #endif
823 _ASM_NOKPROBE_SYMBOL(fast_exception_return)
825 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
826 /* check if the exception happened in a restartable section */
827 1: lis r3,exc_exit_restart_end@ha
828 addi r3,r3,exc_exit_restart_end@l
829 cmplw r12,r3
830 bge 3f
831 lis r4,exc_exit_restart@ha
832 addi r4,r4,exc_exit_restart@l
833 cmplw r12,r4
834 blt 3f
835 lis r3,fee_restarts@ha
836 tophys(r3,r3)
837 lwz r5,fee_restarts@l(r3)
838 addi r5,r5,1
839 stw r5,fee_restarts@l(r3)
840 mr r12,r4 /* restart at exc_exit_restart */
841 b 2b
843 .section .bss
844 .align 2
845 fee_restarts:
846 .space 4
847 .previous
849 /* aargh, a nonrecoverable interrupt, panic */
850 /* aargh, we don't know which trap this is */
851 3:
852 li r10,-1
853 stw r10,_TRAP(r11)
854 addi r3,r1,STACK_FRAME_OVERHEAD
855 lis r10,MSR_KERNEL@h
856 ori r10,r10,MSR_KERNEL@l
857 bl transfer_to_handler_full
858 .long unrecoverable_exception
859 .long ret_from_except
860 #endif
862 .globl ret_from_except_full
863 ret_from_except_full:
864 REST_NVGPRS(r1)
865 /* fall through */
867 .globl ret_from_except
868 ret_from_except:
869 /* Hard-disable interrupts so that current_thread_info()->flags
870 * can't change between when we test it and when we return
871 * from the interrupt. */
872 /* Note: We don't bother telling lockdep about it */
873 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
874 mtmsr r10 /* disable interrupts */
876 lwz r3,_MSR(r1) /* Returning to user mode? */
877 andi. r0,r3,MSR_PR
878 beq resume_kernel
880 user_exc_return: /* r10 contains MSR_KERNEL here */
881 /* Check current_thread_info()->flags */
882 lwz r9,TI_FLAGS(r2)
883 andi. r0,r9,_TIF_USER_WORK_MASK
884 bne do_work
886 restore_user:
887 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
888 /* Check whether this process has its own DBCR0 value. The internal
889 debug mode bit tells us that dbcr0 should be loaded. */
890 lwz r0,THREAD+THREAD_DBCR0(r2)
891 andis. r10,r0,DBCR0_IDM@h
892 bnel- load_dbcr0
893 #endif
894 ACCOUNT_CPU_USER_EXIT(r2, r10, r11)
895 #ifdef CONFIG_PPC_BOOK3S_32
896 kuep_unlock r10, r11
897 #endif
899 b restore
901 /* N.B. the only way to get here is from the beq following ret_from_except. */
902 resume_kernel:
903 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
904 lwz r8,TI_FLAGS(r2)
905 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
906 beq+ 1f
908 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
910 lwz r3,GPR1(r1)
911 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
912 mr r4,r1 /* src: current exception frame */
913 mr r1,r3 /* Reroute the trampoline frame to r1 */
915 /* Copy from the original to the trampoline. */
916 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
917 li r6,0 /* start offset: 0 */
918 mtctr r5
919 2: lwzx r0,r6,r4
920 stwx r0,r6,r3
921 addi r6,r6,4
922 bdnz 2b
924 /* Do real store operation to complete stwu */
925 lwz r5,GPR1(r1)
926 stw r8,0(r5)
928 /* Clear _TIF_EMULATE_STACK_STORE flag */
929 lis r11,_TIF_EMULATE_STACK_STORE@h
930 addi r5,r2,TI_FLAGS
931 0: lwarx r8,0,r5
932 andc r8,r8,r11
933 stwcx. r8,0,r5
934 bne- 0b
935 1:
937 #ifdef CONFIG_PREEMPTION
938 /* check current_thread_info->preempt_count */
939 lwz r0,TI_PREEMPT(r2)
940 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
941 bne restore_kuap
942 andi. r8,r8,_TIF_NEED_RESCHED
943 beq+ restore_kuap
944 lwz r3,_MSR(r1)
945 andi. r0,r3,MSR_EE /* interrupts off? */
946 beq restore_kuap /* don't schedule if so */
947 #ifdef CONFIG_TRACE_IRQFLAGS
948 /* Lockdep thinks irqs are enabled, we need to call
949 * preempt_schedule_irq with IRQs off, so we inform lockdep
950 * now that we -did- turn them off already
951 */
952 bl trace_hardirqs_off
953 #endif
954 bl preempt_schedule_irq
955 #ifdef CONFIG_TRACE_IRQFLAGS
956 /* And now, to properly rebalance the above, we tell lockdep they
957 * are being turned back on, which will happen when we return
958 */
959 bl trace_hardirqs_on
960 #endif
961 #endif /* CONFIG_PREEMPTION */
962 restore_kuap:
963 kuap_restore r1, r2, r9, r10, r0
965 /* interrupts are hard-disabled at this point */
966 restore:
967 #if defined(CONFIG_44x) && !defined(CONFIG_PPC_47x)
968 lis r4,icache_44x_need_flush@ha
969 lwz r5,icache_44x_need_flush@l(r4)
970 cmplwi cr0,r5,0
971 beq+ 1f
972 li r6,0
973 iccci r0,r0
974 stw r6,icache_44x_need_flush@l(r4)
975 1:
976 #endif /* CONFIG_44x */
978 lwz r9,_MSR(r1)
979 #ifdef CONFIG_TRACE_IRQFLAGS
980 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
981 * off in this assembly code while peeking at TI_FLAGS() and such. However
982 * we need to inform it if the exception turned interrupts off, and we
983 * are about to trun them back on.
984 */
985 andi. r10,r9,MSR_EE
986 beq 1f
987 stwu r1,-32(r1)
988 mflr r0
989 stw r0,4(r1)
990 bl trace_hardirqs_on
991 addi r1, r1, 32
992 lwz r9,_MSR(r1)
993 1:
994 #endif /* CONFIG_TRACE_IRQFLAGS */
996 lwz r0,GPR0(r1)
997 lwz r2,GPR2(r1)
998 REST_4GPRS(3, r1)
999 REST_2GPRS(7, r1)
1001 lwz r10,_XER(r1)
1002 lwz r11,_CTR(r1)
1003 mtspr SPRN_XER,r10
1004 mtctr r11
1006 BEGIN_FTR_SECTION
1007 lwarx r11,0,r1
1008 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
1009 stwcx. r0,0,r1 /* to clear the reservation */
1011 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
1012 andi. r10,r9,MSR_RI /* check if this exception occurred */
1013 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
1015 lwz r10,_CCR(r1)
1016 lwz r11,_LINK(r1)
1017 mtcrf 0xFF,r10
1018 mtlr r11
1020 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1021 li r10, 0
1022 stw r10, 8(r1)
1023 /*
1024 * Once we put values in SRR0 and SRR1, we are in a state
1025 * where exceptions are not recoverable, since taking an
1026 * exception will trash SRR0 and SRR1. Therefore we clear the
1027 * MSR:RI bit to indicate this. If we do take an exception,
1028 * we can't return to the point of the exception but we
1029 * can restart the exception exit path at the label
1030 * exc_exit_restart below. -- paulus
1031 */
1032 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL & ~MSR_RI)
1033 mtmsr r10 /* clear the RI bit */
1034 .globl exc_exit_restart
1035 exc_exit_restart:
1036 lwz r12,_NIP(r1)
1037 mtspr SPRN_SRR0,r12
1038 mtspr SPRN_SRR1,r9
1039 REST_4GPRS(9, r1)
1040 lwz r1,GPR1(r1)
1041 .globl exc_exit_restart_end
1042 exc_exit_restart_end:
1043 rfi
1044 _ASM_NOKPROBE_SYMBOL(exc_exit_restart)
1045 _ASM_NOKPROBE_SYMBOL(exc_exit_restart_end)
1047 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
1048 /*
1049 * This is a bit different on 4xx/Book-E because it doesn't have
1050 * the RI bit in the MSR.
1051 * The TLB miss handler checks if we have interrupted
1052 * the exception exit path and restarts it if so
1053 * (well maybe one day it will... :).
1054 */
1055 lwz r11,_LINK(r1)
1056 mtlr r11
1057 lwz r10,_CCR(r1)
1058 mtcrf 0xff,r10
1059 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1060 li r10, 0
1061 stw r10, 8(r1)
1062 REST_2GPRS(9, r1)
1063 .globl exc_exit_restart
1064 exc_exit_restart:
1065 lwz r11,_NIP(r1)
1066 lwz r12,_MSR(r1)
1067 mtspr SPRN_SRR0,r11
1068 mtspr SPRN_SRR1,r12
1069 REST_2GPRS(11, r1)
1070 lwz r1,GPR1(r1)
1071 .globl exc_exit_restart_end
1072 exc_exit_restart_end:
1073 rfi
1074 b . /* prevent prefetch past rfi */
1075 _ASM_NOKPROBE_SYMBOL(exc_exit_restart)
1077 /*
1078 * Returning from a critical interrupt in user mode doesn't need
1079 * to be any different from a normal exception. For a critical
1080 * interrupt in the kernel, we just return (without checking for
1081 * preemption) since the interrupt may have happened at some crucial
1082 * place (e.g. inside the TLB miss handler), and because we will be
1083 * running with r1 pointing into critical_stack, not the current
1084 * process's kernel stack (and therefore current_thread_info() will
1085 * give the wrong answer).
1086 * We have to restore various SPRs that may have been in use at the
1087 * time of the critical interrupt.
1088 *
1089 */
1090 #ifdef CONFIG_40x
1091 #define PPC_40x_TURN_OFF_MSR_DR \
1092 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1093 * assume the instructions here are mapped by a pinned TLB entry */ \
1094 li r10,MSR_IR; \
1095 mtmsr r10; \
1096 isync; \
1097 tophys(r1, r1);
1098 #else
1099 #define PPC_40x_TURN_OFF_MSR_DR
1100 #endif
1102 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1103 REST_NVGPRS(r1); \
1104 lwz r3,_MSR(r1); \
1105 andi. r3,r3,MSR_PR; \
1106 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL); \
1107 bne user_exc_return; \
1108 lwz r0,GPR0(r1); \
1109 lwz r2,GPR2(r1); \
1110 REST_4GPRS(3, r1); \
1111 REST_2GPRS(7, r1); \
1112 lwz r10,_XER(r1); \
1113 lwz r11,_CTR(r1); \
1114 mtspr SPRN_XER,r10; \
1115 mtctr r11; \
1116 stwcx. r0,0,r1; /* to clear the reservation */ \
1117 lwz r11,_LINK(r1); \
1118 mtlr r11; \
1119 lwz r10,_CCR(r1); \
1120 mtcrf 0xff,r10; \
1121 PPC_40x_TURN_OFF_MSR_DR; \
1122 lwz r9,_DEAR(r1); \
1123 lwz r10,_ESR(r1); \
1124 mtspr SPRN_DEAR,r9; \
1125 mtspr SPRN_ESR,r10; \
1126 lwz r11,_NIP(r1); \
1127 lwz r12,_MSR(r1); \
1128 mtspr exc_lvl_srr0,r11; \
1129 mtspr exc_lvl_srr1,r12; \
1130 lwz r9,GPR9(r1); \
1131 lwz r12,GPR12(r1); \
1132 lwz r10,GPR10(r1); \
1133 lwz r11,GPR11(r1); \
1134 lwz r1,GPR1(r1); \
1135 exc_lvl_rfi; \
1136 b .; /* prevent prefetch past exc_lvl_rfi */
1138 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1139 lwz r9,_##exc_lvl_srr0(r1); \
1140 lwz r10,_##exc_lvl_srr1(r1); \
1141 mtspr SPRN_##exc_lvl_srr0,r9; \
1142 mtspr SPRN_##exc_lvl_srr1,r10;
1144 #if defined(CONFIG_PPC_BOOK3E_MMU)
1145 #ifdef CONFIG_PHYS_64BIT
1146 #define RESTORE_MAS7 \
1147 lwz r11,MAS7(r1); \
1148 mtspr SPRN_MAS7,r11;
1149 #else
1150 #define RESTORE_MAS7
1151 #endif /* CONFIG_PHYS_64BIT */
1152 #define RESTORE_MMU_REGS \
1153 lwz r9,MAS0(r1); \
1154 lwz r10,MAS1(r1); \
1155 lwz r11,MAS2(r1); \
1156 mtspr SPRN_MAS0,r9; \
1157 lwz r9,MAS3(r1); \
1158 mtspr SPRN_MAS1,r10; \
1159 lwz r10,MAS6(r1); \
1160 mtspr SPRN_MAS2,r11; \
1161 mtspr SPRN_MAS3,r9; \
1162 mtspr SPRN_MAS6,r10; \
1163 RESTORE_MAS7;
1164 #elif defined(CONFIG_44x)
1165 #define RESTORE_MMU_REGS \
1166 lwz r9,MMUCR(r1); \
1167 mtspr SPRN_MMUCR,r9;
1168 #else
1169 #define RESTORE_MMU_REGS
1170 #endif
1172 #ifdef CONFIG_40x
1173 .globl ret_from_crit_exc
1174 ret_from_crit_exc:
1175 mfspr r9,SPRN_SPRG_THREAD
1176 lis r10,saved_ksp_limit@ha;
1177 lwz r10,saved_ksp_limit@l(r10);
1178 tovirt(r9,r9);
1179 stw r10,KSP_LIMIT(r9)
1180 lis r9,crit_srr0@ha;
1181 lwz r9,crit_srr0@l(r9);
1182 lis r10,crit_srr1@ha;
1183 lwz r10,crit_srr1@l(r10);
1184 mtspr SPRN_SRR0,r9;
1185 mtspr SPRN_SRR1,r10;
1186 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1187 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
1188 #endif /* CONFIG_40x */
1190 #ifdef CONFIG_BOOKE
1191 .globl ret_from_crit_exc
1192 ret_from_crit_exc:
1193 mfspr r9,SPRN_SPRG_THREAD
1194 lwz r10,SAVED_KSP_LIMIT(r1)
1195 stw r10,KSP_LIMIT(r9)
1196 RESTORE_xSRR(SRR0,SRR1);
1197 RESTORE_MMU_REGS;
1198 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1199 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
1201 .globl ret_from_debug_exc
1202 ret_from_debug_exc:
1203 mfspr r9,SPRN_SPRG_THREAD
1204 lwz r10,SAVED_KSP_LIMIT(r1)
1205 stw r10,KSP_LIMIT(r9)
1206 RESTORE_xSRR(SRR0,SRR1);
1207 RESTORE_xSRR(CSRR0,CSRR1);
1208 RESTORE_MMU_REGS;
1209 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1210 _ASM_NOKPROBE_SYMBOL(ret_from_debug_exc)
1212 .globl ret_from_mcheck_exc
1213 ret_from_mcheck_exc:
1214 mfspr r9,SPRN_SPRG_THREAD
1215 lwz r10,SAVED_KSP_LIMIT(r1)
1216 stw r10,KSP_LIMIT(r9)
1217 RESTORE_xSRR(SRR0,SRR1);
1218 RESTORE_xSRR(CSRR0,CSRR1);
1219 RESTORE_xSRR(DSRR0,DSRR1);
1220 RESTORE_MMU_REGS;
1221 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1222 _ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc)
1223 #endif /* CONFIG_BOOKE */
1225 /*
1226 * Load the DBCR0 value for a task that is being ptraced,
1227 * having first saved away the global DBCR0. Note that r0
1228 * has the dbcr0 value to set upon entry to this.
1229 */
1230 load_dbcr0:
1231 mfmsr r10 /* first disable debug exceptions */
1232 rlwinm r10,r10,0,~MSR_DE
1233 mtmsr r10
1234 isync
1235 mfspr r10,SPRN_DBCR0
1236 lis r11,global_dbcr0@ha
1237 addi r11,r11,global_dbcr0@l
1238 #ifdef CONFIG_SMP
1239 lwz r9,TASK_CPU(r2)
1240 slwi r9,r9,3
1241 add r11,r11,r9
1242 #endif
1243 stw r10,0(r11)
1244 mtspr SPRN_DBCR0,r0
1245 lwz r10,4(r11)
1246 addi r10,r10,1
1247 stw r10,4(r11)
1248 li r11,-1
1249 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1250 blr
1252 .section .bss
1253 .align 4
1254 .global global_dbcr0
1255 global_dbcr0:
1256 .space 8*NR_CPUS
1257 .previous
1258 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1260 do_work: /* r10 contains MSR_KERNEL here */
1261 andi. r0,r9,_TIF_NEED_RESCHED
1262 beq do_user_signal
1264 do_resched: /* r10 contains MSR_KERNEL here */
1265 #ifdef CONFIG_TRACE_IRQFLAGS
1266 bl trace_hardirqs_on
1267 mfmsr r10
1268 #endif
1269 ori r10,r10,MSR_EE
1270 mtmsr r10 /* hard-enable interrupts */
1271 bl schedule
1272 recheck:
1273 /* Note: And we don't tell it we are disabling them again
1274 * neither. Those disable/enable cycles used to peek at
1275 * TI_FLAGS aren't advertised.
1276 */
1277 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
1278 mtmsr r10 /* disable interrupts */
1279 lwz r9,TI_FLAGS(r2)
1280 andi. r0,r9,_TIF_NEED_RESCHED
1281 bne- do_resched
1282 andi. r0,r9,_TIF_USER_WORK_MASK
1283 beq restore_user
1284 do_user_signal: /* r10 contains MSR_KERNEL here */
1285 ori r10,r10,MSR_EE
1286 mtmsr r10 /* hard-enable interrupts */
1287 /* save r13-r31 in the exception frame, if not already done */
1288 lwz r3,_TRAP(r1)
1289 andi. r0,r3,1
1290 beq 2f
1291 SAVE_NVGPRS(r1)
1292 rlwinm r3,r3,0,0,30
1293 stw r3,_TRAP(r1)
1294 2: addi r3,r1,STACK_FRAME_OVERHEAD
1295 mr r4,r9
1296 bl do_notify_resume
1297 REST_NVGPRS(r1)
1298 b recheck
1300 /*
1301 * We come here when we are at the end of handling an exception
1302 * that occurred at a place where taking an exception will lose
1303 * state information, such as the contents of SRR0 and SRR1.
1304 */
1305 nonrecoverable:
1306 lis r10,exc_exit_restart_end@ha
1307 addi r10,r10,exc_exit_restart_end@l
1308 cmplw r12,r10
1309 bge 3f
1310 lis r11,exc_exit_restart@ha
1311 addi r11,r11,exc_exit_restart@l
1312 cmplw r12,r11
1313 blt 3f
1314 lis r10,ee_restarts@ha
1315 lwz r12,ee_restarts@l(r10)
1316 addi r12,r12,1
1317 stw r12,ee_restarts@l(r10)
1318 mr r12,r11 /* restart at exc_exit_restart */
1319 blr
1320 3: /* OK, we can't recover, kill this process */
1321 lwz r3,_TRAP(r1)
1322 andi. r0,r3,1
1323 beq 5f
1324 SAVE_NVGPRS(r1)
1325 rlwinm r3,r3,0,0,30
1326 stw r3,_TRAP(r1)
1327 5: mfspr r2,SPRN_SPRG_THREAD
1328 addi r2,r2,-THREAD
1329 tovirt(r2,r2) /* set back r2 to current */
1330 4: addi r3,r1,STACK_FRAME_OVERHEAD
1331 bl unrecoverable_exception
1332 /* shouldn't return */
1333 b 4b
1334 _ASM_NOKPROBE_SYMBOL(nonrecoverable)
1336 .section .bss
1337 .align 2
1338 ee_restarts:
1339 .space 4
1340 .previous
1342 /*
1343 * PROM code for specific machines follows. Put it
1344 * here so it's easy to add arch-specific sections later.
1345 * -- Cort
1346 */
1347 #ifdef CONFIG_PPC_RTAS
1348 /*
1349 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1350 * called with the MMU off.
1351 */
1352 _GLOBAL(enter_rtas)
1353 stwu r1,-INT_FRAME_SIZE(r1)
1354 mflr r0
1355 stw r0,INT_FRAME_SIZE+4(r1)
1356 LOAD_REG_ADDR(r4, rtas)
1357 lis r6,1f@ha /* physical return address for rtas */
1358 addi r6,r6,1f@l
1359 tophys(r6,r6)
1360 tophys_novmstack r7, r1
1361 lwz r8,RTASENTRY(r4)
1362 lwz r4,RTASBASE(r4)
1363 mfmsr r9
1364 stw r9,8(r1)
1365 LOAD_REG_IMMEDIATE(r0,MSR_KERNEL)
1366 mtmsr r0 /* disable interrupts so SRR0/1 don't get trashed */
1367 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1368 mtlr r6
1369 stw r7, THREAD + RTAS_SP(r2)
1370 mtspr SPRN_SRR0,r8
1371 mtspr SPRN_SRR1,r9
1372 rfi
1373 1: tophys_novmstack r9, r1
1374 #ifdef CONFIG_VMAP_STACK
1375 li r0, MSR_KERNEL & ~MSR_IR /* can take DTLB miss */
1376 mtmsr r0
1377 isync
1378 #endif
1379 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1380 lwz r9,8(r9) /* original msr value */
1381 addi r1,r1,INT_FRAME_SIZE
1382 li r0,0
1383 tophys_novmstack r7, r2
1384 stw r0, THREAD + RTAS_SP(r7)
1385 mtspr SPRN_SRR0,r8
1386 mtspr SPRN_SRR1,r9
1387 rfi /* return to caller */
1388 _ASM_NOKPROBE_SYMBOL(enter_rtas)
1389 #endif /* CONFIG_PPC_RTAS */