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io_uring: ensure finish_wait() is always called in __io_uring_task_cancel()
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-msm.c
blob9c7927b03253b44d0aa8921e791b8cf36e8a3205
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 *
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 */
7
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/delay.h>
11 #include <linux/mmc/mmc.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/pm_opp.h>
14 #include <linux/slab.h>
15 #include <linux/iopoll.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/interconnect.h>
18 #include <linux/pinctrl/consumer.h>
19
20 #include "sdhci-pltfm.h"
21 #include "cqhci.h"
22
23 #define CORE_MCI_VERSION 0x50
24 #define CORE_VERSION_MAJOR_SHIFT 28
25 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
26 #define CORE_VERSION_MINOR_MASK 0xff
27
28 #define CORE_MCI_GENERICS 0x70
29 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
30
31 #define HC_MODE_EN 0x1
32 #define CORE_POWER 0x0
33 #define CORE_SW_RST BIT(7)
34 #define FF_CLK_SW_RST_DIS BIT(13)
35
36 #define CORE_PWRCTL_BUS_OFF BIT(0)
37 #define CORE_PWRCTL_BUS_ON BIT(1)
38 #define CORE_PWRCTL_IO_LOW BIT(2)
39 #define CORE_PWRCTL_IO_HIGH BIT(3)
40 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
41 #define CORE_PWRCTL_BUS_FAIL BIT(1)
42 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
43 #define CORE_PWRCTL_IO_FAIL BIT(3)
44 #define REQ_BUS_OFF BIT(0)
45 #define REQ_BUS_ON BIT(1)
46 #define REQ_IO_LOW BIT(2)
47 #define REQ_IO_HIGH BIT(3)
48 #define INT_MASK 0xf
49 #define MAX_PHASES 16
50 #define CORE_DLL_LOCK BIT(7)
51 #define CORE_DDR_DLL_LOCK BIT(11)
52 #define CORE_DLL_EN BIT(16)
53 #define CORE_CDR_EN BIT(17)
54 #define CORE_CK_OUT_EN BIT(18)
55 #define CORE_CDR_EXT_EN BIT(19)
56 #define CORE_DLL_PDN BIT(29)
57 #define CORE_DLL_RST BIT(30)
58 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
59
60 #define CORE_DDR_CAL_EN BIT(0)
61 #define CORE_FLL_CYCLE_CNT BIT(18)
62 #define CORE_DLL_CLOCK_DISABLE BIT(21)
63
64 #define DLL_USR_CTL_POR_VAL 0x10800
65 #define ENABLE_DLL_LOCK_STATUS BIT(26)
66 #define FINE_TUNE_MODE_EN BIT(27)
67 #define BIAS_OK_SIGNAL BIT(29)
68
69 #define DLL_CONFIG_3_LOW_FREQ_VAL 0x08
70 #define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10
71
72 #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
73 #define CORE_CLK_PWRSAVE BIT(1)
74 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
75 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
76 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
77 #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
78 #define CORE_IO_PAD_PWR_SWITCH BIT(16)
79 #define CORE_HC_SELECT_IN_EN BIT(18)
80 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
81 #define CORE_HC_SELECT_IN_MASK (7 << 19)
82
83 #define CORE_3_0V_SUPPORT BIT(25)
84 #define CORE_1_8V_SUPPORT BIT(26)
85 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
86
87 #define CORE_CSR_CDC_CTLR_CFG0 0x130
88 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
89 #define CORE_HW_AUTOCAL_ENA BIT(17)
90
91 #define CORE_CSR_CDC_CTLR_CFG1 0x134
92 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
93 #define CORE_TIMER_ENA BIT(16)
94
95 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
96 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
97 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
98 #define CORE_CDC_OFFSET_CFG 0x14C
99 #define CORE_CSR_CDC_DELAY_CFG 0x150
100 #define CORE_CDC_SLAVE_DDA_CFG 0x160
101 #define CORE_CSR_CDC_STATUS0 0x164
102 #define CORE_CALIBRATION_DONE BIT(0)
103
104 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
105
106 #define CORE_CSR_CDC_GEN_CFG 0x178
107 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
108 #define CORE_CDC_SWITCH_RC_EN BIT(1)
109
110 #define CORE_CDC_T4_DLY_SEL BIT(0)
111 #define CORE_CMDIN_RCLK_EN BIT(1)
112 #define CORE_START_CDC_TRAFFIC BIT(6)
113
114 #define CORE_PWRSAVE_DLL BIT(3)
115
116 #define DDR_CONFIG_POR_VAL 0x80040873
117
118
119 #define INVALID_TUNING_PHASE -1
120 #define SDHCI_MSM_MIN_CLOCK 400000
121 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
122
123 #define CDR_SELEXT_SHIFT 20
124 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
125 #define CMUX_SHIFT_PHASE_SHIFT 24
126 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
127
128 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
129
130 /* Timeout value to avoid infinite waiting for pwr_irq */
131 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
132
133 /* Max load for eMMC Vdd-io supply */
134 #define MMC_VQMMC_MAX_LOAD_UA 325000
135
136 #define msm_host_readl(msm_host, host, offset) \
137 msm_host->var_ops->msm_readl_relaxed(host, offset)
138
139 #define msm_host_writel(msm_host, val, host, offset) \
140 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
141
142 /* CQHCI vendor specific registers */
143 #define CQHCI_VENDOR_CFG1 0xA00
144 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13)
145
146 struct sdhci_msm_offset {
147 u32 core_hc_mode;
148 u32 core_mci_data_cnt;
149 u32 core_mci_status;
150 u32 core_mci_fifo_cnt;
151 u32 core_mci_version;
152 u32 core_generics;
153 u32 core_testbus_config;
154 u32 core_testbus_sel2_bit;
155 u32 core_testbus_ena;
156 u32 core_testbus_sel2;
157 u32 core_pwrctl_status;
158 u32 core_pwrctl_mask;
159 u32 core_pwrctl_clear;
160 u32 core_pwrctl_ctl;
161 u32 core_sdcc_debug_reg;
162 u32 core_dll_config;
163 u32 core_dll_status;
164 u32 core_vendor_spec;
165 u32 core_vendor_spec_adma_err_addr0;
166 u32 core_vendor_spec_adma_err_addr1;
167 u32 core_vendor_spec_func2;
168 u32 core_vendor_spec_capabilities0;
169 u32 core_ddr_200_cfg;
170 u32 core_vendor_spec3;
171 u32 core_dll_config_2;
172 u32 core_dll_config_3;
173 u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
174 u32 core_ddr_config;
175 u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
176 };
177
178 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
179 .core_mci_data_cnt = 0x35c,
180 .core_mci_status = 0x324,
181 .core_mci_fifo_cnt = 0x308,
182 .core_mci_version = 0x318,
183 .core_generics = 0x320,
184 .core_testbus_config = 0x32c,
185 .core_testbus_sel2_bit = 3,
186 .core_testbus_ena = (1 << 31),
187 .core_testbus_sel2 = (1 << 3),
188 .core_pwrctl_status = 0x240,
189 .core_pwrctl_mask = 0x244,
190 .core_pwrctl_clear = 0x248,
191 .core_pwrctl_ctl = 0x24c,
192 .core_sdcc_debug_reg = 0x358,
193 .core_dll_config = 0x200,
194 .core_dll_status = 0x208,
195 .core_vendor_spec = 0x20c,
196 .core_vendor_spec_adma_err_addr0 = 0x214,
197 .core_vendor_spec_adma_err_addr1 = 0x218,
198 .core_vendor_spec_func2 = 0x210,
199 .core_vendor_spec_capabilities0 = 0x21c,
200 .core_ddr_200_cfg = 0x224,
201 .core_vendor_spec3 = 0x250,
202 .core_dll_config_2 = 0x254,
203 .core_dll_config_3 = 0x258,
204 .core_ddr_config = 0x25c,
205 .core_dll_usr_ctl = 0x388,
206 };
207
208 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
209 .core_hc_mode = 0x78,
210 .core_mci_data_cnt = 0x30,
211 .core_mci_status = 0x34,
212 .core_mci_fifo_cnt = 0x44,
213 .core_mci_version = 0x050,
214 .core_generics = 0x70,
215 .core_testbus_config = 0x0cc,
216 .core_testbus_sel2_bit = 4,
217 .core_testbus_ena = (1 << 3),
218 .core_testbus_sel2 = (1 << 4),
219 .core_pwrctl_status = 0xdc,
220 .core_pwrctl_mask = 0xe0,
221 .core_pwrctl_clear = 0xe4,
222 .core_pwrctl_ctl = 0xe8,
223 .core_sdcc_debug_reg = 0x124,
224 .core_dll_config = 0x100,
225 .core_dll_status = 0x108,
226 .core_vendor_spec = 0x10c,
227 .core_vendor_spec_adma_err_addr0 = 0x114,
228 .core_vendor_spec_adma_err_addr1 = 0x118,
229 .core_vendor_spec_func2 = 0x110,
230 .core_vendor_spec_capabilities0 = 0x11c,
231 .core_ddr_200_cfg = 0x184,
232 .core_vendor_spec3 = 0x1b0,
233 .core_dll_config_2 = 0x1b4,
234 .core_ddr_config_old = 0x1b8,
235 .core_ddr_config = 0x1bc,
236 };
237
238 struct sdhci_msm_variant_ops {
239 u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
240 void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
241 u32 offset);
242 };
243
244 /*
245 * From V5, register spaces have changed. Wrap this info in a structure
246 * and choose the data_structure based on version info mentioned in DT.
247 */
248 struct sdhci_msm_variant_info {
249 bool mci_removed;
250 bool restore_dll_config;
251 const struct sdhci_msm_variant_ops *var_ops;
252 const struct sdhci_msm_offset *offset;
253 };
254
255 struct sdhci_msm_host {
256 struct platform_device *pdev;
257 void __iomem *core_mem; /* MSM SDCC mapped address */
258 int pwr_irq; /* power irq */
259 struct clk *bus_clk; /* SDHC bus voter clock */
260 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
261 struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
262 unsigned long clk_rate;
263 struct mmc_host *mmc;
264 struct opp_table *opp_table;
265 bool use_14lpp_dll_reset;
266 bool tuning_done;
267 bool calibration_done;
268 u8 saved_tuning_phase;
269 bool use_cdclp533;
270 u32 curr_pwr_state;
271 u32 curr_io_level;
272 wait_queue_head_t pwr_irq_wait;
273 bool pwr_irq_flag;
274 u32 caps_0;
275 bool mci_removed;
276 bool restore_dll_config;
277 const struct sdhci_msm_variant_ops *var_ops;
278 const struct sdhci_msm_offset *offset;
279 bool use_cdr;
280 u32 transfer_mode;
281 bool updated_ddr_cfg;
282 bool uses_tassadar_dll;
283 u32 dll_config;
284 u32 ddr_config;
285 bool vqmmc_enabled;
286 };
287
288 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
289 {
290 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
291 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
292
293 return msm_host->offset;
294 }
295
296 /*
297 * APIs to read/write to vendor specific registers which were there in the
298 * core_mem region before MCI was removed.
299 */
300 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
301 u32 offset)
302 {
303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
304 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
305
306 return readl_relaxed(msm_host->core_mem + offset);
307 }
308
309 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
310 u32 offset)
311 {
312 return readl_relaxed(host->ioaddr + offset);
313 }
314
315 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
316 struct sdhci_host *host, u32 offset)
317 {
318 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
319 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
320
321 writel_relaxed(val, msm_host->core_mem + offset);
322 }
323
324 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
325 struct sdhci_host *host, u32 offset)
326 {
327 writel_relaxed(val, host->ioaddr + offset);
328 }
329
330 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
331 unsigned int clock)
332 {
333 struct mmc_ios ios = host->mmc->ios;
334 /*
335 * The SDHC requires internal clock frequency to be double the
336 * actual clock that will be set for DDR mode. The controller
337 * uses the faster clock(100/400MHz) for some of its parts and
338 * send the actual required clock (50/200MHz) to the card.
339 */
340 if (ios.timing == MMC_TIMING_UHS_DDR50 ||
341 ios.timing == MMC_TIMING_MMC_DDR52 ||
342 ios.timing == MMC_TIMING_MMC_HS400 ||
343 host->flags & SDHCI_HS400_TUNING)
344 clock *= 2;
345 return clock;
346 }
347
348 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
349 unsigned int clock)
350 {
351 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
352 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
353 struct mmc_ios curr_ios = host->mmc->ios;
354 struct clk *core_clk = msm_host->bulk_clks[0].clk;
355 int rc;
356
357 clock = msm_get_clock_rate_for_bus_mode(host, clock);
358 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), clock);
359 if (rc) {
360 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
361 mmc_hostname(host->mmc), clock,
362 curr_ios.timing);
363 return;
364 }
365 msm_host->clk_rate = clock;
366 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
367 mmc_hostname(host->mmc), clk_get_rate(core_clk),
368 curr_ios.timing);
369 }
370
371 /* Platform specific tuning */
372 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
373 {
374 u32 wait_cnt = 50;
375 u8 ck_out_en;
376 struct mmc_host *mmc = host->mmc;
377 const struct sdhci_msm_offset *msm_offset =
378 sdhci_priv_msm_offset(host);
379
380 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
381 ck_out_en = !!(readl_relaxed(host->ioaddr +
382 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
383
384 while (ck_out_en != poll) {
385 if (--wait_cnt == 0) {
386 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
387 mmc_hostname(mmc), poll);
388 return -ETIMEDOUT;
389 }
390 udelay(1);
391
392 ck_out_en = !!(readl_relaxed(host->ioaddr +
393 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
394 }
395
396 return 0;
397 }
398
399 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
400 {
401 int rc;
402 static const u8 grey_coded_phase_table[] = {
403 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
404 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
405 };
406 unsigned long flags;
407 u32 config;
408 struct mmc_host *mmc = host->mmc;
409 const struct sdhci_msm_offset *msm_offset =
410 sdhci_priv_msm_offset(host);
411
412 if (phase > 0xf)
413 return -EINVAL;
414
415 spin_lock_irqsave(&host->lock, flags);
416
417 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
418 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
419 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
420 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
421
422 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
423 rc = msm_dll_poll_ck_out_en(host, 0);
424 if (rc)
425 goto err_out;
426
427 /*
428 * Write the selected DLL clock output phase (0 ... 15)
429 * to CDR_SELEXT bit field of DLL_CONFIG register.
430 */
431 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
432 config &= ~CDR_SELEXT_MASK;
433 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
434 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
435
436 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
437 config |= CORE_CK_OUT_EN;
438 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
439
440 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
441 rc = msm_dll_poll_ck_out_en(host, 1);
442 if (rc)
443 goto err_out;
444
445 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
446 config |= CORE_CDR_EN;
447 config &= ~CORE_CDR_EXT_EN;
448 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
449 goto out;
450
451 err_out:
452 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
453 mmc_hostname(mmc), phase);
454 out:
455 spin_unlock_irqrestore(&host->lock, flags);
456 return rc;
457 }
458
459 /*
460 * Find out the greatest range of consecuitive selected
461 * DLL clock output phases that can be used as sampling
462 * setting for SD3.0 UHS-I card read operation (in SDR104
463 * timing mode) or for eMMC4.5 card read operation (in
464 * HS400/HS200 timing mode).
465 * Select the 3/4 of the range and configure the DLL with the
466 * selected DLL clock output phase.
467 */
468
469 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
470 u8 *phase_table, u8 total_phases)
471 {
472 int ret;
473 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
474 u8 phases_per_row[MAX_PHASES] = { 0 };
475 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
476 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
477 bool phase_0_found = false, phase_15_found = false;
478 struct mmc_host *mmc = host->mmc;
479
480 if (!total_phases || (total_phases > MAX_PHASES)) {
481 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
482 mmc_hostname(mmc), total_phases);
483 return -EINVAL;
484 }
485
486 for (cnt = 0; cnt < total_phases; cnt++) {
487 ranges[row_index][col_index] = phase_table[cnt];
488 phases_per_row[row_index] += 1;
489 col_index++;
490
491 if ((cnt + 1) == total_phases) {
492 continue;
493 /* check if next phase in phase_table is consecutive or not */
494 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
495 row_index++;
496 col_index = 0;
497 }
498 }
499
500 if (row_index >= MAX_PHASES)
501 return -EINVAL;
502
503 /* Check if phase-0 is present in first valid window? */
504 if (!ranges[0][0]) {
505 phase_0_found = true;
506 phase_0_raw_index = 0;
507 /* Check if cycle exist between 2 valid windows */
508 for (cnt = 1; cnt <= row_index; cnt++) {
509 if (phases_per_row[cnt]) {
510 for (i = 0; i < phases_per_row[cnt]; i++) {
511 if (ranges[cnt][i] == 15) {
512 phase_15_found = true;
513 phase_15_raw_index = cnt;
514 break;
515 }
516 }
517 }
518 }
519 }
520
521 /* If 2 valid windows form cycle then merge them as single window */
522 if (phase_0_found && phase_15_found) {
523 /* number of phases in raw where phase 0 is present */
524 u8 phases_0 = phases_per_row[phase_0_raw_index];
525 /* number of phases in raw where phase 15 is present */
526 u8 phases_15 = phases_per_row[phase_15_raw_index];
527
528 if (phases_0 + phases_15 >= MAX_PHASES)
529 /*
530 * If there are more than 1 phase windows then total
531 * number of phases in both the windows should not be
532 * more than or equal to MAX_PHASES.
533 */
534 return -EINVAL;
535
536 /* Merge 2 cyclic windows */
537 i = phases_15;
538 for (cnt = 0; cnt < phases_0; cnt++) {
539 ranges[phase_15_raw_index][i] =
540 ranges[phase_0_raw_index][cnt];
541 if (++i >= MAX_PHASES)
542 break;
543 }
544
545 phases_per_row[phase_0_raw_index] = 0;
546 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
547 }
548
549 for (cnt = 0; cnt <= row_index; cnt++) {
550 if (phases_per_row[cnt] > curr_max) {
551 curr_max = phases_per_row[cnt];
552 selected_row_index = cnt;
553 }
554 }
555
556 i = (curr_max * 3) / 4;
557 if (i)
558 i--;
559
560 ret = ranges[selected_row_index][i];
561
562 if (ret >= MAX_PHASES) {
563 ret = -EINVAL;
564 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
565 mmc_hostname(mmc), ret);
566 }
567
568 return ret;
569 }
570
571 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
572 {
573 u32 mclk_freq = 0, config;
574 const struct sdhci_msm_offset *msm_offset =
575 sdhci_priv_msm_offset(host);
576
577 /* Program the MCLK value to MCLK_FREQ bit field */
578 if (host->clock <= 112000000)
579 mclk_freq = 0;
580 else if (host->clock <= 125000000)
581 mclk_freq = 1;
582 else if (host->clock <= 137000000)
583 mclk_freq = 2;
584 else if (host->clock <= 150000000)
585 mclk_freq = 3;
586 else if (host->clock <= 162000000)
587 mclk_freq = 4;
588 else if (host->clock <= 175000000)
589 mclk_freq = 5;
590 else if (host->clock <= 187000000)
591 mclk_freq = 6;
592 else if (host->clock <= 200000000)
593 mclk_freq = 7;
594
595 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
596 config &= ~CMUX_SHIFT_PHASE_MASK;
597 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
598 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
599 }
600
601 /* Initialize the DLL (Programmable Delay Line) */
602 static int msm_init_cm_dll(struct sdhci_host *host)
603 {
604 struct mmc_host *mmc = host->mmc;
605 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
606 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
607 int wait_cnt = 50;
608 unsigned long flags, xo_clk = 0;
609 u32 config;
610 const struct sdhci_msm_offset *msm_offset =
611 msm_host->offset;
612
613 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
614 xo_clk = clk_get_rate(msm_host->xo_clk);
615
616 spin_lock_irqsave(&host->lock, flags);
617
618 /*
619 * Make sure that clock is always enabled when DLL
620 * tuning is in progress. Keeping PWRSAVE ON may
621 * turn off the clock.
622 */
623 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
624 config &= ~CORE_CLK_PWRSAVE;
625 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
626
627 if (msm_host->dll_config)
628 writel_relaxed(msm_host->dll_config,
629 host->ioaddr + msm_offset->core_dll_config);
630
631 if (msm_host->use_14lpp_dll_reset) {
632 config = readl_relaxed(host->ioaddr +
633 msm_offset->core_dll_config);
634 config &= ~CORE_CK_OUT_EN;
635 writel_relaxed(config, host->ioaddr +
636 msm_offset->core_dll_config);
637
638 config = readl_relaxed(host->ioaddr +
639 msm_offset->core_dll_config_2);
640 config |= CORE_DLL_CLOCK_DISABLE;
641 writel_relaxed(config, host->ioaddr +
642 msm_offset->core_dll_config_2);
643 }
644
645 config = readl_relaxed(host->ioaddr +
646 msm_offset->core_dll_config);
647 config |= CORE_DLL_RST;
648 writel_relaxed(config, host->ioaddr +
649 msm_offset->core_dll_config);
650
651 config = readl_relaxed(host->ioaddr +
652 msm_offset->core_dll_config);
653 config |= CORE_DLL_PDN;
654 writel_relaxed(config, host->ioaddr +
655 msm_offset->core_dll_config);
656
657 if (!msm_host->dll_config)
658 msm_cm_dll_set_freq(host);
659
660 if (msm_host->use_14lpp_dll_reset &&
661 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
662 u32 mclk_freq = 0;
663
664 config = readl_relaxed(host->ioaddr +
665 msm_offset->core_dll_config_2);
666 config &= CORE_FLL_CYCLE_CNT;
667 if (config)
668 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
669 xo_clk);
670 else
671 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
672 xo_clk);
673
674 config = readl_relaxed(host->ioaddr +
675 msm_offset->core_dll_config_2);
676 config &= ~(0xFF << 10);
677 config |= mclk_freq << 10;
678
679 writel_relaxed(config, host->ioaddr +
680 msm_offset->core_dll_config_2);
681 /* wait for 5us before enabling DLL clock */
682 udelay(5);
683 }
684
685 config = readl_relaxed(host->ioaddr +
686 msm_offset->core_dll_config);
687 config &= ~CORE_DLL_RST;
688 writel_relaxed(config, host->ioaddr +
689 msm_offset->core_dll_config);
690
691 config = readl_relaxed(host->ioaddr +
692 msm_offset->core_dll_config);
693 config &= ~CORE_DLL_PDN;
694 writel_relaxed(config, host->ioaddr +
695 msm_offset->core_dll_config);
696
697 if (msm_host->use_14lpp_dll_reset) {
698 if (!msm_host->dll_config)
699 msm_cm_dll_set_freq(host);
700 config = readl_relaxed(host->ioaddr +
701 msm_offset->core_dll_config_2);
702 config &= ~CORE_DLL_CLOCK_DISABLE;
703 writel_relaxed(config, host->ioaddr +
704 msm_offset->core_dll_config_2);
705 }
706
707 /*
708 * Configure DLL user control register to enable DLL status.
709 * This setting is applicable to SDCC v5.1 onwards only.
710 */
711 if (msm_host->uses_tassadar_dll) {
712 config = DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
713 ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;
714 writel_relaxed(config, host->ioaddr +
715 msm_offset->core_dll_usr_ctl);
716
717 config = readl_relaxed(host->ioaddr +
718 msm_offset->core_dll_config_3);
719 config &= ~0xFF;
720 if (msm_host->clk_rate < 150000000)
721 config |= DLL_CONFIG_3_LOW_FREQ_VAL;
722 else
723 config |= DLL_CONFIG_3_HIGH_FREQ_VAL;
724 writel_relaxed(config, host->ioaddr +
725 msm_offset->core_dll_config_3);
726 }
727
728 config = readl_relaxed(host->ioaddr +
729 msm_offset->core_dll_config);
730 config |= CORE_DLL_EN;
731 writel_relaxed(config, host->ioaddr +
732 msm_offset->core_dll_config);
733
734 config = readl_relaxed(host->ioaddr +
735 msm_offset->core_dll_config);
736 config |= CORE_CK_OUT_EN;
737 writel_relaxed(config, host->ioaddr +
738 msm_offset->core_dll_config);
739
740 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
741 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
742 CORE_DLL_LOCK)) {
743 /* max. wait for 50us sec for LOCK bit to be set */
744 if (--wait_cnt == 0) {
745 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
746 mmc_hostname(mmc));
747 spin_unlock_irqrestore(&host->lock, flags);
748 return -ETIMEDOUT;
749 }
750 udelay(1);
751 }
752
753 spin_unlock_irqrestore(&host->lock, flags);
754 return 0;
755 }
756
757 static void msm_hc_select_default(struct sdhci_host *host)
758 {
759 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
760 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
761 u32 config;
762 const struct sdhci_msm_offset *msm_offset =
763 msm_host->offset;
764
765 if (!msm_host->use_cdclp533) {
766 config = readl_relaxed(host->ioaddr +
767 msm_offset->core_vendor_spec3);
768 config &= ~CORE_PWRSAVE_DLL;
769 writel_relaxed(config, host->ioaddr +
770 msm_offset->core_vendor_spec3);
771 }
772
773 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
774 config &= ~CORE_HC_MCLK_SEL_MASK;
775 config |= CORE_HC_MCLK_SEL_DFLT;
776 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
777
778 /*
779 * Disable HC_SELECT_IN to be able to use the UHS mode select
780 * configuration from Host Control2 register for all other
781 * modes.
782 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
783 * in VENDOR_SPEC_FUNC
784 */
785 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
786 config &= ~CORE_HC_SELECT_IN_EN;
787 config &= ~CORE_HC_SELECT_IN_MASK;
788 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
789
790 /*
791 * Make sure above writes impacting free running MCLK are completed
792 * before changing the clk_rate at GCC.
793 */
794 wmb();
795 }
796
797 static void msm_hc_select_hs400(struct sdhci_host *host)
798 {
799 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
800 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
801 struct mmc_ios ios = host->mmc->ios;
802 u32 config, dll_lock;
803 int rc;
804 const struct sdhci_msm_offset *msm_offset =
805 msm_host->offset;
806
807 /* Select the divided clock (free running MCLK/2) */
808 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
809 config &= ~CORE_HC_MCLK_SEL_MASK;
810 config |= CORE_HC_MCLK_SEL_HS400;
811
812 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
813 /*
814 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
815 * register
816 */
817 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
818 !msm_host->calibration_done) {
819 config = readl_relaxed(host->ioaddr +
820 msm_offset->core_vendor_spec);
821 config |= CORE_HC_SELECT_IN_HS400;
822 config |= CORE_HC_SELECT_IN_EN;
823 writel_relaxed(config, host->ioaddr +
824 msm_offset->core_vendor_spec);
825 }
826 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
827 /*
828 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
829 * core_dll_status to be set. This should get set
830 * within 15 us at 200 MHz.
831 */
832 rc = readl_relaxed_poll_timeout(host->ioaddr +
833 msm_offset->core_dll_status,
834 dll_lock,
835 (dll_lock &
836 (CORE_DLL_LOCK |
837 CORE_DDR_DLL_LOCK)), 10,
838 1000);
839 if (rc == -ETIMEDOUT)
840 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
841 mmc_hostname(host->mmc), dll_lock);
842 }
843 /*
844 * Make sure above writes impacting free running MCLK are completed
845 * before changing the clk_rate at GCC.
846 */
847 wmb();
848 }
849
850 /*
851 * sdhci_msm_hc_select_mode :- In general all timing modes are
852 * controlled via UHS mode select in Host Control2 register.
853 * eMMC specific HS200/HS400 doesn't have their respective modes
854 * defined here, hence we use these values.
855 *
856 * HS200 - SDR104 (Since they both are equivalent in functionality)
857 * HS400 - This involves multiple configurations
858 * Initially SDR104 - when tuning is required as HS200
859 * Then when switching to DDR @ 400MHz (HS400) we use
860 * the vendor specific HC_SELECT_IN to control the mode.
861 *
862 * In addition to controlling the modes we also need to select the
863 * correct input clock for DLL depending on the mode.
864 *
865 * HS400 - divided clock (free running MCLK/2)
866 * All other modes - default (free running MCLK)
867 */
868 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
869 {
870 struct mmc_ios ios = host->mmc->ios;
871
872 if (ios.timing == MMC_TIMING_MMC_HS400 ||
873 host->flags & SDHCI_HS400_TUNING)
874 msm_hc_select_hs400(host);
875 else
876 msm_hc_select_default(host);
877 }
878
879 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
880 {
881 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
882 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
883 u32 config, calib_done;
884 int ret;
885 const struct sdhci_msm_offset *msm_offset =
886 msm_host->offset;
887
888 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
889
890 /*
891 * Retuning in HS400 (DDR mode) will fail, just reset the
892 * tuning block and restore the saved tuning phase.
893 */
894 ret = msm_init_cm_dll(host);
895 if (ret)
896 goto out;
897
898 /* Set the selected phase in delay line hw block */
899 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
900 if (ret)
901 goto out;
902
903 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
904 config |= CORE_CMD_DAT_TRACK_SEL;
905 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
906
907 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
908 config &= ~CORE_CDC_T4_DLY_SEL;
909 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
910
911 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
912 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
913 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
914
915 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
916 config |= CORE_CDC_SWITCH_RC_EN;
917 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
918
919 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
920 config &= ~CORE_START_CDC_TRAFFIC;
921 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
922
923 /* Perform CDC Register Initialization Sequence */
924
925 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
926 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
927 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
928 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
929 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
930 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
931 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
932 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
933 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
934
935 /* CDC HW Calibration */
936
937 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
938 config |= CORE_SW_TRIG_FULL_CALIB;
939 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
940
941 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
942 config &= ~CORE_SW_TRIG_FULL_CALIB;
943 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
944
945 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
946 config |= CORE_HW_AUTOCAL_ENA;
947 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
948
949 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
950 config |= CORE_TIMER_ENA;
951 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
952
953 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
954 calib_done,
955 (calib_done & CORE_CALIBRATION_DONE),
956 1, 50);
957
958 if (ret == -ETIMEDOUT) {
959 pr_err("%s: %s: CDC calibration was not completed\n",
960 mmc_hostname(host->mmc), __func__);
961 goto out;
962 }
963
964 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
965 & CORE_CDC_ERROR_CODE_MASK;
966 if (ret) {
967 pr_err("%s: %s: CDC error code %d\n",
968 mmc_hostname(host->mmc), __func__, ret);
969 ret = -EINVAL;
970 goto out;
971 }
972
973 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
974 config |= CORE_START_CDC_TRAFFIC;
975 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
976 out:
977 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
978 __func__, ret);
979 return ret;
980 }
981
982 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
983 {
984 struct mmc_host *mmc = host->mmc;
985 u32 dll_status, config, ddr_cfg_offset;
986 int ret;
987 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
988 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
989 const struct sdhci_msm_offset *msm_offset =
990 sdhci_priv_msm_offset(host);
991
992 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
993
994 /*
995 * Currently the core_ddr_config register defaults to desired
996 * configuration on reset. Currently reprogramming the power on
997 * reset (POR) value in case it might have been modified by
998 * bootloaders. In the future, if this changes, then the desired
999 * values will need to be programmed appropriately.
1000 */
1001 if (msm_host->updated_ddr_cfg)
1002 ddr_cfg_offset = msm_offset->core_ddr_config;
1003 else
1004 ddr_cfg_offset = msm_offset->core_ddr_config_old;
1005 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
1006
1007 if (mmc->ios.enhanced_strobe) {
1008 config = readl_relaxed(host->ioaddr +
1009 msm_offset->core_ddr_200_cfg);
1010 config |= CORE_CMDIN_RCLK_EN;
1011 writel_relaxed(config, host->ioaddr +
1012 msm_offset->core_ddr_200_cfg);
1013 }
1014
1015 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
1016 config |= CORE_DDR_CAL_EN;
1017 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
1018
1019 ret = readl_relaxed_poll_timeout(host->ioaddr +
1020 msm_offset->core_dll_status,
1021 dll_status,
1022 (dll_status & CORE_DDR_DLL_LOCK),
1023 10, 1000);
1024
1025 if (ret == -ETIMEDOUT) {
1026 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
1027 mmc_hostname(host->mmc), __func__);
1028 goto out;
1029 }
1030
1031 /*
1032 * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
1033 * When MCLK is gated OFF, it is not gated for less than 0.5us
1034 * and MCLK must be switched on for at-least 1us before DATA
1035 * starts coming. Controllers with 14lpp and later tech DLL cannot
1036 * guarantee above requirement. So PWRSAVE_DLL should not be
1037 * turned on for host controllers using this DLL.
1038 */
1039 if (!msm_host->use_14lpp_dll_reset) {
1040 config = readl_relaxed(host->ioaddr +
1041 msm_offset->core_vendor_spec3);
1042 config |= CORE_PWRSAVE_DLL;
1043 writel_relaxed(config, host->ioaddr +
1044 msm_offset->core_vendor_spec3);
1045 }
1046
1047 /*
1048 * Drain writebuffer to ensure above DLL calibration
1049 * and PWRSAVE DLL is enabled.
1050 */
1051 wmb();
1052 out:
1053 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1054 __func__, ret);
1055 return ret;
1056 }
1057
1058 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
1059 {
1060 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1061 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1062 struct mmc_host *mmc = host->mmc;
1063 int ret;
1064 u32 config;
1065 const struct sdhci_msm_offset *msm_offset =
1066 msm_host->offset;
1067
1068 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1069
1070 /*
1071 * Retuning in HS400 (DDR mode) will fail, just reset the
1072 * tuning block and restore the saved tuning phase.
1073 */
1074 ret = msm_init_cm_dll(host);
1075 if (ret)
1076 goto out;
1077
1078 if (!mmc->ios.enhanced_strobe) {
1079 /* Set the selected phase in delay line hw block */
1080 ret = msm_config_cm_dll_phase(host,
1081 msm_host->saved_tuning_phase);
1082 if (ret)
1083 goto out;
1084 config = readl_relaxed(host->ioaddr +
1085 msm_offset->core_dll_config);
1086 config |= CORE_CMD_DAT_TRACK_SEL;
1087 writel_relaxed(config, host->ioaddr +
1088 msm_offset->core_dll_config);
1089 }
1090
1091 if (msm_host->use_cdclp533)
1092 ret = sdhci_msm_cdclp533_calibration(host);
1093 else
1094 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1095 out:
1096 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1097 __func__, ret);
1098 return ret;
1099 }
1100
1101 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1102 {
1103 struct mmc_ios *ios = &host->mmc->ios;
1104
1105 /*
1106 * Tuning is required for SDR104, HS200 and HS400 cards and
1107 * if clock frequency is greater than 100MHz in these modes.
1108 */
1109 if (host->clock <= CORE_FREQ_100MHZ ||
1110 !(ios->timing == MMC_TIMING_MMC_HS400 ||
1111 ios->timing == MMC_TIMING_MMC_HS200 ||
1112 ios->timing == MMC_TIMING_UHS_SDR104) ||
1113 ios->enhanced_strobe)
1114 return false;
1115
1116 return true;
1117 }
1118
1119 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1120 {
1121 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1122 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1123 int ret;
1124
1125 /*
1126 * SDR DLL comes into picture only for timing modes which needs
1127 * tuning.
1128 */
1129 if (!sdhci_msm_is_tuning_needed(host))
1130 return 0;
1131
1132 /* Reset the tuning block */
1133 ret = msm_init_cm_dll(host);
1134 if (ret)
1135 return ret;
1136
1137 /* Restore the tuning block */
1138 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1139
1140 return ret;
1141 }
1142
1143 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1144 {
1145 const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1146 u32 config, oldconfig = readl_relaxed(host->ioaddr +
1147 msm_offset->core_dll_config);
1148
1149 config = oldconfig;
1150 if (enable) {
1151 config |= CORE_CDR_EN;
1152 config &= ~CORE_CDR_EXT_EN;
1153 } else {
1154 config &= ~CORE_CDR_EN;
1155 config |= CORE_CDR_EXT_EN;
1156 }
1157
1158 if (config != oldconfig) {
1159 writel_relaxed(config, host->ioaddr +
1160 msm_offset->core_dll_config);
1161 }
1162 }
1163
1164 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1165 {
1166 struct sdhci_host *host = mmc_priv(mmc);
1167 int tuning_seq_cnt = 10;
1168 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1169 int rc;
1170 struct mmc_ios ios = host->mmc->ios;
1171 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1172 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1173
1174 if (!sdhci_msm_is_tuning_needed(host)) {
1175 msm_host->use_cdr = false;
1176 sdhci_msm_set_cdr(host, false);
1177 return 0;
1178 }
1179
1180 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1181 msm_host->use_cdr = true;
1182
1183 /*
1184 * Clear tuning_done flag before tuning to ensure proper
1185 * HS400 settings.
1186 */
1187 msm_host->tuning_done = 0;
1188
1189 /*
1190 * For HS400 tuning in HS200 timing requires:
1191 * - select MCLK/2 in VENDOR_SPEC
1192 * - program MCLK to 400MHz (or nearest supported) in GCC
1193 */
1194 if (host->flags & SDHCI_HS400_TUNING) {
1195 sdhci_msm_hc_select_mode(host);
1196 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1197 host->flags &= ~SDHCI_HS400_TUNING;
1198 }
1199
1200 retry:
1201 /* First of all reset the tuning block */
1202 rc = msm_init_cm_dll(host);
1203 if (rc)
1204 return rc;
1205
1206 phase = 0;
1207 do {
1208 /* Set the phase in delay line hw block */
1209 rc = msm_config_cm_dll_phase(host, phase);
1210 if (rc)
1211 return rc;
1212
1213 rc = mmc_send_tuning(mmc, opcode, NULL);
1214 if (!rc) {
1215 /* Tuning is successful at this tuning point */
1216 tuned_phases[tuned_phase_cnt++] = phase;
1217 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1218 mmc_hostname(mmc), phase);
1219 }
1220 } while (++phase < ARRAY_SIZE(tuned_phases));
1221
1222 if (tuned_phase_cnt) {
1223 if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {
1224 /*
1225 * All phases valid is _almost_ as bad as no phases
1226 * valid. Probably all phases are not really reliable
1227 * but we didn't detect where the unreliable place is.
1228 * That means we'll essentially be guessing and hoping
1229 * we get a good phase. Better to try a few times.
1230 */
1231 dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n",
1232 mmc_hostname(mmc));
1233 if (--tuning_seq_cnt) {
1234 tuned_phase_cnt = 0;
1235 goto retry;
1236 }
1237 }
1238
1239 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1240 tuned_phase_cnt);
1241 if (rc < 0)
1242 return rc;
1243 else
1244 phase = rc;
1245
1246 /*
1247 * Finally set the selected phase in delay
1248 * line hw block.
1249 */
1250 rc = msm_config_cm_dll_phase(host, phase);
1251 if (rc)
1252 return rc;
1253 msm_host->saved_tuning_phase = phase;
1254 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1255 mmc_hostname(mmc), phase);
1256 } else {
1257 if (--tuning_seq_cnt)
1258 goto retry;
1259 /* Tuning failed */
1260 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1261 mmc_hostname(mmc));
1262 rc = -EIO;
1263 }
1264
1265 if (!rc)
1266 msm_host->tuning_done = true;
1267 return rc;
1268 }
1269
1270 /*
1271 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1272 * This needs to be done for both tuning and enhanced_strobe mode.
1273 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1274 * fixed feedback clock is used.
1275 */
1276 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1277 {
1278 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1279 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1280 int ret;
1281
1282 if (host->clock > CORE_FREQ_100MHZ &&
1283 (msm_host->tuning_done || ios->enhanced_strobe) &&
1284 !msm_host->calibration_done) {
1285 ret = sdhci_msm_hs400_dll_calibration(host);
1286 if (!ret)
1287 msm_host->calibration_done = true;
1288 else
1289 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1290 mmc_hostname(host->mmc), ret);
1291 }
1292 }
1293
1294 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1295 unsigned int uhs)
1296 {
1297 struct mmc_host *mmc = host->mmc;
1298 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1299 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1300 u16 ctrl_2;
1301 u32 config;
1302 const struct sdhci_msm_offset *msm_offset =
1303 msm_host->offset;
1304
1305 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1306 /* Select Bus Speed Mode for host */
1307 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1308 switch (uhs) {
1309 case MMC_TIMING_UHS_SDR12:
1310 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1311 break;
1312 case MMC_TIMING_UHS_SDR25:
1313 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1314 break;
1315 case MMC_TIMING_UHS_SDR50:
1316 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1317 break;
1318 case MMC_TIMING_MMC_HS400:
1319 case MMC_TIMING_MMC_HS200:
1320 case MMC_TIMING_UHS_SDR104:
1321 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1322 break;
1323 case MMC_TIMING_UHS_DDR50:
1324 case MMC_TIMING_MMC_DDR52:
1325 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1326 break;
1327 }
1328
1329 /*
1330 * When clock frequency is less than 100MHz, the feedback clock must be
1331 * provided and DLL must not be used so that tuning can be skipped. To
1332 * provide feedback clock, the mode selection can be any value less
1333 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1334 */
1335 if (host->clock <= CORE_FREQ_100MHZ) {
1336 if (uhs == MMC_TIMING_MMC_HS400 ||
1337 uhs == MMC_TIMING_MMC_HS200 ||
1338 uhs == MMC_TIMING_UHS_SDR104)
1339 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1340 /*
1341 * DLL is not required for clock <= 100MHz
1342 * Thus, make sure DLL it is disabled when not required
1343 */
1344 config = readl_relaxed(host->ioaddr +
1345 msm_offset->core_dll_config);
1346 config |= CORE_DLL_RST;
1347 writel_relaxed(config, host->ioaddr +
1348 msm_offset->core_dll_config);
1349
1350 config = readl_relaxed(host->ioaddr +
1351 msm_offset->core_dll_config);
1352 config |= CORE_DLL_PDN;
1353 writel_relaxed(config, host->ioaddr +
1354 msm_offset->core_dll_config);
1355
1356 /*
1357 * The DLL needs to be restored and CDCLP533 recalibrated
1358 * when the clock frequency is set back to 400MHz.
1359 */
1360 msm_host->calibration_done = false;
1361 }
1362
1363 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1364 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1365 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1366
1367 if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1368 sdhci_msm_hs400(host, &mmc->ios);
1369 }
1370
1371 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
1372 {
1373 struct platform_device *pdev = msm_host->pdev;
1374 int ret;
1375
1376 if (level)
1377 ret = pinctrl_pm_select_default_state(&pdev->dev);
1378 else
1379 ret = pinctrl_pm_select_sleep_state(&pdev->dev);
1380
1381 return ret;
1382 }
1383
1384 static int sdhci_msm_set_vmmc(struct mmc_host *mmc)
1385 {
1386 if (IS_ERR(mmc->supply.vmmc))
1387 return 0;
1388
1389 return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);
1390 }
1391
1392 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
1393 struct mmc_host *mmc, bool level)
1394 {
1395 int ret;
1396 struct mmc_ios ios;
1397
1398 if (msm_host->vqmmc_enabled == level)
1399 return 0;
1400
1401 if (level) {
1402 /* Set the IO voltage regulator to default voltage level */
1403 if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
1404 ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330;
1405 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
1406 ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180;
1407
1408 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1409 ret = mmc_regulator_set_vqmmc(mmc, &ios);
1410 if (ret < 0) {
1411 dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n",
1412 mmc_hostname(mmc), ret);
1413 goto out;
1414 }
1415 }
1416 ret = regulator_enable(mmc->supply.vqmmc);
1417 } else {
1418 ret = regulator_disable(mmc->supply.vqmmc);
1419 }
1420
1421 if (ret)
1422 dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n",
1423 mmc_hostname(mmc), level ? "en":"dis", ret);
1424 else
1425 msm_host->vqmmc_enabled = level;
1426 out:
1427 return ret;
1428 }
1429
1430 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
1431 struct mmc_host *mmc, bool hpm)
1432 {
1433 int load, ret;
1434
1435 load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;
1436 ret = regulator_set_load(mmc->supply.vqmmc, load);
1437 if (ret)
1438 dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n",
1439 mmc_hostname(mmc), ret);
1440 return ret;
1441 }
1442
1443 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
1444 struct mmc_host *mmc, bool level)
1445 {
1446 int ret;
1447 bool always_on;
1448
1449 if (IS_ERR(mmc->supply.vqmmc) ||
1450 (mmc->ios.power_mode == MMC_POWER_UNDEFINED))
1451 return 0;
1452 /*
1453 * For eMMC don't turn off Vqmmc, Instead just configure it in LPM
1454 * and HPM modes by setting the corresponding load.
1455 *
1456 * Till eMMC is initialized (i.e. always_on == 0), just turn on/off
1457 * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off
1458 * gets invoked. Once eMMC is initialized (i.e. always_on == 1),
1459 * Vqmmc should remain ON, So just set the load instead of turning it
1460 * off/on.
1461 */
1462 always_on = !mmc_card_is_removable(mmc) &&
1463 mmc->card && mmc_card_mmc(mmc->card);
1464
1465 if (always_on)
1466 ret = msm_config_vqmmc_mode(msm_host, mmc, level);
1467 else
1468 ret = msm_toggle_vqmmc(msm_host, mmc, level);
1469
1470 return ret;
1471 }
1472
1473 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1474 {
1475 init_waitqueue_head(&msm_host->pwr_irq_wait);
1476 }
1477
1478 static inline void sdhci_msm_complete_pwr_irq_wait(
1479 struct sdhci_msm_host *msm_host)
1480 {
1481 wake_up(&msm_host->pwr_irq_wait);
1482 }
1483
1484 /*
1485 * sdhci_msm_check_power_status API should be called when registers writes
1486 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1487 * To what state the register writes will change the IO lines should be passed
1488 * as the argument req_type. This API will check whether the IO line's state
1489 * is already the expected state and will wait for power irq only if
1490 * power irq is expected to be triggered based on the current IO line state
1491 * and expected IO line state.
1492 */
1493 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1494 {
1495 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1496 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1497 bool done = false;
1498 u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1499 const struct sdhci_msm_offset *msm_offset =
1500 msm_host->offset;
1501
1502 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1503 mmc_hostname(host->mmc), __func__, req_type,
1504 msm_host->curr_pwr_state, msm_host->curr_io_level);
1505
1506 /*
1507 * The power interrupt will not be generated for signal voltage
1508 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1509 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1510 * it as always set.
1511 */
1512 if (!msm_host->mci_removed)
1513 val = msm_host_readl(msm_host, host,
1514 msm_offset->core_generics);
1515 if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1516 !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1517 return;
1518 }
1519
1520 /*
1521 * The IRQ for request type IO High/LOW will be generated when -
1522 * there is a state change in 1.8V enable bit (bit 3) of
1523 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1524 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1525 * to set it to 3.3V before card detection happens, the
1526 * IRQ doesn't get triggered as there is no state change in this bit.
1527 * The driver already handles this case by changing the IO voltage
1528 * level to high as part of controller power up sequence. Hence, check
1529 * for host->pwr to handle a case where IO voltage high request is
1530 * issued even before controller power up.
1531 */
1532 if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1533 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1534 mmc_hostname(host->mmc), req_type);
1535 return;
1536 }
1537 if ((req_type & msm_host->curr_pwr_state) ||
1538 (req_type & msm_host->curr_io_level))
1539 done = true;
1540 /*
1541 * This is needed here to handle cases where register writes will
1542 * not change the current bus state or io level of the controller.
1543 * In this case, no power irq will be triggerred and we should
1544 * not wait.
1545 */
1546 if (!done) {
1547 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1548 msm_host->pwr_irq_flag,
1549 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1550 dev_warn(&msm_host->pdev->dev,
1551 "%s: pwr_irq for req: (%d) timed out\n",
1552 mmc_hostname(host->mmc), req_type);
1553 }
1554 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1555 __func__, req_type);
1556 }
1557
1558 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1559 {
1560 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1561 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1562 const struct sdhci_msm_offset *msm_offset =
1563 msm_host->offset;
1564
1565 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1566 mmc_hostname(host->mmc),
1567 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1568 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1569 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1570 }
1571
1572 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1573 {
1574 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1575 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1576 struct mmc_host *mmc = host->mmc;
1577 u32 irq_status, irq_ack = 0;
1578 int retry = 10, ret;
1579 u32 pwr_state = 0, io_level = 0;
1580 u32 config;
1581 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1582
1583 irq_status = msm_host_readl(msm_host, host,
1584 msm_offset->core_pwrctl_status);
1585 irq_status &= INT_MASK;
1586
1587 msm_host_writel(msm_host, irq_status, host,
1588 msm_offset->core_pwrctl_clear);
1589
1590 /*
1591 * There is a rare HW scenario where the first clear pulse could be
1592 * lost when actual reset and clear/read of status register is
1593 * happening at a time. Hence, retry for at least 10 times to make
1594 * sure status register is cleared. Otherwise, this will result in
1595 * a spurious power IRQ resulting in system instability.
1596 */
1597 while (irq_status & msm_host_readl(msm_host, host,
1598 msm_offset->core_pwrctl_status)) {
1599 if (retry == 0) {
1600 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1601 mmc_hostname(host->mmc), irq_status);
1602 sdhci_msm_dump_pwr_ctrl_regs(host);
1603 WARN_ON(1);
1604 break;
1605 }
1606 msm_host_writel(msm_host, irq_status, host,
1607 msm_offset->core_pwrctl_clear);
1608 retry--;
1609 udelay(10);
1610 }
1611
1612 /* Handle BUS ON/OFF*/
1613 if (irq_status & CORE_PWRCTL_BUS_ON) {
1614 pwr_state = REQ_BUS_ON;
1615 io_level = REQ_IO_HIGH;
1616 }
1617 if (irq_status & CORE_PWRCTL_BUS_OFF) {
1618 pwr_state = REQ_BUS_OFF;
1619 io_level = REQ_IO_LOW;
1620 }
1621
1622 if (pwr_state) {
1623 ret = sdhci_msm_set_vmmc(mmc);
1624 if (!ret)
1625 ret = sdhci_msm_set_vqmmc(msm_host, mmc,
1626 pwr_state & REQ_BUS_ON);
1627 if (!ret)
1628 ret = sdhci_msm_set_pincfg(msm_host,
1629 pwr_state & REQ_BUS_ON);
1630 if (!ret)
1631 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1632 else
1633 irq_ack |= CORE_PWRCTL_BUS_FAIL;
1634 }
1635
1636 /* Handle IO LOW/HIGH */
1637 if (irq_status & CORE_PWRCTL_IO_LOW)
1638 io_level = REQ_IO_LOW;
1639
1640 if (irq_status & CORE_PWRCTL_IO_HIGH)
1641 io_level = REQ_IO_HIGH;
1642
1643 if (io_level)
1644 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1645
1646 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) {
1647 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
1648 if (ret < 0) {
1649 dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",
1650 mmc_hostname(mmc), ret,
1651 mmc->ios.signal_voltage, mmc->ios.vdd,
1652 irq_status);
1653 irq_ack |= CORE_PWRCTL_IO_FAIL;
1654 }
1655 }
1656
1657 /*
1658 * The driver has to acknowledge the interrupt, switch voltages and
1659 * report back if it succeded or not to this register. The voltage
1660 * switches are handled by the sdhci core, so just report success.
1661 */
1662 msm_host_writel(msm_host, irq_ack, host,
1663 msm_offset->core_pwrctl_ctl);
1664
1665 /*
1666 * If we don't have info regarding the voltage levels supported by
1667 * regulators, don't change the IO PAD PWR SWITCH.
1668 */
1669 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1670 u32 new_config;
1671 /*
1672 * We should unset IO PAD PWR switch only if the register write
1673 * can set IO lines high and the regulator also switches to 3 V.
1674 * Else, we should keep the IO PAD PWR switch set.
1675 * This is applicable to certain targets where eMMC vccq supply
1676 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1677 * IO PAD PWR switch must be kept set to reflect actual
1678 * regulator voltage. This way, during initialization of
1679 * controllers with only 1.8V, we will set the IO PAD bit
1680 * without waiting for a REQ_IO_LOW.
1681 */
1682 config = readl_relaxed(host->ioaddr +
1683 msm_offset->core_vendor_spec);
1684 new_config = config;
1685
1686 if ((io_level & REQ_IO_HIGH) &&
1687 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1688 new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1689 else if ((io_level & REQ_IO_LOW) ||
1690 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1691 new_config |= CORE_IO_PAD_PWR_SWITCH;
1692
1693 if (config ^ new_config)
1694 writel_relaxed(new_config, host->ioaddr +
1695 msm_offset->core_vendor_spec);
1696 }
1697
1698 if (pwr_state)
1699 msm_host->curr_pwr_state = pwr_state;
1700 if (io_level)
1701 msm_host->curr_io_level = io_level;
1702
1703 dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1704 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1705 irq_ack);
1706 }
1707
1708 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1709 {
1710 struct sdhci_host *host = (struct sdhci_host *)data;
1711 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1712 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1713
1714 sdhci_msm_handle_pwr_irq(host, irq);
1715 msm_host->pwr_irq_flag = 1;
1716 sdhci_msm_complete_pwr_irq_wait(msm_host);
1717
1718
1719 return IRQ_HANDLED;
1720 }
1721
1722 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1723 {
1724 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1725 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1726 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1727
1728 return clk_round_rate(core_clk, ULONG_MAX);
1729 }
1730
1731 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1732 {
1733 return SDHCI_MSM_MIN_CLOCK;
1734 }
1735
1736 /*
1737 * __sdhci_msm_set_clock - sdhci_msm clock control.
1738 *
1739 * Description:
1740 * MSM controller does not use internal divider and
1741 * instead directly control the GCC clock as per
1742 * HW recommendation.
1743 **/
1744 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1745 {
1746 u16 clk;
1747 /*
1748 * Keep actual_clock as zero -
1749 * - since there is no divider used so no need of having actual_clock.
1750 * - MSM controller uses SDCLK for data timeout calculation. If
1751 * actual_clock is zero, host->clock is taken for calculation.
1752 */
1753 host->mmc->actual_clock = 0;
1754
1755 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1756
1757 if (clock == 0)
1758 return;
1759
1760 /*
1761 * MSM controller do not use clock divider.
1762 * Thus read SDHCI_CLOCK_CONTROL and only enable
1763 * clock with no divider value programmed.
1764 */
1765 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1766 sdhci_enable_clk(host, clk);
1767 }
1768
1769 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1770 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1771 {
1772 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1773 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1774
1775 if (!clock) {
1776 msm_host->clk_rate = clock;
1777 goto out;
1778 }
1779
1780 sdhci_msm_hc_select_mode(host);
1781
1782 msm_set_clock_rate_for_bus_mode(host, clock);
1783 out:
1784 __sdhci_msm_set_clock(host, clock);
1785 }
1786
1787 /*****************************************************************************\
1788 * *
1789 * MSM Command Queue Engine (CQE) *
1790 * *
1791 \*****************************************************************************/
1792
1793 static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
1794 {
1795 int cmd_error = 0;
1796 int data_error = 0;
1797
1798 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1799 return intmask;
1800
1801 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1802 return 0;
1803 }
1804
1805 static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
1806 {
1807 struct sdhci_host *host = mmc_priv(mmc);
1808 unsigned long flags;
1809 u32 ctrl;
1810
1811 /*
1812 * When CQE is halted, the legacy SDHCI path operates only
1813 * on 16-byte descriptors in 64bit mode.
1814 */
1815 if (host->flags & SDHCI_USE_64_BIT_DMA)
1816 host->desc_sz = 16;
1817
1818 spin_lock_irqsave(&host->lock, flags);
1819
1820 /*
1821 * During CQE command transfers, command complete bit gets latched.
1822 * So s/w should clear command complete interrupt status when CQE is
1823 * either halted or disabled. Otherwise unexpected SDCHI legacy
1824 * interrupt gets triggered when CQE is halted/disabled.
1825 */
1826 ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
1827 ctrl |= SDHCI_INT_RESPONSE;
1828 sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
1829 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
1830
1831 spin_unlock_irqrestore(&host->lock, flags);
1832
1833 sdhci_cqe_disable(mmc, recovery);
1834 }
1835
1836 static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
1837 .enable = sdhci_cqe_enable,
1838 .disable = sdhci_msm_cqe_disable,
1839 };
1840
1841 static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
1842 struct platform_device *pdev)
1843 {
1844 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1845 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1846 struct cqhci_host *cq_host;
1847 bool dma64;
1848 u32 cqcfg;
1849 int ret;
1850
1851 /*
1852 * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
1853 * So ensure ADMA table is allocated for 16byte descriptors.
1854 */
1855 if (host->caps & SDHCI_CAN_64BIT)
1856 host->alloc_desc_sz = 16;
1857
1858 ret = sdhci_setup_host(host);
1859 if (ret)
1860 return ret;
1861
1862 cq_host = cqhci_pltfm_init(pdev);
1863 if (IS_ERR(cq_host)) {
1864 ret = PTR_ERR(cq_host);
1865 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
1866 goto cleanup;
1867 }
1868
1869 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1870 cq_host->ops = &sdhci_msm_cqhci_ops;
1871
1872 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1873
1874 ret = cqhci_init(cq_host, host->mmc, dma64);
1875 if (ret) {
1876 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
1877 mmc_hostname(host->mmc), ret);
1878 goto cleanup;
1879 }
1880
1881 /* Disable cqe reset due to cqe enable signal */
1882 cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
1883 cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
1884 cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
1885
1886 /*
1887 * SDHC expects 12byte ADMA descriptors till CQE is enabled.
1888 * So limit desc_sz to 12 so that the data commands that are sent
1889 * during card initialization (before CQE gets enabled) would
1890 * get executed without any issues.
1891 */
1892 if (host->flags & SDHCI_USE_64_BIT_DMA)
1893 host->desc_sz = 12;
1894
1895 ret = __sdhci_add_host(host);
1896 if (ret)
1897 goto cleanup;
1898
1899 dev_info(&pdev->dev, "%s: CQE init: success\n",
1900 mmc_hostname(host->mmc));
1901 return ret;
1902
1903 cleanup:
1904 sdhci_cleanup_host(host);
1905 return ret;
1906 }
1907
1908 /*
1909 * Platform specific register write functions. This is so that, if any
1910 * register write needs to be followed up by platform specific actions,
1911 * they can be added here. These functions can go to sleep when writes
1912 * to certain registers are done.
1913 * These functions are relying on sdhci_set_ios not using spinlock.
1914 */
1915 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1916 {
1917 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1918 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1919 u32 req_type = 0;
1920
1921 switch (reg) {
1922 case SDHCI_HOST_CONTROL2:
1923 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1924 REQ_IO_HIGH;
1925 break;
1926 case SDHCI_SOFTWARE_RESET:
1927 if (host->pwr && (val & SDHCI_RESET_ALL))
1928 req_type = REQ_BUS_OFF;
1929 break;
1930 case SDHCI_POWER_CONTROL:
1931 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1932 break;
1933 case SDHCI_TRANSFER_MODE:
1934 msm_host->transfer_mode = val;
1935 break;
1936 case SDHCI_COMMAND:
1937 if (!msm_host->use_cdr)
1938 break;
1939 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1940 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
1941 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
1942 sdhci_msm_set_cdr(host, true);
1943 else
1944 sdhci_msm_set_cdr(host, false);
1945 break;
1946 }
1947
1948 if (req_type) {
1949 msm_host->pwr_irq_flag = 0;
1950 /*
1951 * Since this register write may trigger a power irq, ensure
1952 * all previous register writes are complete by this point.
1953 */
1954 mb();
1955 }
1956 return req_type;
1957 }
1958
1959 /* This function may sleep*/
1960 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1961 {
1962 u32 req_type = 0;
1963
1964 req_type = __sdhci_msm_check_write(host, val, reg);
1965 writew_relaxed(val, host->ioaddr + reg);
1966
1967 if (req_type)
1968 sdhci_msm_check_power_status(host, req_type);
1969 }
1970
1971 /* This function may sleep*/
1972 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1973 {
1974 u32 req_type = 0;
1975
1976 req_type = __sdhci_msm_check_write(host, val, reg);
1977
1978 writeb_relaxed(val, host->ioaddr + reg);
1979
1980 if (req_type)
1981 sdhci_msm_check_power_status(host, req_type);
1982 }
1983
1984 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1985 {
1986 struct mmc_host *mmc = msm_host->mmc;
1987 struct regulator *supply = mmc->supply.vqmmc;
1988 u32 caps = 0, config;
1989 struct sdhci_host *host = mmc_priv(mmc);
1990 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1991
1992 if (!IS_ERR(mmc->supply.vqmmc)) {
1993 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1994 caps |= CORE_1_8V_SUPPORT;
1995 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1996 caps |= CORE_3_0V_SUPPORT;
1997
1998 if (!caps)
1999 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
2000 mmc_hostname(mmc));
2001 }
2002
2003 if (caps) {
2004 /*
2005 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
2006 * bit can be used as required later on.
2007 */
2008 u32 io_level = msm_host->curr_io_level;
2009
2010 config = readl_relaxed(host->ioaddr +
2011 msm_offset->core_vendor_spec);
2012 config |= CORE_IO_PAD_PWR_SWITCH_EN;
2013
2014 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
2015 config &= ~CORE_IO_PAD_PWR_SWITCH;
2016 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
2017 config |= CORE_IO_PAD_PWR_SWITCH;
2018
2019 writel_relaxed(config,
2020 host->ioaddr + msm_offset->core_vendor_spec);
2021 }
2022 msm_host->caps_0 |= caps;
2023 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
2024 }
2025
2026 static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
2027 {
2028 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL))
2029 cqhci_deactivate(host->mmc);
2030 sdhci_reset(host, mask);
2031 }
2032
2033 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
2034 {
2035 int ret;
2036
2037 ret = mmc_regulator_get_supply(msm_host->mmc);
2038 if (ret)
2039 return ret;
2040
2041 sdhci_msm_set_regulator_caps(msm_host);
2042
2043 return 0;
2044 }
2045
2046 static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc,
2047 struct mmc_ios *ios)
2048 {
2049 struct sdhci_host *host = mmc_priv(mmc);
2050 u16 ctrl, status;
2051
2052 /*
2053 * Signal Voltage Switching is only applicable for Host Controllers
2054 * v3.00 and above.
2055 */
2056 if (host->version < SDHCI_SPEC_300)
2057 return 0;
2058
2059 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2060
2061 switch (ios->signal_voltage) {
2062 case MMC_SIGNAL_VOLTAGE_330:
2063 if (!(host->flags & SDHCI_SIGNALING_330))
2064 return -EINVAL;
2065
2066 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2067 ctrl &= ~SDHCI_CTRL_VDD_180;
2068 break;
2069 case MMC_SIGNAL_VOLTAGE_180:
2070 if (!(host->flags & SDHCI_SIGNALING_180))
2071 return -EINVAL;
2072
2073 /* Enable 1.8V Signal Enable in the Host Control2 register */
2074 ctrl |= SDHCI_CTRL_VDD_180;
2075 break;
2076
2077 default:
2078 return -EINVAL;
2079 }
2080
2081 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2082
2083 /* Wait for 5ms */
2084 usleep_range(5000, 5500);
2085
2086 /* regulator output should be stable within 5 ms */
2087 status = ctrl & SDHCI_CTRL_VDD_180;
2088 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2089 if ((ctrl & SDHCI_CTRL_VDD_180) == status)
2090 return 0;
2091
2092 dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n",
2093 mmc_hostname(mmc));
2094
2095 return -EAGAIN;
2096 }
2097
2098 #define DRIVER_NAME "sdhci_msm"
2099 #define SDHCI_MSM_DUMP(f, x...) \
2100 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2101
2102 static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
2103 {
2104 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2105 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2106 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2107
2108 SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
2109
2110 SDHCI_MSM_DUMP(
2111 "DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n",
2112 readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
2113 readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
2114 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
2115 SDHCI_MSM_DUMP(
2116 "DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n",
2117 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
2118 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
2119 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
2120 SDHCI_MSM_DUMP(
2121 "Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
2122 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
2123 readl_relaxed(host->ioaddr +
2124 msm_offset->core_vendor_spec_func2),
2125 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
2126 }
2127
2128 static const struct sdhci_msm_variant_ops mci_var_ops = {
2129 .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
2130 .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
2131 };
2132
2133 static const struct sdhci_msm_variant_ops v5_var_ops = {
2134 .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
2135 .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
2136 };
2137
2138 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
2139 .var_ops = &mci_var_ops,
2140 .offset = &sdhci_msm_mci_offset,
2141 };
2142
2143 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
2144 .mci_removed = true,
2145 .var_ops = &v5_var_ops,
2146 .offset = &sdhci_msm_v5_offset,
2147 };
2148
2149 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
2150 .mci_removed = true,
2151 .restore_dll_config = true,
2152 .var_ops = &v5_var_ops,
2153 .offset = &sdhci_msm_v5_offset,
2154 };
2155
2156 static const struct of_device_id sdhci_msm_dt_match[] = {
2157 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2158 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2159 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2160 {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2161 {},
2162 };
2163
2164 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
2165
2166 static const struct sdhci_ops sdhci_msm_ops = {
2167 .reset = sdhci_msm_reset,
2168 .set_clock = sdhci_msm_set_clock,
2169 .get_min_clock = sdhci_msm_get_min_clock,
2170 .get_max_clock = sdhci_msm_get_max_clock,
2171 .set_bus_width = sdhci_set_bus_width,
2172 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
2173 .write_w = sdhci_msm_writew,
2174 .write_b = sdhci_msm_writeb,
2175 .irq = sdhci_msm_cqe_irq,
2176 .dump_vendor_regs = sdhci_msm_dump_vendor_regs,
2177 .set_power = sdhci_set_power_noreg,
2178 };
2179
2180 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
2181 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
2182 SDHCI_QUIRK_SINGLE_POWER_WRITE |
2183 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
2184 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
2185
2186 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
2187 .ops = &sdhci_msm_ops,
2188 };
2189
2190 static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
2191 struct sdhci_host *host)
2192 {
2193 struct device_node *node = pdev->dev.of_node;
2194 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2195 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2196
2197 if (of_property_read_u32(node, "qcom,ddr-config",
2198 &msm_host->ddr_config))
2199 msm_host->ddr_config = DDR_CONFIG_POR_VAL;
2200
2201 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2202 }
2203
2204
2205 static int sdhci_msm_probe(struct platform_device *pdev)
2206 {
2207 struct sdhci_host *host;
2208 struct sdhci_pltfm_host *pltfm_host;
2209 struct sdhci_msm_host *msm_host;
2210 struct clk *clk;
2211 int ret;
2212 u16 host_version, core_minor;
2213 u32 core_version, config;
2214 u8 core_major;
2215 const struct sdhci_msm_offset *msm_offset;
2216 const struct sdhci_msm_variant_info *var_info;
2217 struct device_node *node = pdev->dev.of_node;
2218
2219 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
2220 if (IS_ERR(host))
2221 return PTR_ERR(host);
2222
2223 host->sdma_boundary = 0;
2224 pltfm_host = sdhci_priv(host);
2225 msm_host = sdhci_pltfm_priv(pltfm_host);
2226 msm_host->mmc = host->mmc;
2227 msm_host->pdev = pdev;
2228
2229 ret = mmc_of_parse(host->mmc);
2230 if (ret)
2231 goto pltfm_free;
2232
2233 /*
2234 * Based on the compatible string, load the required msm host info from
2235 * the data associated with the version info.
2236 */
2237 var_info = of_device_get_match_data(&pdev->dev);
2238
2239 msm_host->mci_removed = var_info->mci_removed;
2240 msm_host->restore_dll_config = var_info->restore_dll_config;
2241 msm_host->var_ops = var_info->var_ops;
2242 msm_host->offset = var_info->offset;
2243
2244 msm_offset = msm_host->offset;
2245
2246 sdhci_get_of_property(pdev);
2247 sdhci_msm_get_of_property(pdev, host);
2248
2249 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2250
2251 /* Setup SDCC bus voter clock. */
2252 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
2253 if (!IS_ERR(msm_host->bus_clk)) {
2254 /* Vote for max. clk rate for max. performance */
2255 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
2256 if (ret)
2257 goto pltfm_free;
2258 ret = clk_prepare_enable(msm_host->bus_clk);
2259 if (ret)
2260 goto pltfm_free;
2261 }
2262
2263 /* Setup main peripheral bus clock */
2264 clk = devm_clk_get(&pdev->dev, "iface");
2265 if (IS_ERR(clk)) {
2266 ret = PTR_ERR(clk);
2267 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
2268 goto bus_clk_disable;
2269 }
2270 msm_host->bulk_clks[1].clk = clk;
2271
2272 /* Setup SDC MMC clock */
2273 clk = devm_clk_get(&pdev->dev, "core");
2274 if (IS_ERR(clk)) {
2275 ret = PTR_ERR(clk);
2276 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
2277 goto bus_clk_disable;
2278 }
2279 msm_host->bulk_clks[0].clk = clk;
2280
2281 /* Check for optional interconnect paths */
2282 ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL);
2283 if (ret)
2284 goto bus_clk_disable;
2285
2286 msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core");
2287 if (IS_ERR(msm_host->opp_table)) {
2288 ret = PTR_ERR(msm_host->opp_table);
2289 goto bus_clk_disable;
2290 }
2291
2292 /* OPP table is optional */
2293 ret = dev_pm_opp_of_add_table(&pdev->dev);
2294 if (ret && ret != -ENODEV) {
2295 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
2296 goto opp_put_clkname;
2297 }
2298
2299 /* Vote for maximum clock rate for maximum performance */
2300 ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX);
2301 if (ret)
2302 dev_warn(&pdev->dev, "core clock boost failed\n");
2303
2304 clk = devm_clk_get(&pdev->dev, "cal");
2305 if (IS_ERR(clk))
2306 clk = NULL;
2307 msm_host->bulk_clks[2].clk = clk;
2308
2309 clk = devm_clk_get(&pdev->dev, "sleep");
2310 if (IS_ERR(clk))
2311 clk = NULL;
2312 msm_host->bulk_clks[3].clk = clk;
2313
2314 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2315 msm_host->bulk_clks);
2316 if (ret)
2317 goto opp_cleanup;
2318
2319 /*
2320 * xo clock is needed for FLL feature of cm_dll.
2321 * In case if xo clock is not mentioned in DT, warn and proceed.
2322 */
2323 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
2324 if (IS_ERR(msm_host->xo_clk)) {
2325 ret = PTR_ERR(msm_host->xo_clk);
2326 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
2327 }
2328
2329 if (!msm_host->mci_removed) {
2330 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
2331 if (IS_ERR(msm_host->core_mem)) {
2332 ret = PTR_ERR(msm_host->core_mem);
2333 goto clk_disable;
2334 }
2335 }
2336
2337 /* Reset the vendor spec register to power on reset state */
2338 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
2339 host->ioaddr + msm_offset->core_vendor_spec);
2340
2341 if (!msm_host->mci_removed) {
2342 /* Set HC_MODE_EN bit in HC_MODE register */
2343 msm_host_writel(msm_host, HC_MODE_EN, host,
2344 msm_offset->core_hc_mode);
2345 config = msm_host_readl(msm_host, host,
2346 msm_offset->core_hc_mode);
2347 config |= FF_CLK_SW_RST_DIS;
2348 msm_host_writel(msm_host, config, host,
2349 msm_offset->core_hc_mode);
2350 }
2351
2352 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
2353 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
2354 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
2355 SDHCI_VENDOR_VER_SHIFT));
2356
2357 core_version = msm_host_readl(msm_host, host,
2358 msm_offset->core_mci_version);
2359 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
2360 CORE_VERSION_MAJOR_SHIFT;
2361 core_minor = core_version & CORE_VERSION_MINOR_MASK;
2362 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
2363 core_version, core_major, core_minor);
2364
2365 if (core_major == 1 && core_minor >= 0x42)
2366 msm_host->use_14lpp_dll_reset = true;
2367
2368 /*
2369 * SDCC 5 controller with major version 1, minor version 0x34 and later
2370 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
2371 */
2372 if (core_major == 1 && core_minor < 0x34)
2373 msm_host->use_cdclp533 = true;
2374
2375 /*
2376 * Support for some capabilities is not advertised by newer
2377 * controller versions and must be explicitly enabled.
2378 */
2379 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
2380 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
2381 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
2382 writel_relaxed(config, host->ioaddr +
2383 msm_offset->core_vendor_spec_capabilities0);
2384 }
2385
2386 if (core_major == 1 && core_minor >= 0x49)
2387 msm_host->updated_ddr_cfg = true;
2388
2389 if (core_major == 1 && core_minor >= 0x71)
2390 msm_host->uses_tassadar_dll = true;
2391
2392 ret = sdhci_msm_register_vreg(msm_host);
2393 if (ret)
2394 goto clk_disable;
2395
2396 /*
2397 * Power on reset state may trigger power irq if previous status of
2398 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
2399 * interrupt in GIC, any pending power irq interrupt should be
2400 * acknowledged. Otherwise power irq interrupt handler would be
2401 * fired prematurely.
2402 */
2403 sdhci_msm_handle_pwr_irq(host, 0);
2404
2405 /*
2406 * Ensure that above writes are propogated before interrupt enablement
2407 * in GIC.
2408 */
2409 mb();
2410
2411 /* Setup IRQ for handling power/voltage tasks with PMIC */
2412 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2413 if (msm_host->pwr_irq < 0) {
2414 ret = msm_host->pwr_irq;
2415 goto clk_disable;
2416 }
2417
2418 sdhci_msm_init_pwr_irq_wait(msm_host);
2419 /* Enable pwr irq interrupts */
2420 msm_host_writel(msm_host, INT_MASK, host,
2421 msm_offset->core_pwrctl_mask);
2422
2423 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2424 sdhci_msm_pwr_irq, IRQF_ONESHOT,
2425 dev_name(&pdev->dev), host);
2426 if (ret) {
2427 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
2428 goto clk_disable;
2429 }
2430
2431 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
2432
2433 pm_runtime_get_noresume(&pdev->dev);
2434 pm_runtime_set_active(&pdev->dev);
2435 pm_runtime_enable(&pdev->dev);
2436 pm_runtime_set_autosuspend_delay(&pdev->dev,
2437 MSM_MMC_AUTOSUSPEND_DELAY_MS);
2438 pm_runtime_use_autosuspend(&pdev->dev);
2439
2440 host->mmc_host_ops.start_signal_voltage_switch =
2441 sdhci_msm_start_signal_voltage_switch;
2442 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
2443 if (of_property_read_bool(node, "supports-cqe"))
2444 ret = sdhci_msm_cqe_add_host(host, pdev);
2445 else
2446 ret = sdhci_add_host(host);
2447 if (ret)
2448 goto pm_runtime_disable;
2449
2450 pm_runtime_mark_last_busy(&pdev->dev);
2451 pm_runtime_put_autosuspend(&pdev->dev);
2452
2453 return 0;
2454
2455 pm_runtime_disable:
2456 pm_runtime_disable(&pdev->dev);
2457 pm_runtime_set_suspended(&pdev->dev);
2458 pm_runtime_put_noidle(&pdev->dev);
2459 clk_disable:
2460 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2461 msm_host->bulk_clks);
2462 opp_cleanup:
2463 dev_pm_opp_of_remove_table(&pdev->dev);
2464 opp_put_clkname:
2465 dev_pm_opp_put_clkname(msm_host->opp_table);
2466 bus_clk_disable:
2467 if (!IS_ERR(msm_host->bus_clk))
2468 clk_disable_unprepare(msm_host->bus_clk);
2469 pltfm_free:
2470 sdhci_pltfm_free(pdev);
2471 return ret;
2472 }
2473
2474 static int sdhci_msm_remove(struct platform_device *pdev)
2475 {
2476 struct sdhci_host *host = platform_get_drvdata(pdev);
2477 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2478 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2479 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
2480 0xffffffff);
2481
2482 sdhci_remove_host(host, dead);
2483
2484 dev_pm_opp_of_remove_table(&pdev->dev);
2485 dev_pm_opp_put_clkname(msm_host->opp_table);
2486 pm_runtime_get_sync(&pdev->dev);
2487 pm_runtime_disable(&pdev->dev);
2488 pm_runtime_put_noidle(&pdev->dev);
2489
2490 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2491 msm_host->bulk_clks);
2492 if (!IS_ERR(msm_host->bus_clk))
2493 clk_disable_unprepare(msm_host->bus_clk);
2494 sdhci_pltfm_free(pdev);
2495 return 0;
2496 }
2497
2498 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
2499 {
2500 struct sdhci_host *host = dev_get_drvdata(dev);
2501 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2502 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2503
2504 /* Drop the performance vote */
2505 dev_pm_opp_set_rate(dev, 0);
2506 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2507 msm_host->bulk_clks);
2508
2509 return 0;
2510 }
2511
2512 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2513 {
2514 struct sdhci_host *host = dev_get_drvdata(dev);
2515 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2516 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2517 int ret;
2518
2519 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2520 msm_host->bulk_clks);
2521 if (ret)
2522 return ret;
2523 /*
2524 * Whenever core-clock is gated dynamically, it's needed to
2525 * restore the SDR DLL settings when the clock is ungated.
2526 */
2527 if (msm_host->restore_dll_config && msm_host->clk_rate)
2528 ret = sdhci_msm_restore_sdr_dll_config(host);
2529
2530 dev_pm_opp_set_rate(dev, msm_host->clk_rate);
2531
2532 return ret;
2533 }
2534
2535 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2536 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2537 pm_runtime_force_resume)
2538 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2539 sdhci_msm_runtime_resume,
2540 NULL)
2541 };
2542
2543 static struct platform_driver sdhci_msm_driver = {
2544 .probe = sdhci_msm_probe,
2545 .remove = sdhci_msm_remove,
2546 .driver = {
2547 .name = "sdhci_msm",
2548 .of_match_table = sdhci_msm_dt_match,
2549 .pm = &sdhci_msm_pm_ops,
2550 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2551 },
2552 };
2553
2554 module_platform_driver(sdhci_msm_driver);
2555
2556 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2557 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support