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io_uring: ensure finish_wait() is always called in __io_uring_task_cancel()
[linux/fpc-iii.git] / drivers / tty / serial / imx.c
blob425624d794ddf70c07c991245b5af64ed4470018
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/io.h>
30 #include <linux/dma-mapping.h>
31
32 #include <asm/irq.h>
33 #include <linux/platform_data/dma-imx.h>
34
35 #include "serial_mctrl_gpio.h"
36
37 /* Register definitions */
38 #define URXD0 0x0 /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1 0x80 /* Control Register 1 */
41 #define UCR2 0x84 /* Control Register 2 */
42 #define UCR3 0x88 /* Control Register 3 */
43 #define UCR4 0x8c /* Control Register 4 */
44 #define UFCR 0x90 /* FIFO Control Register */
45 #define USR1 0x94 /* Status Register 1 */
46 #define USR2 0x98 /* Status Register 2 */
47 #define UESC 0x9c /* Escape Character Register */
48 #define UTIM 0xa0 /* Escape Timer Register */
49 #define UBIR 0xa4 /* BRM Incremental Register */
50 #define UBMR 0xa8 /* BRM Modulator Register */
51 #define UBRC 0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY (1<<15)
59 #define URXD_ERR (1<<14)
60 #define URXD_OVRRUN (1<<13)
61 #define URXD_FRMERR (1<<12)
62 #define URXD_BRK (1<<11)
63 #define URXD_PRERR (1<<10)
64 #define URXD_RX_DATA (0xFF<<0)
65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72 #define UCR1_IREN (1<<7) /* Infrared interface enable */
73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75 #define UCR1_SNDBRK (1<<4) /* Send break */
76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79 #define UCR1_DOZE (1<<1) /* Doze */
80 #define UCR1_UARTEN (1<<0) /* UART enabled */
81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83 #define UCR2_CTSC (1<<13) /* CTS pin control */
84 #define UCR2_CTS (1<<12) /* Clear to send */
85 #define UCR2_ESCEN (1<<11) /* Escape enable */
86 #define UCR2_PREN (1<<8) /* Parity enable */
87 #define UCR2_PROE (1<<7) /* Parity odd/even */
88 #define UCR2_STPB (1<<6) /* Stop */
89 #define UCR2_WS (1<<5) /* Word size */
90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93 #define UCR2_RXEN (1<<1) /* Receiver enabled */
94 #define UCR2_SRST (1<<0) /* SW reset */
95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN (1<<12) /* Parity enable */
97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR (1<<10) /* Data set ready */
99 #define UCR3_DCD (1<<9) /* Data carrier detect */
100 #define UCR3_RI (1<<8) /* Ring indicator */
101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108 #define UCR3_BPEN (1<<0) /* Preset registers enable */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC (1<<5) /* IR special case */
117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127 #define USR1_RTSS (1<<14) /* RTS pin status */
128 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129 #define USR1_RTSD (1<<12) /* RTS delta */
130 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134 #define USR1_DTRD (1<<7) /* DTR Delta */
135 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141 #define USR2_IDLE (1<<12) /* Idle condition */
142 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
144 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145 #define USR2_WAKE (1<<7) /* Wake */
146 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148 #define USR2_TXDC (1<<3) /* Transmitter complete */
149 #define USR2_BRCD (1<<2) /* Break condition */
150 #define USR2_ORE (1<<1) /* Overrun error */
151 #define USR2_RDR (1<<0) /* Recv data ready */
152 #define UTS_FRCPERR (1<<13) /* Force parity error */
153 #define UTS_LOOP (1<<12) /* Loop tx and rx */
154 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156 #define UTS_TXFULL (1<<4) /* TxFIFO full */
157 #define UTS_RXFULL (1<<3) /* RxFIFO full */
158 #define UTS_SOFTRST (1<<0) /* Software reset */
159
160 /* We've been assigned a range on the "Low-density serial ports" major */
161 #define SERIAL_IMX_MAJOR 207
162 #define MINOR_START 16
163 #define DEV_NAME "ttymxc"
164
165 /*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171 #define MCTRL_TIMEOUT (250*HZ/1000)
172
173 #define DRIVER_NAME "IMX-uart"
174
175 #define UART_NR 8
176
177 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178 enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* shadow registers */
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 unsigned int ucr4;
218 unsigned int ufcr;
219
220 /* DMA fields */
221 unsigned int dma_is_enabled:1;
222 unsigned int dma_is_rxing:1;
223 unsigned int dma_is_txing:1;
224 struct dma_chan *dma_chan_rx, *dma_chan_tx;
225 struct scatterlist rx_sgl, tx_sgl[2];
226 void *rx_buf;
227 struct circ_buf rx_ring;
228 unsigned int rx_periods;
229 dma_cookie_t rx_cookie;
230 unsigned int tx_bytes;
231 unsigned int dma_tx_nents;
232 unsigned int saved_reg[10];
233 bool context_saved;
234
235 enum imx_tx_state tx_state;
236 struct hrtimer trigger_start_tx;
237 struct hrtimer trigger_stop_tx;
238 };
239
240 struct imx_port_ucrs {
241 unsigned int ucr1;
242 unsigned int ucr2;
243 unsigned int ucr3;
244 };
245
246 static struct imx_uart_data imx_uart_devdata[] = {
247 [IMX1_UART] = {
248 .uts_reg = IMX1_UTS,
249 .devtype = IMX1_UART,
250 },
251 [IMX21_UART] = {
252 .uts_reg = IMX21_UTS,
253 .devtype = IMX21_UART,
254 },
255 [IMX53_UART] = {
256 .uts_reg = IMX21_UTS,
257 .devtype = IMX53_UART,
258 },
259 [IMX6Q_UART] = {
260 .uts_reg = IMX21_UTS,
261 .devtype = IMX6Q_UART,
262 },
263 };
264
265 static const struct of_device_id imx_uart_dt_ids[] = {
266 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
267 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
268 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
269 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
270 { /* sentinel */ }
271 };
272 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
273
274 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
275 {
276 switch (offset) {
277 case UCR1:
278 sport->ucr1 = val;
279 break;
280 case UCR2:
281 sport->ucr2 = val;
282 break;
283 case UCR3:
284 sport->ucr3 = val;
285 break;
286 case UCR4:
287 sport->ucr4 = val;
288 break;
289 case UFCR:
290 sport->ufcr = val;
291 break;
292 default:
293 break;
294 }
295 writel(val, sport->port.membase + offset);
296 }
297
298 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
299 {
300 switch (offset) {
301 case UCR1:
302 return sport->ucr1;
303 break;
304 case UCR2:
305 /*
306 * UCR2_SRST is the only bit in the cached registers that might
307 * differ from the value that was last written. As it only
308 * automatically becomes one after being cleared, reread
309 * conditionally.
310 */
311 if (!(sport->ucr2 & UCR2_SRST))
312 sport->ucr2 = readl(sport->port.membase + offset);
313 return sport->ucr2;
314 break;
315 case UCR3:
316 return sport->ucr3;
317 break;
318 case UCR4:
319 return sport->ucr4;
320 break;
321 case UFCR:
322 return sport->ufcr;
323 break;
324 default:
325 return readl(sport->port.membase + offset);
326 }
327 }
328
329 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
330 {
331 return sport->devdata->uts_reg;
332 }
333
334 static inline int imx_uart_is_imx1(struct imx_port *sport)
335 {
336 return sport->devdata->devtype == IMX1_UART;
337 }
338
339 static inline int imx_uart_is_imx21(struct imx_port *sport)
340 {
341 return sport->devdata->devtype == IMX21_UART;
342 }
343
344 static inline int imx_uart_is_imx53(struct imx_port *sport)
345 {
346 return sport->devdata->devtype == IMX53_UART;
347 }
348
349 static inline int imx_uart_is_imx6q(struct imx_port *sport)
350 {
351 return sport->devdata->devtype == IMX6Q_UART;
352 }
353 /*
354 * Save and restore functions for UCR1, UCR2 and UCR3 registers
355 */
356 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
357 static void imx_uart_ucrs_save(struct imx_port *sport,
358 struct imx_port_ucrs *ucr)
359 {
360 /* save control registers */
361 ucr->ucr1 = imx_uart_readl(sport, UCR1);
362 ucr->ucr2 = imx_uart_readl(sport, UCR2);
363 ucr->ucr3 = imx_uart_readl(sport, UCR3);
364 }
365
366 static void imx_uart_ucrs_restore(struct imx_port *sport,
367 struct imx_port_ucrs *ucr)
368 {
369 /* restore control registers */
370 imx_uart_writel(sport, ucr->ucr1, UCR1);
371 imx_uart_writel(sport, ucr->ucr2, UCR2);
372 imx_uart_writel(sport, ucr->ucr3, UCR3);
373 }
374 #endif
375
376 /* called with port.lock taken and irqs caller dependent */
377 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
378 {
379 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
380
381 sport->port.mctrl |= TIOCM_RTS;
382 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
383 }
384
385 /* called with port.lock taken and irqs caller dependent */
386 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
387 {
388 *ucr2 &= ~UCR2_CTSC;
389 *ucr2 |= UCR2_CTS;
390
391 sport->port.mctrl &= ~TIOCM_RTS;
392 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
393 }
394
395 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
396 {
397 long sec = msec / MSEC_PER_SEC;
398 long nsec = (msec % MSEC_PER_SEC) * 1000000;
399 ktime_t t = ktime_set(sec, nsec);
400
401 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
402 }
403
404 /* called with port.lock taken and irqs off */
405 static void imx_uart_start_rx(struct uart_port *port)
406 {
407 struct imx_port *sport = (struct imx_port *)port;
408 unsigned int ucr1, ucr2;
409
410 ucr1 = imx_uart_readl(sport, UCR1);
411 ucr2 = imx_uart_readl(sport, UCR2);
412
413 ucr2 |= UCR2_RXEN;
414
415 if (sport->dma_is_enabled) {
416 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
417 } else {
418 ucr1 |= UCR1_RRDYEN;
419 ucr2 |= UCR2_ATEN;
420 }
421
422 /* Write UCR2 first as it includes RXEN */
423 imx_uart_writel(sport, ucr2, UCR2);
424 imx_uart_writel(sport, ucr1, UCR1);
425 }
426
427 /* called with port.lock taken and irqs off */
428 static void imx_uart_stop_tx(struct uart_port *port)
429 {
430 struct imx_port *sport = (struct imx_port *)port;
431 u32 ucr1, ucr4, usr2;
432
433 if (sport->tx_state == OFF)
434 return;
435
436 /*
437 * We are maybe in the SMP context, so if the DMA TX thread is running
438 * on other cpu, we have to wait for it to finish.
439 */
440 if (sport->dma_is_txing)
441 return;
442
443 ucr1 = imx_uart_readl(sport, UCR1);
444 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
445
446 usr2 = imx_uart_readl(sport, USR2);
447 if (!(usr2 & USR2_TXDC)) {
448 /* The shifter is still busy, so retry once TC triggers */
449 return;
450 }
451
452 ucr4 = imx_uart_readl(sport, UCR4);
453 ucr4 &= ~UCR4_TCEN;
454 imx_uart_writel(sport, ucr4, UCR4);
455
456 /* in rs485 mode disable transmitter */
457 if (port->rs485.flags & SER_RS485_ENABLED) {
458 if (sport->tx_state == SEND) {
459 sport->tx_state = WAIT_AFTER_SEND;
460 start_hrtimer_ms(&sport->trigger_stop_tx,
461 port->rs485.delay_rts_after_send);
462 return;
463 }
464
465 if (sport->tx_state == WAIT_AFTER_RTS ||
466 sport->tx_state == WAIT_AFTER_SEND) {
467 u32 ucr2;
468
469 hrtimer_try_to_cancel(&sport->trigger_start_tx);
470
471 ucr2 = imx_uart_readl(sport, UCR2);
472 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
473 imx_uart_rts_active(sport, &ucr2);
474 else
475 imx_uart_rts_inactive(sport, &ucr2);
476 imx_uart_writel(sport, ucr2, UCR2);
477
478 imx_uart_start_rx(port);
479
480 sport->tx_state = OFF;
481 }
482 } else {
483 sport->tx_state = OFF;
484 }
485 }
486
487 /* called with port.lock taken and irqs off */
488 static void imx_uart_stop_rx(struct uart_port *port)
489 {
490 struct imx_port *sport = (struct imx_port *)port;
491 u32 ucr1, ucr2;
492
493 ucr1 = imx_uart_readl(sport, UCR1);
494 ucr2 = imx_uart_readl(sport, UCR2);
495
496 if (sport->dma_is_enabled) {
497 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
498 } else {
499 ucr1 &= ~UCR1_RRDYEN;
500 ucr2 &= ~UCR2_ATEN;
501 }
502 imx_uart_writel(sport, ucr1, UCR1);
503
504 ucr2 &= ~UCR2_RXEN;
505 imx_uart_writel(sport, ucr2, UCR2);
506 }
507
508 /* called with port.lock taken and irqs off */
509 static void imx_uart_enable_ms(struct uart_port *port)
510 {
511 struct imx_port *sport = (struct imx_port *)port;
512
513 mod_timer(&sport->timer, jiffies);
514
515 mctrl_gpio_enable_ms(sport->gpios);
516 }
517
518 static void imx_uart_dma_tx(struct imx_port *sport);
519
520 /* called with port.lock taken and irqs off */
521 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
522 {
523 struct circ_buf *xmit = &sport->port.state->xmit;
524
525 if (sport->port.x_char) {
526 /* Send next char */
527 imx_uart_writel(sport, sport->port.x_char, URTX0);
528 sport->port.icount.tx++;
529 sport->port.x_char = 0;
530 return;
531 }
532
533 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
534 imx_uart_stop_tx(&sport->port);
535 return;
536 }
537
538 if (sport->dma_is_enabled) {
539 u32 ucr1;
540 /*
541 * We've just sent a X-char Ensure the TX DMA is enabled
542 * and the TX IRQ is disabled.
543 **/
544 ucr1 = imx_uart_readl(sport, UCR1);
545 ucr1 &= ~UCR1_TRDYEN;
546 if (sport->dma_is_txing) {
547 ucr1 |= UCR1_TXDMAEN;
548 imx_uart_writel(sport, ucr1, UCR1);
549 } else {
550 imx_uart_writel(sport, ucr1, UCR1);
551 imx_uart_dma_tx(sport);
552 }
553
554 return;
555 }
556
557 while (!uart_circ_empty(xmit) &&
558 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
559 /* send xmit->buf[xmit->tail]
560 * out the port here */
561 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
562 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
563 sport->port.icount.tx++;
564 }
565
566 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
567 uart_write_wakeup(&sport->port);
568
569 if (uart_circ_empty(xmit))
570 imx_uart_stop_tx(&sport->port);
571 }
572
573 static void imx_uart_dma_tx_callback(void *data)
574 {
575 struct imx_port *sport = data;
576 struct scatterlist *sgl = &sport->tx_sgl[0];
577 struct circ_buf *xmit = &sport->port.state->xmit;
578 unsigned long flags;
579 u32 ucr1;
580
581 spin_lock_irqsave(&sport->port.lock, flags);
582
583 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
584
585 ucr1 = imx_uart_readl(sport, UCR1);
586 ucr1 &= ~UCR1_TXDMAEN;
587 imx_uart_writel(sport, ucr1, UCR1);
588
589 /* update the stat */
590 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
591 sport->port.icount.tx += sport->tx_bytes;
592
593 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
594
595 sport->dma_is_txing = 0;
596
597 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
598 uart_write_wakeup(&sport->port);
599
600 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
601 imx_uart_dma_tx(sport);
602 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
603 u32 ucr4 = imx_uart_readl(sport, UCR4);
604 ucr4 |= UCR4_TCEN;
605 imx_uart_writel(sport, ucr4, UCR4);
606 }
607
608 spin_unlock_irqrestore(&sport->port.lock, flags);
609 }
610
611 /* called with port.lock taken and irqs off */
612 static void imx_uart_dma_tx(struct imx_port *sport)
613 {
614 struct circ_buf *xmit = &sport->port.state->xmit;
615 struct scatterlist *sgl = sport->tx_sgl;
616 struct dma_async_tx_descriptor *desc;
617 struct dma_chan *chan = sport->dma_chan_tx;
618 struct device *dev = sport->port.dev;
619 u32 ucr1, ucr4;
620 int ret;
621
622 if (sport->dma_is_txing)
623 return;
624
625 ucr4 = imx_uart_readl(sport, UCR4);
626 ucr4 &= ~UCR4_TCEN;
627 imx_uart_writel(sport, ucr4, UCR4);
628
629 sport->tx_bytes = uart_circ_chars_pending(xmit);
630
631 if (xmit->tail < xmit->head || xmit->head == 0) {
632 sport->dma_tx_nents = 1;
633 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
634 } else {
635 sport->dma_tx_nents = 2;
636 sg_init_table(sgl, 2);
637 sg_set_buf(sgl, xmit->buf + xmit->tail,
638 UART_XMIT_SIZE - xmit->tail);
639 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
640 }
641
642 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
643 if (ret == 0) {
644 dev_err(dev, "DMA mapping error for TX.\n");
645 return;
646 }
647 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
648 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
649 if (!desc) {
650 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
651 DMA_TO_DEVICE);
652 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
653 return;
654 }
655 desc->callback = imx_uart_dma_tx_callback;
656 desc->callback_param = sport;
657
658 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
659 uart_circ_chars_pending(xmit));
660
661 ucr1 = imx_uart_readl(sport, UCR1);
662 ucr1 |= UCR1_TXDMAEN;
663 imx_uart_writel(sport, ucr1, UCR1);
664
665 /* fire it */
666 sport->dma_is_txing = 1;
667 dmaengine_submit(desc);
668 dma_async_issue_pending(chan);
669 return;
670 }
671
672 /* called with port.lock taken and irqs off */
673 static void imx_uart_start_tx(struct uart_port *port)
674 {
675 struct imx_port *sport = (struct imx_port *)port;
676 u32 ucr1;
677
678 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
679 return;
680
681 /*
682 * We cannot simply do nothing here if sport->tx_state == SEND already
683 * because UCR1_TXMPTYEN might already have been cleared in
684 * imx_uart_stop_tx(), but tx_state is still SEND.
685 */
686
687 if (port->rs485.flags & SER_RS485_ENABLED) {
688 if (sport->tx_state == OFF) {
689 u32 ucr2 = imx_uart_readl(sport, UCR2);
690 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
691 imx_uart_rts_active(sport, &ucr2);
692 else
693 imx_uart_rts_inactive(sport, &ucr2);
694 imx_uart_writel(sport, ucr2, UCR2);
695
696 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
697 imx_uart_stop_rx(port);
698
699 sport->tx_state = WAIT_AFTER_RTS;
700 start_hrtimer_ms(&sport->trigger_start_tx,
701 port->rs485.delay_rts_before_send);
702 return;
703 }
704
705 if (sport->tx_state == WAIT_AFTER_SEND
706 || sport->tx_state == WAIT_AFTER_RTS) {
707
708 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
709
710 /*
711 * Enable transmitter and shifter empty irq only if DMA
712 * is off. In the DMA case this is done in the
713 * tx-callback.
714 */
715 if (!sport->dma_is_enabled) {
716 u32 ucr4 = imx_uart_readl(sport, UCR4);
717 ucr4 |= UCR4_TCEN;
718 imx_uart_writel(sport, ucr4, UCR4);
719 }
720
721 sport->tx_state = SEND;
722 }
723 } else {
724 sport->tx_state = SEND;
725 }
726
727 if (!sport->dma_is_enabled) {
728 ucr1 = imx_uart_readl(sport, UCR1);
729 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
730 }
731
732 if (sport->dma_is_enabled) {
733 if (sport->port.x_char) {
734 /* We have X-char to send, so enable TX IRQ and
735 * disable TX DMA to let TX interrupt to send X-char */
736 ucr1 = imx_uart_readl(sport, UCR1);
737 ucr1 &= ~UCR1_TXDMAEN;
738 ucr1 |= UCR1_TRDYEN;
739 imx_uart_writel(sport, ucr1, UCR1);
740 return;
741 }
742
743 if (!uart_circ_empty(&port->state->xmit) &&
744 !uart_tx_stopped(port))
745 imx_uart_dma_tx(sport);
746 return;
747 }
748 }
749
750 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
751 {
752 struct imx_port *sport = dev_id;
753 u32 usr1;
754
755 imx_uart_writel(sport, USR1_RTSD, USR1);
756 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
757 uart_handle_cts_change(&sport->port, !!usr1);
758 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
759
760 return IRQ_HANDLED;
761 }
762
763 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
764 {
765 struct imx_port *sport = dev_id;
766 irqreturn_t ret;
767
768 spin_lock(&sport->port.lock);
769
770 ret = __imx_uart_rtsint(irq, dev_id);
771
772 spin_unlock(&sport->port.lock);
773
774 return ret;
775 }
776
777 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
778 {
779 struct imx_port *sport = dev_id;
780
781 spin_lock(&sport->port.lock);
782 imx_uart_transmit_buffer(sport);
783 spin_unlock(&sport->port.lock);
784 return IRQ_HANDLED;
785 }
786
787 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
788 {
789 struct imx_port *sport = dev_id;
790 unsigned int rx, flg, ignored = 0;
791 struct tty_port *port = &sport->port.state->port;
792
793 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
794 u32 usr2;
795
796 flg = TTY_NORMAL;
797 sport->port.icount.rx++;
798
799 rx = imx_uart_readl(sport, URXD0);
800
801 usr2 = imx_uart_readl(sport, USR2);
802 if (usr2 & USR2_BRCD) {
803 imx_uart_writel(sport, USR2_BRCD, USR2);
804 if (uart_handle_break(&sport->port))
805 continue;
806 }
807
808 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
809 continue;
810
811 if (unlikely(rx & URXD_ERR)) {
812 if (rx & URXD_BRK)
813 sport->port.icount.brk++;
814 else if (rx & URXD_PRERR)
815 sport->port.icount.parity++;
816 else if (rx & URXD_FRMERR)
817 sport->port.icount.frame++;
818 if (rx & URXD_OVRRUN)
819 sport->port.icount.overrun++;
820
821 if (rx & sport->port.ignore_status_mask) {
822 if (++ignored > 100)
823 goto out;
824 continue;
825 }
826
827 rx &= (sport->port.read_status_mask | 0xFF);
828
829 if (rx & URXD_BRK)
830 flg = TTY_BREAK;
831 else if (rx & URXD_PRERR)
832 flg = TTY_PARITY;
833 else if (rx & URXD_FRMERR)
834 flg = TTY_FRAME;
835 if (rx & URXD_OVRRUN)
836 flg = TTY_OVERRUN;
837
838 sport->port.sysrq = 0;
839 }
840
841 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
842 goto out;
843
844 if (tty_insert_flip_char(port, rx, flg) == 0)
845 sport->port.icount.buf_overrun++;
846 }
847
848 out:
849 tty_flip_buffer_push(port);
850
851 return IRQ_HANDLED;
852 }
853
854 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
855 {
856 struct imx_port *sport = dev_id;
857 irqreturn_t ret;
858
859 spin_lock(&sport->port.lock);
860
861 ret = __imx_uart_rxint(irq, dev_id);
862
863 spin_unlock(&sport->port.lock);
864
865 return ret;
866 }
867
868 static void imx_uart_clear_rx_errors(struct imx_port *sport);
869
870 /*
871 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
872 */
873 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
874 {
875 unsigned int tmp = TIOCM_DSR;
876 unsigned usr1 = imx_uart_readl(sport, USR1);
877 unsigned usr2 = imx_uart_readl(sport, USR2);
878
879 if (usr1 & USR1_RTSS)
880 tmp |= TIOCM_CTS;
881
882 /* in DCE mode DCDIN is always 0 */
883 if (!(usr2 & USR2_DCDIN))
884 tmp |= TIOCM_CAR;
885
886 if (sport->dte_mode)
887 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
888 tmp |= TIOCM_RI;
889
890 return tmp;
891 }
892
893 /*
894 * Handle any change of modem status signal since we were last called.
895 */
896 static void imx_uart_mctrl_check(struct imx_port *sport)
897 {
898 unsigned int status, changed;
899
900 status = imx_uart_get_hwmctrl(sport);
901 changed = status ^ sport->old_status;
902
903 if (changed == 0)
904 return;
905
906 sport->old_status = status;
907
908 if (changed & TIOCM_RI && status & TIOCM_RI)
909 sport->port.icount.rng++;
910 if (changed & TIOCM_DSR)
911 sport->port.icount.dsr++;
912 if (changed & TIOCM_CAR)
913 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
914 if (changed & TIOCM_CTS)
915 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
916
917 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
918 }
919
920 static irqreturn_t imx_uart_int(int irq, void *dev_id)
921 {
922 struct imx_port *sport = dev_id;
923 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
924 irqreturn_t ret = IRQ_NONE;
925 unsigned long flags = 0;
926
927 /*
928 * IRQs might not be disabled upon entering this interrupt handler,
929 * e.g. when interrupt handlers are forced to be threaded. To support
930 * this scenario as well, disable IRQs when acquiring the spinlock.
931 */
932 spin_lock_irqsave(&sport->port.lock, flags);
933
934 usr1 = imx_uart_readl(sport, USR1);
935 usr2 = imx_uart_readl(sport, USR2);
936 ucr1 = imx_uart_readl(sport, UCR1);
937 ucr2 = imx_uart_readl(sport, UCR2);
938 ucr3 = imx_uart_readl(sport, UCR3);
939 ucr4 = imx_uart_readl(sport, UCR4);
940
941 /*
942 * Even if a condition is true that can trigger an irq only handle it if
943 * the respective irq source is enabled. This prevents some undesired
944 * actions, for example if a character that sits in the RX FIFO and that
945 * should be fetched via DMA is tried to be fetched using PIO. Or the
946 * receiver is currently off and so reading from URXD0 results in an
947 * exception. So just mask the (raw) status bits for disabled irqs.
948 */
949 if ((ucr1 & UCR1_RRDYEN) == 0)
950 usr1 &= ~USR1_RRDY;
951 if ((ucr2 & UCR2_ATEN) == 0)
952 usr1 &= ~USR1_AGTIM;
953 if ((ucr1 & UCR1_TRDYEN) == 0)
954 usr1 &= ~USR1_TRDY;
955 if ((ucr4 & UCR4_TCEN) == 0)
956 usr2 &= ~USR2_TXDC;
957 if ((ucr3 & UCR3_DTRDEN) == 0)
958 usr1 &= ~USR1_DTRD;
959 if ((ucr1 & UCR1_RTSDEN) == 0)
960 usr1 &= ~USR1_RTSD;
961 if ((ucr3 & UCR3_AWAKEN) == 0)
962 usr1 &= ~USR1_AWAKE;
963 if ((ucr4 & UCR4_OREN) == 0)
964 usr2 &= ~USR2_ORE;
965
966 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
967 imx_uart_writel(sport, USR1_AGTIM, USR1);
968
969 __imx_uart_rxint(irq, dev_id);
970 ret = IRQ_HANDLED;
971 }
972
973 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
974 imx_uart_transmit_buffer(sport);
975 ret = IRQ_HANDLED;
976 }
977
978 if (usr1 & USR1_DTRD) {
979 imx_uart_writel(sport, USR1_DTRD, USR1);
980
981 imx_uart_mctrl_check(sport);
982
983 ret = IRQ_HANDLED;
984 }
985
986 if (usr1 & USR1_RTSD) {
987 __imx_uart_rtsint(irq, dev_id);
988 ret = IRQ_HANDLED;
989 }
990
991 if (usr1 & USR1_AWAKE) {
992 imx_uart_writel(sport, USR1_AWAKE, USR1);
993 ret = IRQ_HANDLED;
994 }
995
996 if (usr2 & USR2_ORE) {
997 sport->port.icount.overrun++;
998 imx_uart_writel(sport, USR2_ORE, USR2);
999 ret = IRQ_HANDLED;
1000 }
1001
1002 spin_unlock_irqrestore(&sport->port.lock, flags);
1003
1004 return ret;
1005 }
1006
1007 /*
1008 * Return TIOCSER_TEMT when transmitter is not busy.
1009 */
1010 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1011 {
1012 struct imx_port *sport = (struct imx_port *)port;
1013 unsigned int ret;
1014
1015 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1016
1017 /* If the TX DMA is working, return 0. */
1018 if (sport->dma_is_txing)
1019 ret = 0;
1020
1021 return ret;
1022 }
1023
1024 /* called with port.lock taken and irqs off */
1025 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1026 {
1027 struct imx_port *sport = (struct imx_port *)port;
1028 unsigned int ret = imx_uart_get_hwmctrl(sport);
1029
1030 mctrl_gpio_get(sport->gpios, &ret);
1031
1032 return ret;
1033 }
1034
1035 /* called with port.lock taken and irqs off */
1036 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1037 {
1038 struct imx_port *sport = (struct imx_port *)port;
1039 u32 ucr3, uts;
1040
1041 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1042 u32 ucr2;
1043
1044 /*
1045 * Turn off autoRTS if RTS is lowered and restore autoRTS
1046 * setting if RTS is raised.
1047 */
1048 ucr2 = imx_uart_readl(sport, UCR2);
1049 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1050 if (mctrl & TIOCM_RTS) {
1051 ucr2 |= UCR2_CTS;
1052 /*
1053 * UCR2_IRTS is unset if and only if the port is
1054 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1055 * to get the state to restore to.
1056 */
1057 if (!(ucr2 & UCR2_IRTS))
1058 ucr2 |= UCR2_CTSC;
1059 }
1060 imx_uart_writel(sport, ucr2, UCR2);
1061 }
1062
1063 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1064 if (!(mctrl & TIOCM_DTR))
1065 ucr3 |= UCR3_DSR;
1066 imx_uart_writel(sport, ucr3, UCR3);
1067
1068 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1069 if (mctrl & TIOCM_LOOP)
1070 uts |= UTS_LOOP;
1071 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1072
1073 mctrl_gpio_set(sport->gpios, mctrl);
1074 }
1075
1076 /*
1077 * Interrupts always disabled.
1078 */
1079 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1080 {
1081 struct imx_port *sport = (struct imx_port *)port;
1082 unsigned long flags;
1083 u32 ucr1;
1084
1085 spin_lock_irqsave(&sport->port.lock, flags);
1086
1087 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1088
1089 if (break_state != 0)
1090 ucr1 |= UCR1_SNDBRK;
1091
1092 imx_uart_writel(sport, ucr1, UCR1);
1093
1094 spin_unlock_irqrestore(&sport->port.lock, flags);
1095 }
1096
1097 /*
1098 * This is our per-port timeout handler, for checking the
1099 * modem status signals.
1100 */
1101 static void imx_uart_timeout(struct timer_list *t)
1102 {
1103 struct imx_port *sport = from_timer(sport, t, timer);
1104 unsigned long flags;
1105
1106 if (sport->port.state) {
1107 spin_lock_irqsave(&sport->port.lock, flags);
1108 imx_uart_mctrl_check(sport);
1109 spin_unlock_irqrestore(&sport->port.lock, flags);
1110
1111 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1112 }
1113 }
1114
1115 /*
1116 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1117 * [1] the RX DMA buffer is full.
1118 * [2] the aging timer expires
1119 *
1120 * Condition [2] is triggered when a character has been sitting in the FIFO
1121 * for at least 8 byte durations.
1122 */
1123 static void imx_uart_dma_rx_callback(void *data)
1124 {
1125 struct imx_port *sport = data;
1126 struct dma_chan *chan = sport->dma_chan_rx;
1127 struct scatterlist *sgl = &sport->rx_sgl;
1128 struct tty_port *port = &sport->port.state->port;
1129 struct dma_tx_state state;
1130 struct circ_buf *rx_ring = &sport->rx_ring;
1131 enum dma_status status;
1132 unsigned int w_bytes = 0;
1133 unsigned int r_bytes;
1134 unsigned int bd_size;
1135
1136 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1137
1138 if (status == DMA_ERROR) {
1139 imx_uart_clear_rx_errors(sport);
1140 return;
1141 }
1142
1143 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1144
1145 /*
1146 * The state-residue variable represents the empty space
1147 * relative to the entire buffer. Taking this in consideration
1148 * the head is always calculated base on the buffer total
1149 * length - DMA transaction residue. The UART script from the
1150 * SDMA firmware will jump to the next buffer descriptor,
1151 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1152 * Taking this in consideration the tail is always at the
1153 * beginning of the buffer descriptor that contains the head.
1154 */
1155
1156 /* Calculate the head */
1157 rx_ring->head = sg_dma_len(sgl) - state.residue;
1158
1159 /* Calculate the tail. */
1160 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1161 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1162
1163 if (rx_ring->head <= sg_dma_len(sgl) &&
1164 rx_ring->head > rx_ring->tail) {
1165
1166 /* Move data from tail to head */
1167 r_bytes = rx_ring->head - rx_ring->tail;
1168
1169 /* CPU claims ownership of RX DMA buffer */
1170 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1171 DMA_FROM_DEVICE);
1172
1173 w_bytes = tty_insert_flip_string(port,
1174 sport->rx_buf + rx_ring->tail, r_bytes);
1175
1176 /* UART retrieves ownership of RX DMA buffer */
1177 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1178 DMA_FROM_DEVICE);
1179
1180 if (w_bytes != r_bytes)
1181 sport->port.icount.buf_overrun++;
1182
1183 sport->port.icount.rx += w_bytes;
1184 } else {
1185 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1186 WARN_ON(rx_ring->head <= rx_ring->tail);
1187 }
1188 }
1189
1190 if (w_bytes) {
1191 tty_flip_buffer_push(port);
1192 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1193 }
1194 }
1195
1196 /* RX DMA buffer periods */
1197 #define RX_DMA_PERIODS 16
1198 #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4)
1199
1200 static int imx_uart_start_rx_dma(struct imx_port *sport)
1201 {
1202 struct scatterlist *sgl = &sport->rx_sgl;
1203 struct dma_chan *chan = sport->dma_chan_rx;
1204 struct device *dev = sport->port.dev;
1205 struct dma_async_tx_descriptor *desc;
1206 int ret;
1207
1208 sport->rx_ring.head = 0;
1209 sport->rx_ring.tail = 0;
1210 sport->rx_periods = RX_DMA_PERIODS;
1211
1212 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1213 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1214 if (ret == 0) {
1215 dev_err(dev, "DMA mapping error for RX.\n");
1216 return -EINVAL;
1217 }
1218
1219 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1220 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1221 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1222
1223 if (!desc) {
1224 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1225 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1226 return -EINVAL;
1227 }
1228 desc->callback = imx_uart_dma_rx_callback;
1229 desc->callback_param = sport;
1230
1231 dev_dbg(dev, "RX: prepare for the DMA.\n");
1232 sport->dma_is_rxing = 1;
1233 sport->rx_cookie = dmaengine_submit(desc);
1234 dma_async_issue_pending(chan);
1235 return 0;
1236 }
1237
1238 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1239 {
1240 struct tty_port *port = &sport->port.state->port;
1241 u32 usr1, usr2;
1242
1243 usr1 = imx_uart_readl(sport, USR1);
1244 usr2 = imx_uart_readl(sport, USR2);
1245
1246 if (usr2 & USR2_BRCD) {
1247 sport->port.icount.brk++;
1248 imx_uart_writel(sport, USR2_BRCD, USR2);
1249 uart_handle_break(&sport->port);
1250 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1251 sport->port.icount.buf_overrun++;
1252 tty_flip_buffer_push(port);
1253 } else {
1254 if (usr1 & USR1_FRAMERR) {
1255 sport->port.icount.frame++;
1256 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1257 } else if (usr1 & USR1_PARITYERR) {
1258 sport->port.icount.parity++;
1259 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1260 }
1261 }
1262
1263 if (usr2 & USR2_ORE) {
1264 sport->port.icount.overrun++;
1265 imx_uart_writel(sport, USR2_ORE, USR2);
1266 }
1267
1268 }
1269
1270 #define TXTL_DEFAULT 2 /* reset default */
1271 #define RXTL_DEFAULT 1 /* reset default */
1272 #define TXTL_DMA 8 /* DMA burst setting */
1273 #define RXTL_DMA 9 /* DMA burst setting */
1274
1275 static void imx_uart_setup_ufcr(struct imx_port *sport,
1276 unsigned char txwl, unsigned char rxwl)
1277 {
1278 unsigned int val;
1279
1280 /* set receiver / transmitter trigger level */
1281 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1282 val |= txwl << UFCR_TXTL_SHF | rxwl;
1283 imx_uart_writel(sport, val, UFCR);
1284 }
1285
1286 static void imx_uart_dma_exit(struct imx_port *sport)
1287 {
1288 if (sport->dma_chan_rx) {
1289 dmaengine_terminate_sync(sport->dma_chan_rx);
1290 dma_release_channel(sport->dma_chan_rx);
1291 sport->dma_chan_rx = NULL;
1292 sport->rx_cookie = -EINVAL;
1293 kfree(sport->rx_buf);
1294 sport->rx_buf = NULL;
1295 }
1296
1297 if (sport->dma_chan_tx) {
1298 dmaengine_terminate_sync(sport->dma_chan_tx);
1299 dma_release_channel(sport->dma_chan_tx);
1300 sport->dma_chan_tx = NULL;
1301 }
1302 }
1303
1304 static int imx_uart_dma_init(struct imx_port *sport)
1305 {
1306 struct dma_slave_config slave_config = {};
1307 struct device *dev = sport->port.dev;
1308 int ret;
1309
1310 /* Prepare for RX : */
1311 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1312 if (!sport->dma_chan_rx) {
1313 dev_dbg(dev, "cannot get the DMA channel.\n");
1314 ret = -EINVAL;
1315 goto err;
1316 }
1317
1318 slave_config.direction = DMA_DEV_TO_MEM;
1319 slave_config.src_addr = sport->port.mapbase + URXD0;
1320 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1321 /* one byte less than the watermark level to enable the aging timer */
1322 slave_config.src_maxburst = RXTL_DMA - 1;
1323 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1324 if (ret) {
1325 dev_err(dev, "error in RX dma configuration.\n");
1326 goto err;
1327 }
1328
1329 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1330 if (!sport->rx_buf) {
1331 ret = -ENOMEM;
1332 goto err;
1333 }
1334 sport->rx_ring.buf = sport->rx_buf;
1335
1336 /* Prepare for TX : */
1337 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1338 if (!sport->dma_chan_tx) {
1339 dev_err(dev, "cannot get the TX DMA channel!\n");
1340 ret = -EINVAL;
1341 goto err;
1342 }
1343
1344 slave_config.direction = DMA_MEM_TO_DEV;
1345 slave_config.dst_addr = sport->port.mapbase + URTX0;
1346 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1347 slave_config.dst_maxburst = TXTL_DMA;
1348 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1349 if (ret) {
1350 dev_err(dev, "error in TX dma configuration.");
1351 goto err;
1352 }
1353
1354 return 0;
1355 err:
1356 imx_uart_dma_exit(sport);
1357 return ret;
1358 }
1359
1360 static void imx_uart_enable_dma(struct imx_port *sport)
1361 {
1362 u32 ucr1;
1363
1364 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1365
1366 /* set UCR1 */
1367 ucr1 = imx_uart_readl(sport, UCR1);
1368 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1369 imx_uart_writel(sport, ucr1, UCR1);
1370
1371 sport->dma_is_enabled = 1;
1372 }
1373
1374 static void imx_uart_disable_dma(struct imx_port *sport)
1375 {
1376 u32 ucr1;
1377
1378 /* clear UCR1 */
1379 ucr1 = imx_uart_readl(sport, UCR1);
1380 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1381 imx_uart_writel(sport, ucr1, UCR1);
1382
1383 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1384
1385 sport->dma_is_enabled = 0;
1386 }
1387
1388 /* half the RX buffer size */
1389 #define CTSTL 16
1390
1391 static int imx_uart_startup(struct uart_port *port)
1392 {
1393 struct imx_port *sport = (struct imx_port *)port;
1394 int retval, i;
1395 unsigned long flags;
1396 int dma_is_inited = 0;
1397 u32 ucr1, ucr2, ucr3, ucr4;
1398
1399 retval = clk_prepare_enable(sport->clk_per);
1400 if (retval)
1401 return retval;
1402 retval = clk_prepare_enable(sport->clk_ipg);
1403 if (retval) {
1404 clk_disable_unprepare(sport->clk_per);
1405 return retval;
1406 }
1407
1408 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1409
1410 /* disable the DREN bit (Data Ready interrupt enable) before
1411 * requesting IRQs
1412 */
1413 ucr4 = imx_uart_readl(sport, UCR4);
1414
1415 /* set the trigger level for CTS */
1416 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1417 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1418
1419 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1420
1421 /* Can we enable the DMA support? */
1422 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1423 dma_is_inited = 1;
1424
1425 spin_lock_irqsave(&sport->port.lock, flags);
1426 /* Reset fifo's and state machines */
1427 i = 100;
1428
1429 ucr2 = imx_uart_readl(sport, UCR2);
1430 ucr2 &= ~UCR2_SRST;
1431 imx_uart_writel(sport, ucr2, UCR2);
1432
1433 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1434 udelay(1);
1435
1436 /*
1437 * Finally, clear and enable interrupts
1438 */
1439 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1440 imx_uart_writel(sport, USR2_ORE, USR2);
1441
1442 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1443 ucr1 |= UCR1_UARTEN;
1444 if (sport->have_rtscts)
1445 ucr1 |= UCR1_RTSDEN;
1446
1447 imx_uart_writel(sport, ucr1, UCR1);
1448
1449 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1450 if (!sport->dma_is_enabled)
1451 ucr4 |= UCR4_OREN;
1452 if (sport->inverted_rx)
1453 ucr4 |= UCR4_INVR;
1454 imx_uart_writel(sport, ucr4, UCR4);
1455
1456 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1457 /*
1458 * configure tx polarity before enabling tx
1459 */
1460 if (sport->inverted_tx)
1461 ucr3 |= UCR3_INVT;
1462
1463 if (!imx_uart_is_imx1(sport)) {
1464 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1465
1466 if (sport->dte_mode)
1467 /* disable broken interrupts */
1468 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1469 }
1470 imx_uart_writel(sport, ucr3, UCR3);
1471
1472 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1473 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1474 if (!sport->have_rtscts)
1475 ucr2 |= UCR2_IRTS;
1476 /*
1477 * make sure the edge sensitive RTS-irq is disabled,
1478 * we're using RTSD instead.
1479 */
1480 if (!imx_uart_is_imx1(sport))
1481 ucr2 &= ~UCR2_RTSEN;
1482 imx_uart_writel(sport, ucr2, UCR2);
1483
1484 /*
1485 * Enable modem status interrupts
1486 */
1487 imx_uart_enable_ms(&sport->port);
1488
1489 if (dma_is_inited) {
1490 imx_uart_enable_dma(sport);
1491 imx_uart_start_rx_dma(sport);
1492 } else {
1493 ucr1 = imx_uart_readl(sport, UCR1);
1494 ucr1 |= UCR1_RRDYEN;
1495 imx_uart_writel(sport, ucr1, UCR1);
1496
1497 ucr2 = imx_uart_readl(sport, UCR2);
1498 ucr2 |= UCR2_ATEN;
1499 imx_uart_writel(sport, ucr2, UCR2);
1500 }
1501
1502 spin_unlock_irqrestore(&sport->port.lock, flags);
1503
1504 return 0;
1505 }
1506
1507 static void imx_uart_shutdown(struct uart_port *port)
1508 {
1509 struct imx_port *sport = (struct imx_port *)port;
1510 unsigned long flags;
1511 u32 ucr1, ucr2, ucr4;
1512
1513 if (sport->dma_is_enabled) {
1514 dmaengine_terminate_sync(sport->dma_chan_tx);
1515 if (sport->dma_is_txing) {
1516 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1517 sport->dma_tx_nents, DMA_TO_DEVICE);
1518 sport->dma_is_txing = 0;
1519 }
1520 dmaengine_terminate_sync(sport->dma_chan_rx);
1521 if (sport->dma_is_rxing) {
1522 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1523 1, DMA_FROM_DEVICE);
1524 sport->dma_is_rxing = 0;
1525 }
1526
1527 spin_lock_irqsave(&sport->port.lock, flags);
1528 imx_uart_stop_tx(port);
1529 imx_uart_stop_rx(port);
1530 imx_uart_disable_dma(sport);
1531 spin_unlock_irqrestore(&sport->port.lock, flags);
1532 imx_uart_dma_exit(sport);
1533 }
1534
1535 mctrl_gpio_disable_ms(sport->gpios);
1536
1537 spin_lock_irqsave(&sport->port.lock, flags);
1538 ucr2 = imx_uart_readl(sport, UCR2);
1539 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1540 imx_uart_writel(sport, ucr2, UCR2);
1541 spin_unlock_irqrestore(&sport->port.lock, flags);
1542
1543 /*
1544 * Stop our timer.
1545 */
1546 del_timer_sync(&sport->timer);
1547
1548 /*
1549 * Disable all interrupts, port and break condition.
1550 */
1551
1552 spin_lock_irqsave(&sport->port.lock, flags);
1553
1554 ucr1 = imx_uart_readl(sport, UCR1);
1555 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1556 imx_uart_writel(sport, ucr1, UCR1);
1557
1558 ucr4 = imx_uart_readl(sport, UCR4);
1559 ucr4 &= ~(UCR4_OREN | UCR4_TCEN);
1560 imx_uart_writel(sport, ucr4, UCR4);
1561
1562 spin_unlock_irqrestore(&sport->port.lock, flags);
1563
1564 clk_disable_unprepare(sport->clk_per);
1565 clk_disable_unprepare(sport->clk_ipg);
1566 }
1567
1568 /* called with port.lock taken and irqs off */
1569 static void imx_uart_flush_buffer(struct uart_port *port)
1570 {
1571 struct imx_port *sport = (struct imx_port *)port;
1572 struct scatterlist *sgl = &sport->tx_sgl[0];
1573 u32 ucr2;
1574 int i = 100, ubir, ubmr, uts;
1575
1576 if (!sport->dma_chan_tx)
1577 return;
1578
1579 sport->tx_bytes = 0;
1580 dmaengine_terminate_all(sport->dma_chan_tx);
1581 if (sport->dma_is_txing) {
1582 u32 ucr1;
1583
1584 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1585 DMA_TO_DEVICE);
1586 ucr1 = imx_uart_readl(sport, UCR1);
1587 ucr1 &= ~UCR1_TXDMAEN;
1588 imx_uart_writel(sport, ucr1, UCR1);
1589 sport->dma_is_txing = 0;
1590 }
1591
1592 /*
1593 * According to the Reference Manual description of the UART SRST bit:
1594 *
1595 * "Reset the transmit and receive state machines,
1596 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1597 * and UTS[6-3]".
1598 *
1599 * We don't need to restore the old values from USR1, USR2, URXD and
1600 * UTXD. UBRC is read only, so only save/restore the other three
1601 * registers.
1602 */
1603 ubir = imx_uart_readl(sport, UBIR);
1604 ubmr = imx_uart_readl(sport, UBMR);
1605 uts = imx_uart_readl(sport, IMX21_UTS);
1606
1607 ucr2 = imx_uart_readl(sport, UCR2);
1608 ucr2 &= ~UCR2_SRST;
1609 imx_uart_writel(sport, ucr2, UCR2);
1610
1611 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1612 udelay(1);
1613
1614 /* Restore the registers */
1615 imx_uart_writel(sport, ubir, UBIR);
1616 imx_uart_writel(sport, ubmr, UBMR);
1617 imx_uart_writel(sport, uts, IMX21_UTS);
1618 }
1619
1620 static void
1621 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1622 struct ktermios *old)
1623 {
1624 struct imx_port *sport = (struct imx_port *)port;
1625 unsigned long flags;
1626 u32 ucr2, old_ucr2, ufcr;
1627 unsigned int baud, quot;
1628 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1629 unsigned long div;
1630 unsigned long num, denom, old_ubir, old_ubmr;
1631 uint64_t tdiv64;
1632
1633 /*
1634 * We only support CS7 and CS8.
1635 */
1636 while ((termios->c_cflag & CSIZE) != CS7 &&
1637 (termios->c_cflag & CSIZE) != CS8) {
1638 termios->c_cflag &= ~CSIZE;
1639 termios->c_cflag |= old_csize;
1640 old_csize = CS8;
1641 }
1642
1643 del_timer_sync(&sport->timer);
1644
1645 /*
1646 * Ask the core to calculate the divisor for us.
1647 */
1648 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1649 quot = uart_get_divisor(port, baud);
1650
1651 spin_lock_irqsave(&sport->port.lock, flags);
1652
1653 /*
1654 * Read current UCR2 and save it for future use, then clear all the bits
1655 * except those we will or may need to preserve.
1656 */
1657 old_ucr2 = imx_uart_readl(sport, UCR2);
1658 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1659
1660 ucr2 |= UCR2_SRST | UCR2_IRTS;
1661 if ((termios->c_cflag & CSIZE) == CS8)
1662 ucr2 |= UCR2_WS;
1663
1664 if (!sport->have_rtscts)
1665 termios->c_cflag &= ~CRTSCTS;
1666
1667 if (port->rs485.flags & SER_RS485_ENABLED) {
1668 /*
1669 * RTS is mandatory for rs485 operation, so keep
1670 * it under manual control and keep transmitter
1671 * disabled.
1672 */
1673 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1674 imx_uart_rts_active(sport, &ucr2);
1675 else
1676 imx_uart_rts_inactive(sport, &ucr2);
1677
1678 } else if (termios->c_cflag & CRTSCTS) {
1679 /*
1680 * Only let receiver control RTS output if we were not requested
1681 * to have RTS inactive (which then should take precedence).
1682 */
1683 if (ucr2 & UCR2_CTS)
1684 ucr2 |= UCR2_CTSC;
1685 }
1686
1687 if (termios->c_cflag & CRTSCTS)
1688 ucr2 &= ~UCR2_IRTS;
1689 if (termios->c_cflag & CSTOPB)
1690 ucr2 |= UCR2_STPB;
1691 if (termios->c_cflag & PARENB) {
1692 ucr2 |= UCR2_PREN;
1693 if (termios->c_cflag & PARODD)
1694 ucr2 |= UCR2_PROE;
1695 }
1696
1697 sport->port.read_status_mask = 0;
1698 if (termios->c_iflag & INPCK)
1699 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1700 if (termios->c_iflag & (BRKINT | PARMRK))
1701 sport->port.read_status_mask |= URXD_BRK;
1702
1703 /*
1704 * Characters to ignore
1705 */
1706 sport->port.ignore_status_mask = 0;
1707 if (termios->c_iflag & IGNPAR)
1708 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1709 if (termios->c_iflag & IGNBRK) {
1710 sport->port.ignore_status_mask |= URXD_BRK;
1711 /*
1712 * If we're ignoring parity and break indicators,
1713 * ignore overruns too (for real raw support).
1714 */
1715 if (termios->c_iflag & IGNPAR)
1716 sport->port.ignore_status_mask |= URXD_OVRRUN;
1717 }
1718
1719 if ((termios->c_cflag & CREAD) == 0)
1720 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1721
1722 /*
1723 * Update the per-port timeout.
1724 */
1725 uart_update_timeout(port, termios->c_cflag, baud);
1726
1727 /* custom-baudrate handling */
1728 div = sport->port.uartclk / (baud * 16);
1729 if (baud == 38400 && quot != div)
1730 baud = sport->port.uartclk / (quot * 16);
1731
1732 div = sport->port.uartclk / (baud * 16);
1733 if (div > 7)
1734 div = 7;
1735 if (!div)
1736 div = 1;
1737
1738 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1739 1 << 16, 1 << 16, &num, &denom);
1740
1741 tdiv64 = sport->port.uartclk;
1742 tdiv64 *= num;
1743 do_div(tdiv64, denom * 16 * div);
1744 tty_termios_encode_baud_rate(termios,
1745 (speed_t)tdiv64, (speed_t)tdiv64);
1746
1747 num -= 1;
1748 denom -= 1;
1749
1750 ufcr = imx_uart_readl(sport, UFCR);
1751 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1752 imx_uart_writel(sport, ufcr, UFCR);
1753
1754 /*
1755 * Two registers below should always be written both and in this
1756 * particular order. One consequence is that we need to check if any of
1757 * them changes and then update both. We do need the check for change
1758 * as even writing the same values seem to "restart"
1759 * transmission/receiving logic in the hardware, that leads to data
1760 * breakage even when rate doesn't in fact change. E.g., user switches
1761 * RTS/CTS handshake and suddenly gets broken bytes.
1762 */
1763 old_ubir = imx_uart_readl(sport, UBIR);
1764 old_ubmr = imx_uart_readl(sport, UBMR);
1765 if (old_ubir != num || old_ubmr != denom) {
1766 imx_uart_writel(sport, num, UBIR);
1767 imx_uart_writel(sport, denom, UBMR);
1768 }
1769
1770 if (!imx_uart_is_imx1(sport))
1771 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1772 IMX21_ONEMS);
1773
1774 imx_uart_writel(sport, ucr2, UCR2);
1775
1776 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1777 imx_uart_enable_ms(&sport->port);
1778
1779 spin_unlock_irqrestore(&sport->port.lock, flags);
1780 }
1781
1782 static const char *imx_uart_type(struct uart_port *port)
1783 {
1784 struct imx_port *sport = (struct imx_port *)port;
1785
1786 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1787 }
1788
1789 /*
1790 * Configure/autoconfigure the port.
1791 */
1792 static void imx_uart_config_port(struct uart_port *port, int flags)
1793 {
1794 struct imx_port *sport = (struct imx_port *)port;
1795
1796 if (flags & UART_CONFIG_TYPE)
1797 sport->port.type = PORT_IMX;
1798 }
1799
1800 /*
1801 * Verify the new serial_struct (for TIOCSSERIAL).
1802 * The only change we allow are to the flags and type, and
1803 * even then only between PORT_IMX and PORT_UNKNOWN
1804 */
1805 static int
1806 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1807 {
1808 struct imx_port *sport = (struct imx_port *)port;
1809 int ret = 0;
1810
1811 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1812 ret = -EINVAL;
1813 if (sport->port.irq != ser->irq)
1814 ret = -EINVAL;
1815 if (ser->io_type != UPIO_MEM)
1816 ret = -EINVAL;
1817 if (sport->port.uartclk / 16 != ser->baud_base)
1818 ret = -EINVAL;
1819 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1820 ret = -EINVAL;
1821 if (sport->port.iobase != ser->port)
1822 ret = -EINVAL;
1823 if (ser->hub6 != 0)
1824 ret = -EINVAL;
1825 return ret;
1826 }
1827
1828 #if defined(CONFIG_CONSOLE_POLL)
1829
1830 static int imx_uart_poll_init(struct uart_port *port)
1831 {
1832 struct imx_port *sport = (struct imx_port *)port;
1833 unsigned long flags;
1834 u32 ucr1, ucr2;
1835 int retval;
1836
1837 retval = clk_prepare_enable(sport->clk_ipg);
1838 if (retval)
1839 return retval;
1840 retval = clk_prepare_enable(sport->clk_per);
1841 if (retval)
1842 clk_disable_unprepare(sport->clk_ipg);
1843
1844 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1845
1846 spin_lock_irqsave(&sport->port.lock, flags);
1847
1848 /*
1849 * Be careful about the order of enabling bits here. First enable the
1850 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1851 * This prevents that a character that already sits in the RX fifo is
1852 * triggering an irq but the try to fetch it from there results in an
1853 * exception because UARTEN or RXEN is still off.
1854 */
1855 ucr1 = imx_uart_readl(sport, UCR1);
1856 ucr2 = imx_uart_readl(sport, UCR2);
1857
1858 if (imx_uart_is_imx1(sport))
1859 ucr1 |= IMX1_UCR1_UARTCLKEN;
1860
1861 ucr1 |= UCR1_UARTEN;
1862 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1863
1864 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1865 ucr2 &= ~UCR2_ATEN;
1866
1867 imx_uart_writel(sport, ucr1, UCR1);
1868 imx_uart_writel(sport, ucr2, UCR2);
1869
1870 /* now enable irqs */
1871 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1872 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1873
1874 spin_unlock_irqrestore(&sport->port.lock, flags);
1875
1876 return 0;
1877 }
1878
1879 static int imx_uart_poll_get_char(struct uart_port *port)
1880 {
1881 struct imx_port *sport = (struct imx_port *)port;
1882 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1883 return NO_POLL_CHAR;
1884
1885 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1886 }
1887
1888 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1889 {
1890 struct imx_port *sport = (struct imx_port *)port;
1891 unsigned int status;
1892
1893 /* drain */
1894 do {
1895 status = imx_uart_readl(sport, USR1);
1896 } while (~status & USR1_TRDY);
1897
1898 /* write */
1899 imx_uart_writel(sport, c, URTX0);
1900
1901 /* flush */
1902 do {
1903 status = imx_uart_readl(sport, USR2);
1904 } while (~status & USR2_TXDC);
1905 }
1906 #endif
1907
1908 /* called with port.lock taken and irqs off or from .probe without locking */
1909 static int imx_uart_rs485_config(struct uart_port *port,
1910 struct serial_rs485 *rs485conf)
1911 {
1912 struct imx_port *sport = (struct imx_port *)port;
1913 u32 ucr2;
1914
1915 /* RTS is required to control the transmitter */
1916 if (!sport->have_rtscts && !sport->have_rtsgpio)
1917 rs485conf->flags &= ~SER_RS485_ENABLED;
1918
1919 if (rs485conf->flags & SER_RS485_ENABLED) {
1920 /* Enable receiver if low-active RTS signal is requested */
1921 if (sport->have_rtscts && !sport->have_rtsgpio &&
1922 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1923 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1924
1925 /* disable transmitter */
1926 ucr2 = imx_uart_readl(sport, UCR2);
1927 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1928 imx_uart_rts_active(sport, &ucr2);
1929 else
1930 imx_uart_rts_inactive(sport, &ucr2);
1931 imx_uart_writel(sport, ucr2, UCR2);
1932 }
1933
1934 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1935 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1936 rs485conf->flags & SER_RS485_RX_DURING_TX)
1937 imx_uart_start_rx(port);
1938
1939 port->rs485 = *rs485conf;
1940
1941 return 0;
1942 }
1943
1944 static const struct uart_ops imx_uart_pops = {
1945 .tx_empty = imx_uart_tx_empty,
1946 .set_mctrl = imx_uart_set_mctrl,
1947 .get_mctrl = imx_uart_get_mctrl,
1948 .stop_tx = imx_uart_stop_tx,
1949 .start_tx = imx_uart_start_tx,
1950 .stop_rx = imx_uart_stop_rx,
1951 .enable_ms = imx_uart_enable_ms,
1952 .break_ctl = imx_uart_break_ctl,
1953 .startup = imx_uart_startup,
1954 .shutdown = imx_uart_shutdown,
1955 .flush_buffer = imx_uart_flush_buffer,
1956 .set_termios = imx_uart_set_termios,
1957 .type = imx_uart_type,
1958 .config_port = imx_uart_config_port,
1959 .verify_port = imx_uart_verify_port,
1960 #if defined(CONFIG_CONSOLE_POLL)
1961 .poll_init = imx_uart_poll_init,
1962 .poll_get_char = imx_uart_poll_get_char,
1963 .poll_put_char = imx_uart_poll_put_char,
1964 #endif
1965 };
1966
1967 static struct imx_port *imx_uart_ports[UART_NR];
1968
1969 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
1970 static void imx_uart_console_putchar(struct uart_port *port, int ch)
1971 {
1972 struct imx_port *sport = (struct imx_port *)port;
1973
1974 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1975 barrier();
1976
1977 imx_uart_writel(sport, ch, URTX0);
1978 }
1979
1980 /*
1981 * Interrupts are disabled on entering
1982 */
1983 static void
1984 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1985 {
1986 struct imx_port *sport = imx_uart_ports[co->index];
1987 struct imx_port_ucrs old_ucr;
1988 unsigned int ucr1;
1989 unsigned long flags = 0;
1990 int locked = 1;
1991
1992 if (sport->port.sysrq)
1993 locked = 0;
1994 else if (oops_in_progress)
1995 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1996 else
1997 spin_lock_irqsave(&sport->port.lock, flags);
1998
1999 /*
2000 * First, save UCR1/2/3 and then disable interrupts
2001 */
2002 imx_uart_ucrs_save(sport, &old_ucr);
2003 ucr1 = old_ucr.ucr1;
2004
2005 if (imx_uart_is_imx1(sport))
2006 ucr1 |= IMX1_UCR1_UARTCLKEN;
2007 ucr1 |= UCR1_UARTEN;
2008 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2009
2010 imx_uart_writel(sport, ucr1, UCR1);
2011
2012 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2013
2014 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2015
2016 /*
2017 * Finally, wait for transmitter to become empty
2018 * and restore UCR1/2/3
2019 */
2020 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2021
2022 imx_uart_ucrs_restore(sport, &old_ucr);
2023
2024 if (locked)
2025 spin_unlock_irqrestore(&sport->port.lock, flags);
2026 }
2027
2028 /*
2029 * If the port was already initialised (eg, by a boot loader),
2030 * try to determine the current setup.
2031 */
2032 static void __init
2033 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2034 int *parity, int *bits)
2035 {
2036
2037 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2038 /* ok, the port was enabled */
2039 unsigned int ucr2, ubir, ubmr, uartclk;
2040 unsigned int baud_raw;
2041 unsigned int ucfr_rfdiv;
2042
2043 ucr2 = imx_uart_readl(sport, UCR2);
2044
2045 *parity = 'n';
2046 if (ucr2 & UCR2_PREN) {
2047 if (ucr2 & UCR2_PROE)
2048 *parity = 'o';
2049 else
2050 *parity = 'e';
2051 }
2052
2053 if (ucr2 & UCR2_WS)
2054 *bits = 8;
2055 else
2056 *bits = 7;
2057
2058 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2059 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2060
2061 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2062 if (ucfr_rfdiv == 6)
2063 ucfr_rfdiv = 7;
2064 else
2065 ucfr_rfdiv = 6 - ucfr_rfdiv;
2066
2067 uartclk = clk_get_rate(sport->clk_per);
2068 uartclk /= ucfr_rfdiv;
2069
2070 { /*
2071 * The next code provides exact computation of
2072 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2073 * without need of float support or long long division,
2074 * which would be required to prevent 32bit arithmetic overflow
2075 */
2076 unsigned int mul = ubir + 1;
2077 unsigned int div = 16 * (ubmr + 1);
2078 unsigned int rem = uartclk % div;
2079
2080 baud_raw = (uartclk / div) * mul;
2081 baud_raw += (rem * mul + div / 2) / div;
2082 *baud = (baud_raw + 50) / 100 * 100;
2083 }
2084
2085 if (*baud != baud_raw)
2086 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2087 baud_raw, *baud);
2088 }
2089 }
2090
2091 static int __init
2092 imx_uart_console_setup(struct console *co, char *options)
2093 {
2094 struct imx_port *sport;
2095 int baud = 9600;
2096 int bits = 8;
2097 int parity = 'n';
2098 int flow = 'n';
2099 int retval;
2100
2101 /*
2102 * Check whether an invalid uart number has been specified, and
2103 * if so, search for the first available port that does have
2104 * console support.
2105 */
2106 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2107 co->index = 0;
2108 sport = imx_uart_ports[co->index];
2109 if (sport == NULL)
2110 return -ENODEV;
2111
2112 /* For setting the registers, we only need to enable the ipg clock. */
2113 retval = clk_prepare_enable(sport->clk_ipg);
2114 if (retval)
2115 goto error_console;
2116
2117 if (options)
2118 uart_parse_options(options, &baud, &parity, &bits, &flow);
2119 else
2120 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2121
2122 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2123
2124 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2125
2126 if (retval) {
2127 clk_disable_unprepare(sport->clk_ipg);
2128 goto error_console;
2129 }
2130
2131 retval = clk_prepare_enable(sport->clk_per);
2132 if (retval)
2133 clk_disable_unprepare(sport->clk_ipg);
2134
2135 error_console:
2136 return retval;
2137 }
2138
2139 static struct uart_driver imx_uart_uart_driver;
2140 static struct console imx_uart_console = {
2141 .name = DEV_NAME,
2142 .write = imx_uart_console_write,
2143 .device = uart_console_device,
2144 .setup = imx_uart_console_setup,
2145 .flags = CON_PRINTBUFFER,
2146 .index = -1,
2147 .data = &imx_uart_uart_driver,
2148 };
2149
2150 #define IMX_CONSOLE &imx_uart_console
2151
2152 #else
2153 #define IMX_CONSOLE NULL
2154 #endif
2155
2156 static struct uart_driver imx_uart_uart_driver = {
2157 .owner = THIS_MODULE,
2158 .driver_name = DRIVER_NAME,
2159 .dev_name = DEV_NAME,
2160 .major = SERIAL_IMX_MAJOR,
2161 .minor = MINOR_START,
2162 .nr = ARRAY_SIZE(imx_uart_ports),
2163 .cons = IMX_CONSOLE,
2164 };
2165
2166 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2167 {
2168 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2169 unsigned long flags;
2170
2171 spin_lock_irqsave(&sport->port.lock, flags);
2172 if (sport->tx_state == WAIT_AFTER_RTS)
2173 imx_uart_start_tx(&sport->port);
2174 spin_unlock_irqrestore(&sport->port.lock, flags);
2175
2176 return HRTIMER_NORESTART;
2177 }
2178
2179 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2180 {
2181 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2182 unsigned long flags;
2183
2184 spin_lock_irqsave(&sport->port.lock, flags);
2185 if (sport->tx_state == WAIT_AFTER_SEND)
2186 imx_uart_stop_tx(&sport->port);
2187 spin_unlock_irqrestore(&sport->port.lock, flags);
2188
2189 return HRTIMER_NORESTART;
2190 }
2191
2192 static int imx_uart_probe(struct platform_device *pdev)
2193 {
2194 struct device_node *np = pdev->dev.of_node;
2195 struct imx_port *sport;
2196 void __iomem *base;
2197 int ret = 0;
2198 u32 ucr1;
2199 struct resource *res;
2200 int txirq, rxirq, rtsirq;
2201
2202 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2203 if (!sport)
2204 return -ENOMEM;
2205
2206 sport->devdata = of_device_get_match_data(&pdev->dev);
2207
2208 ret = of_alias_get_id(np, "serial");
2209 if (ret < 0) {
2210 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2211 return ret;
2212 }
2213 sport->port.line = ret;
2214
2215 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2216 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2217 sport->have_rtscts = 1;
2218
2219 if (of_get_property(np, "fsl,dte-mode", NULL))
2220 sport->dte_mode = 1;
2221
2222 if (of_get_property(np, "rts-gpios", NULL))
2223 sport->have_rtsgpio = 1;
2224
2225 if (of_get_property(np, "fsl,inverted-tx", NULL))
2226 sport->inverted_tx = 1;
2227
2228 if (of_get_property(np, "fsl,inverted-rx", NULL))
2229 sport->inverted_rx = 1;
2230
2231 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2232 dev_err(&pdev->dev, "serial%d out of range\n",
2233 sport->port.line);
2234 return -EINVAL;
2235 }
2236
2237 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2238 base = devm_ioremap_resource(&pdev->dev, res);
2239 if (IS_ERR(base))
2240 return PTR_ERR(base);
2241
2242 rxirq = platform_get_irq(pdev, 0);
2243 if (rxirq < 0)
2244 return rxirq;
2245 txirq = platform_get_irq_optional(pdev, 1);
2246 rtsirq = platform_get_irq_optional(pdev, 2);
2247
2248 sport->port.dev = &pdev->dev;
2249 sport->port.mapbase = res->start;
2250 sport->port.membase = base;
2251 sport->port.type = PORT_IMX,
2252 sport->port.iotype = UPIO_MEM;
2253 sport->port.irq = rxirq;
2254 sport->port.fifosize = 32;
2255 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2256 sport->port.ops = &imx_uart_pops;
2257 sport->port.rs485_config = imx_uart_rs485_config;
2258 sport->port.flags = UPF_BOOT_AUTOCONF;
2259 timer_setup(&sport->timer, imx_uart_timeout, 0);
2260
2261 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2262 if (IS_ERR(sport->gpios))
2263 return PTR_ERR(sport->gpios);
2264
2265 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2266 if (IS_ERR(sport->clk_ipg)) {
2267 ret = PTR_ERR(sport->clk_ipg);
2268 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2269 return ret;
2270 }
2271
2272 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2273 if (IS_ERR(sport->clk_per)) {
2274 ret = PTR_ERR(sport->clk_per);
2275 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2276 return ret;
2277 }
2278
2279 sport->port.uartclk = clk_get_rate(sport->clk_per);
2280
2281 /* For register access, we only need to enable the ipg clock. */
2282 ret = clk_prepare_enable(sport->clk_ipg);
2283 if (ret) {
2284 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2285 return ret;
2286 }
2287
2288 /* initialize shadow register values */
2289 sport->ucr1 = readl(sport->port.membase + UCR1);
2290 sport->ucr2 = readl(sport->port.membase + UCR2);
2291 sport->ucr3 = readl(sport->port.membase + UCR3);
2292 sport->ucr4 = readl(sport->port.membase + UCR4);
2293 sport->ufcr = readl(sport->port.membase + UFCR);
2294
2295 ret = uart_get_rs485_mode(&sport->port);
2296 if (ret) {
2297 clk_disable_unprepare(sport->clk_ipg);
2298 return ret;
2299 }
2300
2301 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2302 (!sport->have_rtscts && !sport->have_rtsgpio))
2303 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2304
2305 /*
2306 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2307 * signal cannot be set low during transmission in case the
2308 * receiver is off (limitation of the i.MX UART IP).
2309 */
2310 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2311 sport->have_rtscts && !sport->have_rtsgpio &&
2312 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2313 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2314 dev_err(&pdev->dev,
2315 "low-active RTS not possible when receiver is off, enabling receiver\n");
2316
2317 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2318
2319 /* Disable interrupts before requesting them */
2320 ucr1 = imx_uart_readl(sport, UCR1);
2321 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2322 imx_uart_writel(sport, ucr1, UCR1);
2323
2324 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2325 /*
2326 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2327 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2328 * and DCD (when they are outputs) or enables the respective
2329 * irqs. So set this bit early, i.e. before requesting irqs.
2330 */
2331 u32 ufcr = imx_uart_readl(sport, UFCR);
2332 if (!(ufcr & UFCR_DCEDTE))
2333 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2334
2335 /*
2336 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2337 * enabled later because they cannot be cleared
2338 * (confirmed on i.MX25) which makes them unusable.
2339 */
2340 imx_uart_writel(sport,
2341 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2342 UCR3);
2343
2344 } else {
2345 u32 ucr3 = UCR3_DSR;
2346 u32 ufcr = imx_uart_readl(sport, UFCR);
2347 if (ufcr & UFCR_DCEDTE)
2348 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2349
2350 if (!imx_uart_is_imx1(sport))
2351 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2352 imx_uart_writel(sport, ucr3, UCR3);
2353 }
2354
2355 clk_disable_unprepare(sport->clk_ipg);
2356
2357 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2358 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2359 sport->trigger_start_tx.function = imx_trigger_start_tx;
2360 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2361
2362 /*
2363 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2364 * chips only have one interrupt.
2365 */
2366 if (txirq > 0) {
2367 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2368 dev_name(&pdev->dev), sport);
2369 if (ret) {
2370 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2371 ret);
2372 return ret;
2373 }
2374
2375 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2376 dev_name(&pdev->dev), sport);
2377 if (ret) {
2378 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2379 ret);
2380 return ret;
2381 }
2382
2383 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2384 dev_name(&pdev->dev), sport);
2385 if (ret) {
2386 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2387 ret);
2388 return ret;
2389 }
2390 } else {
2391 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2392 dev_name(&pdev->dev), sport);
2393 if (ret) {
2394 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2395 return ret;
2396 }
2397 }
2398
2399 imx_uart_ports[sport->port.line] = sport;
2400
2401 platform_set_drvdata(pdev, sport);
2402
2403 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2404 }
2405
2406 static int imx_uart_remove(struct platform_device *pdev)
2407 {
2408 struct imx_port *sport = platform_get_drvdata(pdev);
2409
2410 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2411 }
2412
2413 static void imx_uart_restore_context(struct imx_port *sport)
2414 {
2415 unsigned long flags;
2416
2417 spin_lock_irqsave(&sport->port.lock, flags);
2418 if (!sport->context_saved) {
2419 spin_unlock_irqrestore(&sport->port.lock, flags);
2420 return;
2421 }
2422
2423 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2424 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2425 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2426 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2427 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2428 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2429 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2430 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2431 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2432 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2433 sport->context_saved = false;
2434 spin_unlock_irqrestore(&sport->port.lock, flags);
2435 }
2436
2437 static void imx_uart_save_context(struct imx_port *sport)
2438 {
2439 unsigned long flags;
2440
2441 /* Save necessary regs */
2442 spin_lock_irqsave(&sport->port.lock, flags);
2443 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2444 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2445 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2446 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2447 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2448 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2449 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2450 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2451 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2452 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2453 sport->context_saved = true;
2454 spin_unlock_irqrestore(&sport->port.lock, flags);
2455 }
2456
2457 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2458 {
2459 u32 ucr3;
2460
2461 ucr3 = imx_uart_readl(sport, UCR3);
2462 if (on) {
2463 imx_uart_writel(sport, USR1_AWAKE, USR1);
2464 ucr3 |= UCR3_AWAKEN;
2465 } else {
2466 ucr3 &= ~UCR3_AWAKEN;
2467 }
2468 imx_uart_writel(sport, ucr3, UCR3);
2469
2470 if (sport->have_rtscts) {
2471 u32 ucr1 = imx_uart_readl(sport, UCR1);
2472 if (on)
2473 ucr1 |= UCR1_RTSDEN;
2474 else
2475 ucr1 &= ~UCR1_RTSDEN;
2476 imx_uart_writel(sport, ucr1, UCR1);
2477 }
2478 }
2479
2480 static int imx_uart_suspend_noirq(struct device *dev)
2481 {
2482 struct imx_port *sport = dev_get_drvdata(dev);
2483
2484 imx_uart_save_context(sport);
2485
2486 clk_disable(sport->clk_ipg);
2487
2488 pinctrl_pm_select_sleep_state(dev);
2489
2490 return 0;
2491 }
2492
2493 static int imx_uart_resume_noirq(struct device *dev)
2494 {
2495 struct imx_port *sport = dev_get_drvdata(dev);
2496 int ret;
2497
2498 pinctrl_pm_select_default_state(dev);
2499
2500 ret = clk_enable(sport->clk_ipg);
2501 if (ret)
2502 return ret;
2503
2504 imx_uart_restore_context(sport);
2505
2506 return 0;
2507 }
2508
2509 static int imx_uart_suspend(struct device *dev)
2510 {
2511 struct imx_port *sport = dev_get_drvdata(dev);
2512 int ret;
2513
2514 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2515 disable_irq(sport->port.irq);
2516
2517 ret = clk_prepare_enable(sport->clk_ipg);
2518 if (ret)
2519 return ret;
2520
2521 /* enable wakeup from i.MX UART */
2522 imx_uart_enable_wakeup(sport, true);
2523
2524 return 0;
2525 }
2526
2527 static int imx_uart_resume(struct device *dev)
2528 {
2529 struct imx_port *sport = dev_get_drvdata(dev);
2530
2531 /* disable wakeup from i.MX UART */
2532 imx_uart_enable_wakeup(sport, false);
2533
2534 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2535 enable_irq(sport->port.irq);
2536
2537 clk_disable_unprepare(sport->clk_ipg);
2538
2539 return 0;
2540 }
2541
2542 static int imx_uart_freeze(struct device *dev)
2543 {
2544 struct imx_port *sport = dev_get_drvdata(dev);
2545
2546 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2547
2548 return clk_prepare_enable(sport->clk_ipg);
2549 }
2550
2551 static int imx_uart_thaw(struct device *dev)
2552 {
2553 struct imx_port *sport = dev_get_drvdata(dev);
2554
2555 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2556
2557 clk_disable_unprepare(sport->clk_ipg);
2558
2559 return 0;
2560 }
2561
2562 static const struct dev_pm_ops imx_uart_pm_ops = {
2563 .suspend_noirq = imx_uart_suspend_noirq,
2564 .resume_noirq = imx_uart_resume_noirq,
2565 .freeze_noirq = imx_uart_suspend_noirq,
2566 .restore_noirq = imx_uart_resume_noirq,
2567 .suspend = imx_uart_suspend,
2568 .resume = imx_uart_resume,
2569 .freeze = imx_uart_freeze,
2570 .thaw = imx_uart_thaw,
2571 .restore = imx_uart_thaw,
2572 };
2573
2574 static struct platform_driver imx_uart_platform_driver = {
2575 .probe = imx_uart_probe,
2576 .remove = imx_uart_remove,
2577
2578 .driver = {
2579 .name = "imx-uart",
2580 .of_match_table = imx_uart_dt_ids,
2581 .pm = &imx_uart_pm_ops,
2582 },
2583 };
2584
2585 static int __init imx_uart_init(void)
2586 {
2587 int ret = uart_register_driver(&imx_uart_uart_driver);
2588
2589 if (ret)
2590 return ret;
2591
2592 ret = platform_driver_register(&imx_uart_platform_driver);
2593 if (ret != 0)
2594 uart_unregister_driver(&imx_uart_uart_driver);
2595
2596 return ret;
2597 }
2598
2599 static void __exit imx_uart_exit(void)
2600 {
2601 platform_driver_unregister(&imx_uart_platform_driver);
2602 uart_unregister_driver(&imx_uart_uart_driver);
2603 }
2604
2605 module_init(imx_uart_init);
2606 module_exit(imx_uart_exit);
2607
2608 MODULE_AUTHOR("Sascha Hauer");
2609 MODULE_DESCRIPTION("IMX generic serial port driver");
2610 MODULE_LICENSE("GPL");
2611 MODULE_ALIAS("platform:imx-uart");
Linux with added FPC-III support