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Merge tag 'mmc-v4.6-rc4' of git://git.linaro.org/people/ulf.hansson/mmc
[linux/fpc-iii.git] / drivers / vme / bridges / vme_ca91cx42.c
blob5fbeab38889ebd29843c3c0e32e7d7a36f937d76
1 /*
2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
3 *
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * Derived from ca91c042.c by Michael Wyrick
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18 #include <linux/module.h>
19 #include <linux/mm.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/pci.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/poll.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/time.h>
30 #include <linux/io.h>
31 #include <linux/uaccess.h>
32 #include <linux/vme.h>
33
34 #include "../vme_bridge.h"
35 #include "vme_ca91cx42.h"
36
37 static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
38 static void ca91cx42_remove(struct pci_dev *);
39
40 /* Module parameters */
41 static int geoid;
42
43 static const char driver_name[] = "vme_ca91cx42";
44
45 static const struct pci_device_id ca91cx42_ids[] = {
46 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
47 { },
48 };
49
50 static struct pci_driver ca91cx42_driver = {
51 .name = driver_name,
52 .id_table = ca91cx42_ids,
53 .probe = ca91cx42_probe,
54 .remove = ca91cx42_remove,
55 };
56
57 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
58 {
59 wake_up(&bridge->dma_queue);
60
61 return CA91CX42_LINT_DMA;
62 }
63
64 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
65 {
66 int i;
67 u32 serviced = 0;
68
69 for (i = 0; i < 4; i++) {
70 if (stat & CA91CX42_LINT_LM[i]) {
71 /* We only enable interrupts if the callback is set */
72 bridge->lm_callback[i](i);
73 serviced |= CA91CX42_LINT_LM[i];
74 }
75 }
76
77 return serviced;
78 }
79
80 /* XXX This needs to be split into 4 queues */
81 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
82 {
83 wake_up(&bridge->mbox_queue);
84
85 return CA91CX42_LINT_MBOX;
86 }
87
88 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
89 {
90 wake_up(&bridge->iack_queue);
91
92 return CA91CX42_LINT_SW_IACK;
93 }
94
95 static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
96 {
97 int val;
98 struct ca91cx42_driver *bridge;
99
100 bridge = ca91cx42_bridge->driver_priv;
101
102 val = ioread32(bridge->base + DGCS);
103
104 if (!(val & 0x00000800)) {
105 dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA "
106 "Read Error DGCS=%08X\n", val);
107 }
108
109 return CA91CX42_LINT_VERR;
110 }
111
112 static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
113 {
114 int val;
115 struct ca91cx42_driver *bridge;
116
117 bridge = ca91cx42_bridge->driver_priv;
118
119 val = ioread32(bridge->base + DGCS);
120
121 if (!(val & 0x00000800))
122 dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA "
123 "Read Error DGCS=%08X\n", val);
124
125 return CA91CX42_LINT_LERR;
126 }
127
128
129 static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
130 int stat)
131 {
132 int vec, i, serviced = 0;
133 struct ca91cx42_driver *bridge;
134
135 bridge = ca91cx42_bridge->driver_priv;
136
137
138 for (i = 7; i > 0; i--) {
139 if (stat & (1 << i)) {
140 vec = ioread32(bridge->base +
141 CA91CX42_V_STATID[i]) & 0xff;
142
143 vme_irq_handler(ca91cx42_bridge, i, vec);
144
145 serviced |= (1 << i);
146 }
147 }
148
149 return serviced;
150 }
151
152 static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
153 {
154 u32 stat, enable, serviced = 0;
155 struct vme_bridge *ca91cx42_bridge;
156 struct ca91cx42_driver *bridge;
157
158 ca91cx42_bridge = ptr;
159
160 bridge = ca91cx42_bridge->driver_priv;
161
162 enable = ioread32(bridge->base + LINT_EN);
163 stat = ioread32(bridge->base + LINT_STAT);
164
165 /* Only look at unmasked interrupts */
166 stat &= enable;
167
168 if (unlikely(!stat))
169 return IRQ_NONE;
170
171 if (stat & CA91CX42_LINT_DMA)
172 serviced |= ca91cx42_DMA_irqhandler(bridge);
173 if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
174 CA91CX42_LINT_LM3))
175 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
176 if (stat & CA91CX42_LINT_MBOX)
177 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
178 if (stat & CA91CX42_LINT_SW_IACK)
179 serviced |= ca91cx42_IACK_irqhandler(bridge);
180 if (stat & CA91CX42_LINT_VERR)
181 serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge);
182 if (stat & CA91CX42_LINT_LERR)
183 serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge);
184 if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
185 CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
186 CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
187 CA91CX42_LINT_VIRQ7))
188 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
189
190 /* Clear serviced interrupts */
191 iowrite32(serviced, bridge->base + LINT_STAT);
192
193 return IRQ_HANDLED;
194 }
195
196 static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
197 {
198 int result, tmp;
199 struct pci_dev *pdev;
200 struct ca91cx42_driver *bridge;
201
202 bridge = ca91cx42_bridge->driver_priv;
203
204 /* Need pdev */
205 pdev = to_pci_dev(ca91cx42_bridge->parent);
206
207 INIT_LIST_HEAD(&ca91cx42_bridge->vme_error_handlers);
208
209 mutex_init(&ca91cx42_bridge->irq_mtx);
210
211 /* Disable interrupts from PCI to VME */
212 iowrite32(0, bridge->base + VINT_EN);
213
214 /* Disable PCI interrupts */
215 iowrite32(0, bridge->base + LINT_EN);
216 /* Clear Any Pending PCI Interrupts */
217 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
218
219 result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
220 driver_name, ca91cx42_bridge);
221 if (result) {
222 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
223 pdev->irq);
224 return result;
225 }
226
227 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
228 iowrite32(0, bridge->base + LINT_MAP0);
229 iowrite32(0, bridge->base + LINT_MAP1);
230 iowrite32(0, bridge->base + LINT_MAP2);
231
232 /* Enable DMA, mailbox & LM Interrupts */
233 tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
234 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
235 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
236
237 iowrite32(tmp, bridge->base + LINT_EN);
238
239 return 0;
240 }
241
242 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
243 struct pci_dev *pdev)
244 {
245 struct vme_bridge *ca91cx42_bridge;
246
247 /* Disable interrupts from PCI to VME */
248 iowrite32(0, bridge->base + VINT_EN);
249
250 /* Disable PCI interrupts */
251 iowrite32(0, bridge->base + LINT_EN);
252 /* Clear Any Pending PCI Interrupts */
253 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
254
255 ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge,
256 driver_priv);
257 free_irq(pdev->irq, ca91cx42_bridge);
258 }
259
260 static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level)
261 {
262 u32 tmp;
263
264 tmp = ioread32(bridge->base + LINT_STAT);
265
266 if (tmp & (1 << level))
267 return 0;
268 else
269 return 1;
270 }
271
272 /*
273 * Set up an VME interrupt
274 */
275 static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level,
276 int state, int sync)
277
278 {
279 struct pci_dev *pdev;
280 u32 tmp;
281 struct ca91cx42_driver *bridge;
282
283 bridge = ca91cx42_bridge->driver_priv;
284
285 /* Enable IRQ level */
286 tmp = ioread32(bridge->base + LINT_EN);
287
288 if (state == 0)
289 tmp &= ~CA91CX42_LINT_VIRQ[level];
290 else
291 tmp |= CA91CX42_LINT_VIRQ[level];
292
293 iowrite32(tmp, bridge->base + LINT_EN);
294
295 if ((state == 0) && (sync != 0)) {
296 pdev = to_pci_dev(ca91cx42_bridge->parent);
297
298 synchronize_irq(pdev->irq);
299 }
300 }
301
302 static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
303 int statid)
304 {
305 u32 tmp;
306 struct ca91cx42_driver *bridge;
307
308 bridge = ca91cx42_bridge->driver_priv;
309
310 /* Universe can only generate even vectors */
311 if (statid & 1)
312 return -EINVAL;
313
314 mutex_lock(&bridge->vme_int);
315
316 tmp = ioread32(bridge->base + VINT_EN);
317
318 /* Set Status/ID */
319 iowrite32(statid << 24, bridge->base + STATID);
320
321 /* Assert VMEbus IRQ */
322 tmp = tmp | (1 << (level + 24));
323 iowrite32(tmp, bridge->base + VINT_EN);
324
325 /* Wait for IACK */
326 wait_event_interruptible(bridge->iack_queue,
327 ca91cx42_iack_received(bridge, level));
328
329 /* Return interrupt to low state */
330 tmp = ioread32(bridge->base + VINT_EN);
331 tmp = tmp & ~(1 << (level + 24));
332 iowrite32(tmp, bridge->base + VINT_EN);
333
334 mutex_unlock(&bridge->vme_int);
335
336 return 0;
337 }
338
339 static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
340 unsigned long long vme_base, unsigned long long size,
341 dma_addr_t pci_base, u32 aspace, u32 cycle)
342 {
343 unsigned int i, addr = 0, granularity;
344 unsigned int temp_ctl = 0;
345 unsigned int vme_bound, pci_offset;
346 struct vme_bridge *ca91cx42_bridge;
347 struct ca91cx42_driver *bridge;
348
349 ca91cx42_bridge = image->parent;
350
351 bridge = ca91cx42_bridge->driver_priv;
352
353 i = image->number;
354
355 switch (aspace) {
356 case VME_A16:
357 addr |= CA91CX42_VSI_CTL_VAS_A16;
358 break;
359 case VME_A24:
360 addr |= CA91CX42_VSI_CTL_VAS_A24;
361 break;
362 case VME_A32:
363 addr |= CA91CX42_VSI_CTL_VAS_A32;
364 break;
365 case VME_USER1:
366 addr |= CA91CX42_VSI_CTL_VAS_USER1;
367 break;
368 case VME_USER2:
369 addr |= CA91CX42_VSI_CTL_VAS_USER2;
370 break;
371 case VME_A64:
372 case VME_CRCSR:
373 case VME_USER3:
374 case VME_USER4:
375 default:
376 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
377 return -EINVAL;
378 break;
379 }
380
381 /*
382 * Bound address is a valid address for the window, adjust
383 * accordingly
384 */
385 vme_bound = vme_base + size;
386 pci_offset = pci_base - vme_base;
387
388 if ((i == 0) || (i == 4))
389 granularity = 0x1000;
390 else
391 granularity = 0x10000;
392
393 if (vme_base & (granularity - 1)) {
394 dev_err(ca91cx42_bridge->parent, "Invalid VME base "
395 "alignment\n");
396 return -EINVAL;
397 }
398 if (vme_bound & (granularity - 1)) {
399 dev_err(ca91cx42_bridge->parent, "Invalid VME bound "
400 "alignment\n");
401 return -EINVAL;
402 }
403 if (pci_offset & (granularity - 1)) {
404 dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset "
405 "alignment\n");
406 return -EINVAL;
407 }
408
409 /* Disable while we are mucking around */
410 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
411 temp_ctl &= ~CA91CX42_VSI_CTL_EN;
412 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
413
414 /* Setup mapping */
415 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
416 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
417 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
418
419 /* Setup address space */
420 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
421 temp_ctl |= addr;
422
423 /* Setup cycle types */
424 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
425 if (cycle & VME_SUPER)
426 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
427 if (cycle & VME_USER)
428 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
429 if (cycle & VME_PROG)
430 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
431 if (cycle & VME_DATA)
432 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
433
434 /* Write ctl reg without enable */
435 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
436
437 if (enabled)
438 temp_ctl |= CA91CX42_VSI_CTL_EN;
439
440 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
441
442 return 0;
443 }
444
445 static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
446 unsigned long long *vme_base, unsigned long long *size,
447 dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
448 {
449 unsigned int i, granularity = 0, ctl = 0;
450 unsigned long long vme_bound, pci_offset;
451 struct ca91cx42_driver *bridge;
452
453 bridge = image->parent->driver_priv;
454
455 i = image->number;
456
457 if ((i == 0) || (i == 4))
458 granularity = 0x1000;
459 else
460 granularity = 0x10000;
461
462 /* Read Registers */
463 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
464
465 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
466 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
467 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
468
469 *pci_base = (dma_addr_t)vme_base + pci_offset;
470 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
471
472 *enabled = 0;
473 *aspace = 0;
474 *cycle = 0;
475
476 if (ctl & CA91CX42_VSI_CTL_EN)
477 *enabled = 1;
478
479 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
480 *aspace = VME_A16;
481 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
482 *aspace = VME_A24;
483 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
484 *aspace = VME_A32;
485 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
486 *aspace = VME_USER1;
487 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
488 *aspace = VME_USER2;
489
490 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
491 *cycle |= VME_SUPER;
492 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
493 *cycle |= VME_USER;
494 if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
495 *cycle |= VME_PROG;
496 if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
497 *cycle |= VME_DATA;
498
499 return 0;
500 }
501
502 /*
503 * Allocate and map PCI Resource
504 */
505 static int ca91cx42_alloc_resource(struct vme_master_resource *image,
506 unsigned long long size)
507 {
508 unsigned long long existing_size;
509 int retval = 0;
510 struct pci_dev *pdev;
511 struct vme_bridge *ca91cx42_bridge;
512
513 ca91cx42_bridge = image->parent;
514
515 /* Find pci_dev container of dev */
516 if (ca91cx42_bridge->parent == NULL) {
517 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
518 return -EINVAL;
519 }
520 pdev = to_pci_dev(ca91cx42_bridge->parent);
521
522 existing_size = (unsigned long long)(image->bus_resource.end -
523 image->bus_resource.start);
524
525 /* If the existing size is OK, return */
526 if (existing_size == (size - 1))
527 return 0;
528
529 if (existing_size != 0) {
530 iounmap(image->kern_base);
531 image->kern_base = NULL;
532 kfree(image->bus_resource.name);
533 release_resource(&image->bus_resource);
534 memset(&image->bus_resource, 0, sizeof(struct resource));
535 }
536
537 if (image->bus_resource.name == NULL) {
538 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
539 if (image->bus_resource.name == NULL) {
540 dev_err(ca91cx42_bridge->parent, "Unable to allocate "
541 "memory for resource name\n");
542 retval = -ENOMEM;
543 goto err_name;
544 }
545 }
546
547 sprintf((char *)image->bus_resource.name, "%s.%d",
548 ca91cx42_bridge->name, image->number);
549
550 image->bus_resource.start = 0;
551 image->bus_resource.end = (unsigned long)size;
552 image->bus_resource.flags = IORESOURCE_MEM;
553
554 retval = pci_bus_alloc_resource(pdev->bus,
555 &image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM,
556 0, NULL, NULL);
557 if (retval) {
558 dev_err(ca91cx42_bridge->parent, "Failed to allocate mem "
559 "resource for window %d size 0x%lx start 0x%lx\n",
560 image->number, (unsigned long)size,
561 (unsigned long)image->bus_resource.start);
562 goto err_resource;
563 }
564
565 image->kern_base = ioremap_nocache(
566 image->bus_resource.start, size);
567 if (image->kern_base == NULL) {
568 dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n");
569 retval = -ENOMEM;
570 goto err_remap;
571 }
572
573 return 0;
574
575 err_remap:
576 release_resource(&image->bus_resource);
577 err_resource:
578 kfree(image->bus_resource.name);
579 memset(&image->bus_resource, 0, sizeof(struct resource));
580 err_name:
581 return retval;
582 }
583
584 /*
585 * Free and unmap PCI Resource
586 */
587 static void ca91cx42_free_resource(struct vme_master_resource *image)
588 {
589 iounmap(image->kern_base);
590 image->kern_base = NULL;
591 release_resource(&image->bus_resource);
592 kfree(image->bus_resource.name);
593 memset(&image->bus_resource, 0, sizeof(struct resource));
594 }
595
596
597 static int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
598 unsigned long long vme_base, unsigned long long size, u32 aspace,
599 u32 cycle, u32 dwidth)
600 {
601 int retval = 0;
602 unsigned int i, granularity = 0;
603 unsigned int temp_ctl = 0;
604 unsigned long long pci_bound, vme_offset, pci_base;
605 struct vme_bridge *ca91cx42_bridge;
606 struct ca91cx42_driver *bridge;
607
608 ca91cx42_bridge = image->parent;
609
610 bridge = ca91cx42_bridge->driver_priv;
611
612 i = image->number;
613
614 if ((i == 0) || (i == 4))
615 granularity = 0x1000;
616 else
617 granularity = 0x10000;
618
619 /* Verify input data */
620 if (vme_base & (granularity - 1)) {
621 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
622 "alignment\n");
623 retval = -EINVAL;
624 goto err_window;
625 }
626 if (size & (granularity - 1)) {
627 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
628 "alignment\n");
629 retval = -EINVAL;
630 goto err_window;
631 }
632
633 spin_lock(&image->lock);
634
635 /*
636 * Let's allocate the resource here rather than further up the stack as
637 * it avoids pushing loads of bus dependent stuff up the stack
638 */
639 retval = ca91cx42_alloc_resource(image, size);
640 if (retval) {
641 spin_unlock(&image->lock);
642 dev_err(ca91cx42_bridge->parent, "Unable to allocate memory "
643 "for resource name\n");
644 retval = -ENOMEM;
645 goto err_res;
646 }
647
648 pci_base = (unsigned long long)image->bus_resource.start;
649
650 /*
651 * Bound address is a valid address for the window, adjust
652 * according to window granularity.
653 */
654 pci_bound = pci_base + size;
655 vme_offset = vme_base - pci_base;
656
657 /* Disable while we are mucking around */
658 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
659 temp_ctl &= ~CA91CX42_LSI_CTL_EN;
660 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
661
662 /* Setup cycle types */
663 temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
664 if (cycle & VME_BLT)
665 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
666 if (cycle & VME_MBLT)
667 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
668
669 /* Setup data width */
670 temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
671 switch (dwidth) {
672 case VME_D8:
673 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
674 break;
675 case VME_D16:
676 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
677 break;
678 case VME_D32:
679 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
680 break;
681 case VME_D64:
682 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
683 break;
684 default:
685 spin_unlock(&image->lock);
686 dev_err(ca91cx42_bridge->parent, "Invalid data width\n");
687 retval = -EINVAL;
688 goto err_dwidth;
689 break;
690 }
691
692 /* Setup address space */
693 temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
694 switch (aspace) {
695 case VME_A16:
696 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
697 break;
698 case VME_A24:
699 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
700 break;
701 case VME_A32:
702 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
703 break;
704 case VME_CRCSR:
705 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
706 break;
707 case VME_USER1:
708 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
709 break;
710 case VME_USER2:
711 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
712 break;
713 case VME_A64:
714 case VME_USER3:
715 case VME_USER4:
716 default:
717 spin_unlock(&image->lock);
718 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
719 retval = -EINVAL;
720 goto err_aspace;
721 break;
722 }
723
724 temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
725 if (cycle & VME_SUPER)
726 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
727 if (cycle & VME_PROG)
728 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
729
730 /* Setup mapping */
731 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
732 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
733 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
734
735 /* Write ctl reg without enable */
736 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
737
738 if (enabled)
739 temp_ctl |= CA91CX42_LSI_CTL_EN;
740
741 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
742
743 spin_unlock(&image->lock);
744 return 0;
745
746 err_aspace:
747 err_dwidth:
748 ca91cx42_free_resource(image);
749 err_res:
750 err_window:
751 return retval;
752 }
753
754 static int __ca91cx42_master_get(struct vme_master_resource *image,
755 int *enabled, unsigned long long *vme_base, unsigned long long *size,
756 u32 *aspace, u32 *cycle, u32 *dwidth)
757 {
758 unsigned int i, ctl;
759 unsigned long long pci_base, pci_bound, vme_offset;
760 struct ca91cx42_driver *bridge;
761
762 bridge = image->parent->driver_priv;
763
764 i = image->number;
765
766 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
767
768 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
769 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
770 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
771
772 *vme_base = pci_base + vme_offset;
773 *size = (unsigned long long)(pci_bound - pci_base);
774
775 *enabled = 0;
776 *aspace = 0;
777 *cycle = 0;
778 *dwidth = 0;
779
780 if (ctl & CA91CX42_LSI_CTL_EN)
781 *enabled = 1;
782
783 /* Setup address space */
784 switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
785 case CA91CX42_LSI_CTL_VAS_A16:
786 *aspace = VME_A16;
787 break;
788 case CA91CX42_LSI_CTL_VAS_A24:
789 *aspace = VME_A24;
790 break;
791 case CA91CX42_LSI_CTL_VAS_A32:
792 *aspace = VME_A32;
793 break;
794 case CA91CX42_LSI_CTL_VAS_CRCSR:
795 *aspace = VME_CRCSR;
796 break;
797 case CA91CX42_LSI_CTL_VAS_USER1:
798 *aspace = VME_USER1;
799 break;
800 case CA91CX42_LSI_CTL_VAS_USER2:
801 *aspace = VME_USER2;
802 break;
803 }
804
805 /* XXX Not sure howto check for MBLT */
806 /* Setup cycle types */
807 if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
808 *cycle |= VME_BLT;
809 else
810 *cycle |= VME_SCT;
811
812 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
813 *cycle |= VME_SUPER;
814 else
815 *cycle |= VME_USER;
816
817 if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
818 *cycle = VME_PROG;
819 else
820 *cycle = VME_DATA;
821
822 /* Setup data width */
823 switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
824 case CA91CX42_LSI_CTL_VDW_D8:
825 *dwidth = VME_D8;
826 break;
827 case CA91CX42_LSI_CTL_VDW_D16:
828 *dwidth = VME_D16;
829 break;
830 case CA91CX42_LSI_CTL_VDW_D32:
831 *dwidth = VME_D32;
832 break;
833 case CA91CX42_LSI_CTL_VDW_D64:
834 *dwidth = VME_D64;
835 break;
836 }
837
838 return 0;
839 }
840
841 static int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
842 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
843 u32 *cycle, u32 *dwidth)
844 {
845 int retval;
846
847 spin_lock(&image->lock);
848
849 retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
850 cycle, dwidth);
851
852 spin_unlock(&image->lock);
853
854 return retval;
855 }
856
857 static ssize_t ca91cx42_master_read(struct vme_master_resource *image,
858 void *buf, size_t count, loff_t offset)
859 {
860 ssize_t retval;
861 void __iomem *addr = image->kern_base + offset;
862 unsigned int done = 0;
863 unsigned int count32;
864
865 if (count == 0)
866 return 0;
867
868 spin_lock(&image->lock);
869
870 /* The following code handles VME address alignment. We cannot use
871 * memcpy_xxx here because it may cut data transfers in to 8-bit
872 * cycles when D16 or D32 cycles are required on the VME bus.
873 * On the other hand, the bridge itself assures that the maximum data
874 * cycle configured for the transfer is used and splits it
875 * automatically for non-aligned addresses, so we don't want the
876 * overhead of needlessly forcing small transfers for the entire cycle.
877 */
878 if ((uintptr_t)addr & 0x1) {
879 *(u8 *)buf = ioread8(addr);
880 done += 1;
881 if (done == count)
882 goto out;
883 }
884 if ((uintptr_t)(addr + done) & 0x2) {
885 if ((count - done) < 2) {
886 *(u8 *)(buf + done) = ioread8(addr + done);
887 done += 1;
888 goto out;
889 } else {
890 *(u16 *)(buf + done) = ioread16(addr + done);
891 done += 2;
892 }
893 }
894
895 count32 = (count - done) & ~0x3;
896 while (done < count32) {
897 *(u32 *)(buf + done) = ioread32(addr + done);
898 done += 4;
899 }
900
901 if ((count - done) & 0x2) {
902 *(u16 *)(buf + done) = ioread16(addr + done);
903 done += 2;
904 }
905 if ((count - done) & 0x1) {
906 *(u8 *)(buf + done) = ioread8(addr + done);
907 done += 1;
908 }
909 out:
910 retval = count;
911 spin_unlock(&image->lock);
912
913 return retval;
914 }
915
916 static ssize_t ca91cx42_master_write(struct vme_master_resource *image,
917 void *buf, size_t count, loff_t offset)
918 {
919 ssize_t retval;
920 void __iomem *addr = image->kern_base + offset;
921 unsigned int done = 0;
922 unsigned int count32;
923
924 if (count == 0)
925 return 0;
926
927 spin_lock(&image->lock);
928
929 /* Here we apply for the same strategy we do in master_read
930 * function in order to assure the correct cycles.
931 */
932 if ((uintptr_t)addr & 0x1) {
933 iowrite8(*(u8 *)buf, addr);
934 done += 1;
935 if (done == count)
936 goto out;
937 }
938 if ((uintptr_t)(addr + done) & 0x2) {
939 if ((count - done) < 2) {
940 iowrite8(*(u8 *)(buf + done), addr + done);
941 done += 1;
942 goto out;
943 } else {
944 iowrite16(*(u16 *)(buf + done), addr + done);
945 done += 2;
946 }
947 }
948
949 count32 = (count - done) & ~0x3;
950 while (done < count32) {
951 iowrite32(*(u32 *)(buf + done), addr + done);
952 done += 4;
953 }
954
955 if ((count - done) & 0x2) {
956 iowrite16(*(u16 *)(buf + done), addr + done);
957 done += 2;
958 }
959 if ((count - done) & 0x1) {
960 iowrite8(*(u8 *)(buf + done), addr + done);
961 done += 1;
962 }
963 out:
964 retval = count;
965
966 spin_unlock(&image->lock);
967
968 return retval;
969 }
970
971 static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
972 unsigned int mask, unsigned int compare, unsigned int swap,
973 loff_t offset)
974 {
975 u32 result;
976 uintptr_t pci_addr;
977 int i;
978 struct ca91cx42_driver *bridge;
979 struct device *dev;
980
981 bridge = image->parent->driver_priv;
982 dev = image->parent->parent;
983
984 /* Find the PCI address that maps to the desired VME address */
985 i = image->number;
986
987 /* Locking as we can only do one of these at a time */
988 mutex_lock(&bridge->vme_rmw);
989
990 /* Lock image */
991 spin_lock(&image->lock);
992
993 pci_addr = (uintptr_t)image->kern_base + offset;
994
995 /* Address must be 4-byte aligned */
996 if (pci_addr & 0x3) {
997 dev_err(dev, "RMW Address not 4-byte aligned\n");
998 result = -EINVAL;
999 goto out;
1000 }
1001
1002 /* Ensure RMW Disabled whilst configuring */
1003 iowrite32(0, bridge->base + SCYC_CTL);
1004
1005 /* Configure registers */
1006 iowrite32(mask, bridge->base + SCYC_EN);
1007 iowrite32(compare, bridge->base + SCYC_CMP);
1008 iowrite32(swap, bridge->base + SCYC_SWP);
1009 iowrite32(pci_addr, bridge->base + SCYC_ADDR);
1010
1011 /* Enable RMW */
1012 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
1013
1014 /* Kick process off with a read to the required address. */
1015 result = ioread32(image->kern_base + offset);
1016
1017 /* Disable RMW */
1018 iowrite32(0, bridge->base + SCYC_CTL);
1019
1020 out:
1021 spin_unlock(&image->lock);
1022
1023 mutex_unlock(&bridge->vme_rmw);
1024
1025 return result;
1026 }
1027
1028 static int ca91cx42_dma_list_add(struct vme_dma_list *list,
1029 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1030 {
1031 struct ca91cx42_dma_entry *entry, *prev;
1032 struct vme_dma_pci *pci_attr;
1033 struct vme_dma_vme *vme_attr;
1034 dma_addr_t desc_ptr;
1035 int retval = 0;
1036 struct device *dev;
1037
1038 dev = list->parent->parent->parent;
1039
1040 /* XXX descriptor must be aligned on 64-bit boundaries */
1041 entry = kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
1042 if (entry == NULL) {
1043 dev_err(dev, "Failed to allocate memory for dma resource "
1044 "structure\n");
1045 retval = -ENOMEM;
1046 goto err_mem;
1047 }
1048
1049 /* Test descriptor alignment */
1050 if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {
1051 dev_err(dev, "Descriptor not aligned to 16 byte boundary as "
1052 "required: %p\n", &entry->descriptor);
1053 retval = -EINVAL;
1054 goto err_align;
1055 }
1056
1057 memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor));
1058
1059 if (dest->type == VME_DMA_VME) {
1060 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
1061 vme_attr = dest->private;
1062 pci_attr = src->private;
1063 } else {
1064 vme_attr = src->private;
1065 pci_attr = dest->private;
1066 }
1067
1068 /* Check we can do fulfill required attributes */
1069 if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1070 VME_USER2)) != 0) {
1071
1072 dev_err(dev, "Unsupported cycle type\n");
1073 retval = -EINVAL;
1074 goto err_aspace;
1075 }
1076
1077 if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1078 VME_PROG | VME_DATA)) != 0) {
1079
1080 dev_err(dev, "Unsupported cycle type\n");
1081 retval = -EINVAL;
1082 goto err_cycle;
1083 }
1084
1085 /* Check to see if we can fulfill source and destination */
1086 if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1087 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1088
1089 dev_err(dev, "Cannot perform transfer with this "
1090 "source-destination combination\n");
1091 retval = -EINVAL;
1092 goto err_direct;
1093 }
1094
1095 /* Setup cycle types */
1096 if (vme_attr->cycle & VME_BLT)
1097 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1098
1099 /* Setup data width */
1100 switch (vme_attr->dwidth) {
1101 case VME_D8:
1102 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1103 break;
1104 case VME_D16:
1105 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1106 break;
1107 case VME_D32:
1108 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1109 break;
1110 case VME_D64:
1111 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1112 break;
1113 default:
1114 dev_err(dev, "Invalid data width\n");
1115 return -EINVAL;
1116 }
1117
1118 /* Setup address space */
1119 switch (vme_attr->aspace) {
1120 case VME_A16:
1121 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1122 break;
1123 case VME_A24:
1124 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1125 break;
1126 case VME_A32:
1127 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1128 break;
1129 case VME_USER1:
1130 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1131 break;
1132 case VME_USER2:
1133 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1134 break;
1135 default:
1136 dev_err(dev, "Invalid address space\n");
1137 return -EINVAL;
1138 break;
1139 }
1140
1141 if (vme_attr->cycle & VME_SUPER)
1142 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1143 if (vme_attr->cycle & VME_PROG)
1144 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1145
1146 entry->descriptor.dtbc = count;
1147 entry->descriptor.dla = pci_attr->address;
1148 entry->descriptor.dva = vme_attr->address;
1149 entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1150
1151 /* Add to list */
1152 list_add_tail(&entry->list, &list->entries);
1153
1154 /* Fill out previous descriptors "Next Address" */
1155 if (entry->list.prev != &list->entries) {
1156 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1157 list);
1158 /* We need the bus address for the pointer */
1159 desc_ptr = virt_to_bus(&entry->descriptor);
1160 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1161 }
1162
1163 return 0;
1164
1165 err_cycle:
1166 err_aspace:
1167 err_direct:
1168 err_align:
1169 kfree(entry);
1170 err_mem:
1171 return retval;
1172 }
1173
1174 static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1175 {
1176 u32 tmp;
1177 struct ca91cx42_driver *bridge;
1178
1179 bridge = ca91cx42_bridge->driver_priv;
1180
1181 tmp = ioread32(bridge->base + DGCS);
1182
1183 if (tmp & CA91CX42_DGCS_ACT)
1184 return 0;
1185 else
1186 return 1;
1187 }
1188
1189 static int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1190 {
1191 struct vme_dma_resource *ctrlr;
1192 struct ca91cx42_dma_entry *entry;
1193 int retval;
1194 dma_addr_t bus_addr;
1195 u32 val;
1196 struct device *dev;
1197 struct ca91cx42_driver *bridge;
1198
1199 ctrlr = list->parent;
1200
1201 bridge = ctrlr->parent->driver_priv;
1202 dev = ctrlr->parent->parent;
1203
1204 mutex_lock(&ctrlr->mtx);
1205
1206 if (!(list_empty(&ctrlr->running))) {
1207 /*
1208 * XXX We have an active DMA transfer and currently haven't
1209 * sorted out the mechanism for "pending" DMA transfers.
1210 * Return busy.
1211 */
1212 /* Need to add to pending here */
1213 mutex_unlock(&ctrlr->mtx);
1214 return -EBUSY;
1215 } else {
1216 list_add(&list->list, &ctrlr->running);
1217 }
1218
1219 /* Get first bus address and write into registers */
1220 entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry,
1221 list);
1222
1223 bus_addr = virt_to_bus(&entry->descriptor);
1224
1225 mutex_unlock(&ctrlr->mtx);
1226
1227 iowrite32(0, bridge->base + DTBC);
1228 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1229
1230 /* Start the operation */
1231 val = ioread32(bridge->base + DGCS);
1232
1233 /* XXX Could set VMEbus On and Off Counters here */
1234 val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1235
1236 val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1237 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1238 CA91CX42_DGCS_PERR);
1239
1240 iowrite32(val, bridge->base + DGCS);
1241
1242 val |= CA91CX42_DGCS_GO;
1243
1244 iowrite32(val, bridge->base + DGCS);
1245
1246 retval = wait_event_interruptible(bridge->dma_queue,
1247 ca91cx42_dma_busy(ctrlr->parent));
1248
1249 if (retval) {
1250 val = ioread32(bridge->base + DGCS);
1251 iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS);
1252 /* Wait for the operation to abort */
1253 wait_event(bridge->dma_queue,
1254 ca91cx42_dma_busy(ctrlr->parent));
1255 retval = -EINTR;
1256 goto exit;
1257 }
1258
1259 /*
1260 * Read status register, this register is valid until we kick off a
1261 * new transfer.
1262 */
1263 val = ioread32(bridge->base + DGCS);
1264
1265 if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1266 CA91CX42_DGCS_PERR)) {
1267
1268 dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val);
1269 val = ioread32(bridge->base + DCTL);
1270 retval = -EIO;
1271 }
1272
1273 exit:
1274 /* Remove list from running list */
1275 mutex_lock(&ctrlr->mtx);
1276 list_del(&list->list);
1277 mutex_unlock(&ctrlr->mtx);
1278
1279 return retval;
1280
1281 }
1282
1283 static int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1284 {
1285 struct list_head *pos, *temp;
1286 struct ca91cx42_dma_entry *entry;
1287
1288 /* detach and free each entry */
1289 list_for_each_safe(pos, temp, &list->entries) {
1290 list_del(pos);
1291 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1292 kfree(entry);
1293 }
1294
1295 return 0;
1296 }
1297
1298 /*
1299 * All 4 location monitors reside at the same base - this is therefore a
1300 * system wide configuration.
1301 *
1302 * This does not enable the LM monitor - that should be done when the first
1303 * callback is attached and disabled when the last callback is removed.
1304 */
1305 static int ca91cx42_lm_set(struct vme_lm_resource *lm,
1306 unsigned long long lm_base, u32 aspace, u32 cycle)
1307 {
1308 u32 temp_base, lm_ctl = 0;
1309 int i;
1310 struct ca91cx42_driver *bridge;
1311 struct device *dev;
1312
1313 bridge = lm->parent->driver_priv;
1314 dev = lm->parent->parent;
1315
1316 /* Check the alignment of the location monitor */
1317 temp_base = (u32)lm_base;
1318 if (temp_base & 0xffff) {
1319 dev_err(dev, "Location monitor must be aligned to 64KB "
1320 "boundary");
1321 return -EINVAL;
1322 }
1323
1324 mutex_lock(&lm->mtx);
1325
1326 /* If we already have a callback attached, we can't move it! */
1327 for (i = 0; i < lm->monitors; i++) {
1328 if (bridge->lm_callback[i] != NULL) {
1329 mutex_unlock(&lm->mtx);
1330 dev_err(dev, "Location monitor callback attached, "
1331 "can't reset\n");
1332 return -EBUSY;
1333 }
1334 }
1335
1336 switch (aspace) {
1337 case VME_A16:
1338 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1339 break;
1340 case VME_A24:
1341 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1342 break;
1343 case VME_A32:
1344 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1345 break;
1346 default:
1347 mutex_unlock(&lm->mtx);
1348 dev_err(dev, "Invalid address space\n");
1349 return -EINVAL;
1350 break;
1351 }
1352
1353 if (cycle & VME_SUPER)
1354 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1355 if (cycle & VME_USER)
1356 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1357 if (cycle & VME_PROG)
1358 lm_ctl |= CA91CX42_LM_CTL_PGM;
1359 if (cycle & VME_DATA)
1360 lm_ctl |= CA91CX42_LM_CTL_DATA;
1361
1362 iowrite32(lm_base, bridge->base + LM_BS);
1363 iowrite32(lm_ctl, bridge->base + LM_CTL);
1364
1365 mutex_unlock(&lm->mtx);
1366
1367 return 0;
1368 }
1369
1370 /* Get configuration of the callback monitor and return whether it is enabled
1371 * or disabled.
1372 */
1373 static int ca91cx42_lm_get(struct vme_lm_resource *lm,
1374 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
1375 {
1376 u32 lm_ctl, enabled = 0;
1377 struct ca91cx42_driver *bridge;
1378
1379 bridge = lm->parent->driver_priv;
1380
1381 mutex_lock(&lm->mtx);
1382
1383 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1384 lm_ctl = ioread32(bridge->base + LM_CTL);
1385
1386 if (lm_ctl & CA91CX42_LM_CTL_EN)
1387 enabled = 1;
1388
1389 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1390 *aspace = VME_A16;
1391 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1392 *aspace = VME_A24;
1393 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1394 *aspace = VME_A32;
1395
1396 *cycle = 0;
1397 if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1398 *cycle |= VME_SUPER;
1399 if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1400 *cycle |= VME_USER;
1401 if (lm_ctl & CA91CX42_LM_CTL_PGM)
1402 *cycle |= VME_PROG;
1403 if (lm_ctl & CA91CX42_LM_CTL_DATA)
1404 *cycle |= VME_DATA;
1405
1406 mutex_unlock(&lm->mtx);
1407
1408 return enabled;
1409 }
1410
1411 /*
1412 * Attach a callback to a specific location monitor.
1413 *
1414 * Callback will be passed the monitor triggered.
1415 */
1416 static int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1417 void (*callback)(int))
1418 {
1419 u32 lm_ctl, tmp;
1420 struct ca91cx42_driver *bridge;
1421 struct device *dev;
1422
1423 bridge = lm->parent->driver_priv;
1424 dev = lm->parent->parent;
1425
1426 mutex_lock(&lm->mtx);
1427
1428 /* Ensure that the location monitor is configured - need PGM or DATA */
1429 lm_ctl = ioread32(bridge->base + LM_CTL);
1430 if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1431 mutex_unlock(&lm->mtx);
1432 dev_err(dev, "Location monitor not properly configured\n");
1433 return -EINVAL;
1434 }
1435
1436 /* Check that a callback isn't already attached */
1437 if (bridge->lm_callback[monitor] != NULL) {
1438 mutex_unlock(&lm->mtx);
1439 dev_err(dev, "Existing callback attached\n");
1440 return -EBUSY;
1441 }
1442
1443 /* Attach callback */
1444 bridge->lm_callback[monitor] = callback;
1445
1446 /* Enable Location Monitor interrupt */
1447 tmp = ioread32(bridge->base + LINT_EN);
1448 tmp |= CA91CX42_LINT_LM[monitor];
1449 iowrite32(tmp, bridge->base + LINT_EN);
1450
1451 /* Ensure that global Location Monitor Enable set */
1452 if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1453 lm_ctl |= CA91CX42_LM_CTL_EN;
1454 iowrite32(lm_ctl, bridge->base + LM_CTL);
1455 }
1456
1457 mutex_unlock(&lm->mtx);
1458
1459 return 0;
1460 }
1461
1462 /*
1463 * Detach a callback function forn a specific location monitor.
1464 */
1465 static int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1466 {
1467 u32 tmp;
1468 struct ca91cx42_driver *bridge;
1469
1470 bridge = lm->parent->driver_priv;
1471
1472 mutex_lock(&lm->mtx);
1473
1474 /* Disable Location Monitor and ensure previous interrupts are clear */
1475 tmp = ioread32(bridge->base + LINT_EN);
1476 tmp &= ~CA91CX42_LINT_LM[monitor];
1477 iowrite32(tmp, bridge->base + LINT_EN);
1478
1479 iowrite32(CA91CX42_LINT_LM[monitor],
1480 bridge->base + LINT_STAT);
1481
1482 /* Detach callback */
1483 bridge->lm_callback[monitor] = NULL;
1484
1485 /* If all location monitors disabled, disable global Location Monitor */
1486 if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1487 CA91CX42_LINT_LM3)) == 0) {
1488 tmp = ioread32(bridge->base + LM_CTL);
1489 tmp &= ~CA91CX42_LM_CTL_EN;
1490 iowrite32(tmp, bridge->base + LM_CTL);
1491 }
1492
1493 mutex_unlock(&lm->mtx);
1494
1495 return 0;
1496 }
1497
1498 static int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1499 {
1500 u32 slot = 0;
1501 struct ca91cx42_driver *bridge;
1502
1503 bridge = ca91cx42_bridge->driver_priv;
1504
1505 if (!geoid) {
1506 slot = ioread32(bridge->base + VCSR_BS);
1507 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1508 } else
1509 slot = geoid;
1510
1511 return (int)slot;
1512
1513 }
1514
1515 static void *ca91cx42_alloc_consistent(struct device *parent, size_t size,
1516 dma_addr_t *dma)
1517 {
1518 struct pci_dev *pdev;
1519
1520 /* Find pci_dev container of dev */
1521 pdev = to_pci_dev(parent);
1522
1523 return pci_alloc_consistent(pdev, size, dma);
1524 }
1525
1526 static void ca91cx42_free_consistent(struct device *parent, size_t size,
1527 void *vaddr, dma_addr_t dma)
1528 {
1529 struct pci_dev *pdev;
1530
1531 /* Find pci_dev container of dev */
1532 pdev = to_pci_dev(parent);
1533
1534 pci_free_consistent(pdev, size, vaddr, dma);
1535 }
1536
1537 /*
1538 * Configure CR/CSR space
1539 *
1540 * Access to the CR/CSR can be configured at power-up. The location of the
1541 * CR/CSR registers in the CR/CSR address space is determined by the boards
1542 * Auto-ID or Geographic address. This function ensures that the window is
1543 * enabled at an offset consistent with the boards geopgraphic address.
1544 */
1545 static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1546 struct pci_dev *pdev)
1547 {
1548 unsigned int crcsr_addr;
1549 int tmp, slot;
1550 struct ca91cx42_driver *bridge;
1551
1552 bridge = ca91cx42_bridge->driver_priv;
1553
1554 slot = ca91cx42_slot_get(ca91cx42_bridge);
1555
1556 /* Write CSR Base Address if slot ID is supplied as a module param */
1557 if (geoid)
1558 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1559
1560 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1561 if (slot == 0) {
1562 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1563 "CR/CSR space\n");
1564 return -EINVAL;
1565 }
1566
1567 /* Allocate mem for CR/CSR image */
1568 bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1569 &bridge->crcsr_bus);
1570 if (bridge->crcsr_kernel == NULL) {
1571 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1572 "image\n");
1573 return -ENOMEM;
1574 }
1575
1576 crcsr_addr = slot * (512 * 1024);
1577 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1578
1579 tmp = ioread32(bridge->base + VCSR_CTL);
1580 tmp |= CA91CX42_VCSR_CTL_EN;
1581 iowrite32(tmp, bridge->base + VCSR_CTL);
1582
1583 return 0;
1584 }
1585
1586 static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1587 struct pci_dev *pdev)
1588 {
1589 u32 tmp;
1590 struct ca91cx42_driver *bridge;
1591
1592 bridge = ca91cx42_bridge->driver_priv;
1593
1594 /* Turn off CR/CSR space */
1595 tmp = ioread32(bridge->base + VCSR_CTL);
1596 tmp &= ~CA91CX42_VCSR_CTL_EN;
1597 iowrite32(tmp, bridge->base + VCSR_CTL);
1598
1599 /* Free image */
1600 iowrite32(0, bridge->base + VCSR_TO);
1601
1602 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1603 bridge->crcsr_bus);
1604 }
1605
1606 static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1607 {
1608 int retval, i;
1609 u32 data;
1610 struct list_head *pos = NULL, *n;
1611 struct vme_bridge *ca91cx42_bridge;
1612 struct ca91cx42_driver *ca91cx42_device;
1613 struct vme_master_resource *master_image;
1614 struct vme_slave_resource *slave_image;
1615 struct vme_dma_resource *dma_ctrlr;
1616 struct vme_lm_resource *lm;
1617
1618 /* We want to support more than one of each bridge so we need to
1619 * dynamically allocate the bridge structure
1620 */
1621 ca91cx42_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1622
1623 if (ca91cx42_bridge == NULL) {
1624 dev_err(&pdev->dev, "Failed to allocate memory for device "
1625 "structure\n");
1626 retval = -ENOMEM;
1627 goto err_struct;
1628 }
1629
1630 ca91cx42_device = kzalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1631
1632 if (ca91cx42_device == NULL) {
1633 dev_err(&pdev->dev, "Failed to allocate memory for device "
1634 "structure\n");
1635 retval = -ENOMEM;
1636 goto err_driver;
1637 }
1638
1639 ca91cx42_bridge->driver_priv = ca91cx42_device;
1640
1641 /* Enable the device */
1642 retval = pci_enable_device(pdev);
1643 if (retval) {
1644 dev_err(&pdev->dev, "Unable to enable device\n");
1645 goto err_enable;
1646 }
1647
1648 /* Map Registers */
1649 retval = pci_request_regions(pdev, driver_name);
1650 if (retval) {
1651 dev_err(&pdev->dev, "Unable to reserve resources\n");
1652 goto err_resource;
1653 }
1654
1655 /* map registers in BAR 0 */
1656 ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1657 4096);
1658 if (!ca91cx42_device->base) {
1659 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1660 retval = -EIO;
1661 goto err_remap;
1662 }
1663
1664 /* Check to see if the mapping worked out */
1665 data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1666 if (data != PCI_VENDOR_ID_TUNDRA) {
1667 dev_err(&pdev->dev, "PCI_ID check failed\n");
1668 retval = -EIO;
1669 goto err_test;
1670 }
1671
1672 /* Initialize wait queues & mutual exclusion flags */
1673 init_waitqueue_head(&ca91cx42_device->dma_queue);
1674 init_waitqueue_head(&ca91cx42_device->iack_queue);
1675 mutex_init(&ca91cx42_device->vme_int);
1676 mutex_init(&ca91cx42_device->vme_rmw);
1677
1678 ca91cx42_bridge->parent = &pdev->dev;
1679 strcpy(ca91cx42_bridge->name, driver_name);
1680
1681 /* Setup IRQ */
1682 retval = ca91cx42_irq_init(ca91cx42_bridge);
1683 if (retval != 0) {
1684 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1685 goto err_irq;
1686 }
1687
1688 /* Add master windows to list */
1689 INIT_LIST_HEAD(&ca91cx42_bridge->master_resources);
1690 for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1691 master_image = kmalloc(sizeof(struct vme_master_resource),
1692 GFP_KERNEL);
1693 if (master_image == NULL) {
1694 dev_err(&pdev->dev, "Failed to allocate memory for "
1695 "master resource structure\n");
1696 retval = -ENOMEM;
1697 goto err_master;
1698 }
1699 master_image->parent = ca91cx42_bridge;
1700 spin_lock_init(&master_image->lock);
1701 master_image->locked = 0;
1702 master_image->number = i;
1703 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1704 VME_CRCSR | VME_USER1 | VME_USER2;
1705 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1706 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1707 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1708 memset(&master_image->bus_resource, 0,
1709 sizeof(struct resource));
1710 master_image->kern_base = NULL;
1711 list_add_tail(&master_image->list,
1712 &ca91cx42_bridge->master_resources);
1713 }
1714
1715 /* Add slave windows to list */
1716 INIT_LIST_HEAD(&ca91cx42_bridge->slave_resources);
1717 for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1718 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1719 GFP_KERNEL);
1720 if (slave_image == NULL) {
1721 dev_err(&pdev->dev, "Failed to allocate memory for "
1722 "slave resource structure\n");
1723 retval = -ENOMEM;
1724 goto err_slave;
1725 }
1726 slave_image->parent = ca91cx42_bridge;
1727 mutex_init(&slave_image->mtx);
1728 slave_image->locked = 0;
1729 slave_image->number = i;
1730 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1731 VME_USER2;
1732
1733 /* Only windows 0 and 4 support A16 */
1734 if (i == 0 || i == 4)
1735 slave_image->address_attr |= VME_A16;
1736
1737 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1738 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1739 list_add_tail(&slave_image->list,
1740 &ca91cx42_bridge->slave_resources);
1741 }
1742
1743 /* Add dma engines to list */
1744 INIT_LIST_HEAD(&ca91cx42_bridge->dma_resources);
1745 for (i = 0; i < CA91C142_MAX_DMA; i++) {
1746 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1747 GFP_KERNEL);
1748 if (dma_ctrlr == NULL) {
1749 dev_err(&pdev->dev, "Failed to allocate memory for "
1750 "dma resource structure\n");
1751 retval = -ENOMEM;
1752 goto err_dma;
1753 }
1754 dma_ctrlr->parent = ca91cx42_bridge;
1755 mutex_init(&dma_ctrlr->mtx);
1756 dma_ctrlr->locked = 0;
1757 dma_ctrlr->number = i;
1758 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1759 VME_DMA_MEM_TO_VME;
1760 INIT_LIST_HEAD(&dma_ctrlr->pending);
1761 INIT_LIST_HEAD(&dma_ctrlr->running);
1762 list_add_tail(&dma_ctrlr->list,
1763 &ca91cx42_bridge->dma_resources);
1764 }
1765
1766 /* Add location monitor to list */
1767 INIT_LIST_HEAD(&ca91cx42_bridge->lm_resources);
1768 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1769 if (lm == NULL) {
1770 dev_err(&pdev->dev, "Failed to allocate memory for "
1771 "location monitor resource structure\n");
1772 retval = -ENOMEM;
1773 goto err_lm;
1774 }
1775 lm->parent = ca91cx42_bridge;
1776 mutex_init(&lm->mtx);
1777 lm->locked = 0;
1778 lm->number = 1;
1779 lm->monitors = 4;
1780 list_add_tail(&lm->list, &ca91cx42_bridge->lm_resources);
1781
1782 ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1783 ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1784 ca91cx42_bridge->master_get = ca91cx42_master_get;
1785 ca91cx42_bridge->master_set = ca91cx42_master_set;
1786 ca91cx42_bridge->master_read = ca91cx42_master_read;
1787 ca91cx42_bridge->master_write = ca91cx42_master_write;
1788 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1789 ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1790 ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1791 ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1792 ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1793 ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1794 ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1795 ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1796 ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1797 ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1798 ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1799 ca91cx42_bridge->alloc_consistent = ca91cx42_alloc_consistent;
1800 ca91cx42_bridge->free_consistent = ca91cx42_free_consistent;
1801
1802 data = ioread32(ca91cx42_device->base + MISC_CTL);
1803 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1804 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1805 dev_info(&pdev->dev, "Slot ID is %d\n",
1806 ca91cx42_slot_get(ca91cx42_bridge));
1807
1808 if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
1809 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1810
1811 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1812 * ca91cx42_remove()
1813 */
1814 retval = vme_register_bridge(ca91cx42_bridge);
1815 if (retval != 0) {
1816 dev_err(&pdev->dev, "Chip Registration failed.\n");
1817 goto err_reg;
1818 }
1819
1820 pci_set_drvdata(pdev, ca91cx42_bridge);
1821
1822 return 0;
1823
1824 err_reg:
1825 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1826 err_lm:
1827 /* resources are stored in link list */
1828 list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
1829 lm = list_entry(pos, struct vme_lm_resource, list);
1830 list_del(pos);
1831 kfree(lm);
1832 }
1833 err_dma:
1834 /* resources are stored in link list */
1835 list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
1836 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1837 list_del(pos);
1838 kfree(dma_ctrlr);
1839 }
1840 err_slave:
1841 /* resources are stored in link list */
1842 list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
1843 slave_image = list_entry(pos, struct vme_slave_resource, list);
1844 list_del(pos);
1845 kfree(slave_image);
1846 }
1847 err_master:
1848 /* resources are stored in link list */
1849 list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
1850 master_image = list_entry(pos, struct vme_master_resource,
1851 list);
1852 list_del(pos);
1853 kfree(master_image);
1854 }
1855
1856 ca91cx42_irq_exit(ca91cx42_device, pdev);
1857 err_irq:
1858 err_test:
1859 iounmap(ca91cx42_device->base);
1860 err_remap:
1861 pci_release_regions(pdev);
1862 err_resource:
1863 pci_disable_device(pdev);
1864 err_enable:
1865 kfree(ca91cx42_device);
1866 err_driver:
1867 kfree(ca91cx42_bridge);
1868 err_struct:
1869 return retval;
1870
1871 }
1872
1873 static void ca91cx42_remove(struct pci_dev *pdev)
1874 {
1875 struct list_head *pos = NULL, *n;
1876 struct vme_master_resource *master_image;
1877 struct vme_slave_resource *slave_image;
1878 struct vme_dma_resource *dma_ctrlr;
1879 struct vme_lm_resource *lm;
1880 struct ca91cx42_driver *bridge;
1881 struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1882
1883 bridge = ca91cx42_bridge->driver_priv;
1884
1885
1886 /* Turn off Ints */
1887 iowrite32(0, bridge->base + LINT_EN);
1888
1889 /* Turn off the windows */
1890 iowrite32(0x00800000, bridge->base + LSI0_CTL);
1891 iowrite32(0x00800000, bridge->base + LSI1_CTL);
1892 iowrite32(0x00800000, bridge->base + LSI2_CTL);
1893 iowrite32(0x00800000, bridge->base + LSI3_CTL);
1894 iowrite32(0x00800000, bridge->base + LSI4_CTL);
1895 iowrite32(0x00800000, bridge->base + LSI5_CTL);
1896 iowrite32(0x00800000, bridge->base + LSI6_CTL);
1897 iowrite32(0x00800000, bridge->base + LSI7_CTL);
1898 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1899 iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1900 iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1901 iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1902 iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1903 iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1904 iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1905 iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1906
1907 vme_unregister_bridge(ca91cx42_bridge);
1908
1909 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1910
1911 /* resources are stored in link list */
1912 list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
1913 lm = list_entry(pos, struct vme_lm_resource, list);
1914 list_del(pos);
1915 kfree(lm);
1916 }
1917
1918 /* resources are stored in link list */
1919 list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
1920 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1921 list_del(pos);
1922 kfree(dma_ctrlr);
1923 }
1924
1925 /* resources are stored in link list */
1926 list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
1927 slave_image = list_entry(pos, struct vme_slave_resource, list);
1928 list_del(pos);
1929 kfree(slave_image);
1930 }
1931
1932 /* resources are stored in link list */
1933 list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
1934 master_image = list_entry(pos, struct vme_master_resource,
1935 list);
1936 list_del(pos);
1937 kfree(master_image);
1938 }
1939
1940 ca91cx42_irq_exit(bridge, pdev);
1941
1942 iounmap(bridge->base);
1943
1944 pci_release_regions(pdev);
1945
1946 pci_disable_device(pdev);
1947
1948 kfree(ca91cx42_bridge);
1949 }
1950
1951 module_pci_driver(ca91cx42_driver);
1952
1953 MODULE_PARM_DESC(geoid, "Override geographical addressing");
1954 module_param(geoid, int, 0);
1955
1956 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1957 MODULE_LICENSE("GPL");
Linux with added FPC-III support