arch/mips/mti-malta/malta-int.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Carsten Langgaard, carstenl@mips.com
   7  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
   8  * Copyright (C) 2001 Ralf Baechle
   9  * Copyright (C) 2013 Imagination Technologies Ltd.
  10  *
  11  * Routines for generic manipulation of the interrupts found on the MIPS
  12  * Malta board. The interrupt controller is located in the South Bridge
  13  * a PIIX4 device with two internal 82C95 interrupt controllers.
  14  */
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqchip.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/irqchip/mips-gic.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/kernel.h>
  26 #include <linux/random.h>
  27
  28 #include <asm/traps.h>
  29 #include <asm/i8259.h>
  30 #include <asm/irq_cpu.h>
  31 #include <asm/irq_regs.h>
  32 #include <asm/mips-cm.h>
  33 #include <asm/mips-boards/malta.h>
  34 #include <asm/mips-boards/maltaint.h>
  35 #include <asm/gt64120.h>
  36 #include <asm/mips-boards/generic.h>
  37 #include <asm/mips-boards/msc01_pci.h>
  38 #include <asm/msc01_ic.h>
  39 #include <asm/setup.h>
  40 #include <asm/rtlx.h>
  41
  42 static inline int mips_pcibios_iack(void)
  43 {
  44         int irq;
  45
  46         /*
  47          * Determine highest priority pending interrupt by performing
  48          * a PCI Interrupt Acknowledge cycle.
  49          */
  50         switch (mips_revision_sconid) {
  51         case MIPS_REVISION_SCON_SOCIT:
  52         case MIPS_REVISION_SCON_ROCIT:
  53         case MIPS_REVISION_SCON_SOCITSC:
  54         case MIPS_REVISION_SCON_SOCITSCP:
  55                 MSC_READ(MSC01_PCI_IACK, irq);
  56                 irq &= 0xff;
  57                 break;
  58         case MIPS_REVISION_SCON_GT64120:
  59                 irq = GT_READ(GT_PCI0_IACK_OFS);
  60                 irq &= 0xff;
  61                 break;
  62         case MIPS_REVISION_SCON_BONITO:
  63                 /* The following will generate a PCI IACK cycle on the
  64                  * Bonito controller. It's a little bit kludgy, but it
  65                  * was the easiest way to implement it in hardware at
  66                  * the given time.
  67                  */
  68                 BONITO_PCIMAP_CFG = 0x20000;
  69
  70                 /* Flush Bonito register block */
  71                 (void) BONITO_PCIMAP_CFG;
  72                 iob();    /* sync */
  73
  74                 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
  75                 iob();    /* sync */
  76                 irq &= 0xff;
  77                 BONITO_PCIMAP_CFG = 0;
  78                 break;
  79         default:
  80                 pr_emerg("Unknown system controller.\n");
  81                 return -1;
  82         }
  83         return irq;
  84 }
  85
  86 static void corehi_irqdispatch(void)
  87 {
  88         unsigned int intedge, intsteer, pcicmd, pcibadaddr;
  89         unsigned int pcimstat, intisr, inten, intpol;
  90         unsigned int intrcause, datalo, datahi;
  91         struct pt_regs *regs = get_irq_regs();
  92
  93         pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
  94         pr_emerg("epc    : %08lx\nStatus: %08lx\n"
  95                  "Cause : %08lx\nbadVaddr : %08lx\n",
  96                  regs->cp0_epc, regs->cp0_status,
  97                  regs->cp0_cause, regs->cp0_badvaddr);
  98
  99         /* Read all the registers and then print them as there is a
 100            problem with interspersed printk's upsetting the Bonito controller.
 101            Do it for the others too.
 102         */
 103
 104         switch (mips_revision_sconid) {
 105         case MIPS_REVISION_SCON_SOCIT:
 106         case MIPS_REVISION_SCON_ROCIT:
 107         case MIPS_REVISION_SCON_SOCITSC:
 108         case MIPS_REVISION_SCON_SOCITSCP:
 109                 ll_msc_irq();
 110                 break;
 111         case MIPS_REVISION_SCON_GT64120:
 112                 intrcause = GT_READ(GT_INTRCAUSE_OFS);
 113                 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
 114                 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
 115                 pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
 116                 pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
 117                                 datahi, datalo);
 118                 break;
 119         case MIPS_REVISION_SCON_BONITO:
 120                 pcibadaddr = BONITO_PCIBADADDR;
 121                 pcimstat = BONITO_PCIMSTAT;
 122                 intisr = BONITO_INTISR;
 123                 inten = BONITO_INTEN;
 124                 intpol = BONITO_INTPOL;
 125                 intedge = BONITO_INTEDGE;
 126                 intsteer = BONITO_INTSTEER;
 127                 pcicmd = BONITO_PCICMD;
 128                 pr_emerg("BONITO_INTISR = %08x\n", intisr);
 129                 pr_emerg("BONITO_INTEN = %08x\n", inten);
 130                 pr_emerg("BONITO_INTPOL = %08x\n", intpol);
 131                 pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
 132                 pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
 133                 pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
 134                 pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
 135                 pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
 136                 break;
 137         }
 138
 139         die("CoreHi interrupt", regs);
 140 }
 141
 142 static irqreturn_t corehi_handler(int irq, void *dev_id)
 143 {
 144         corehi_irqdispatch();
 145         return IRQ_HANDLED;
 146 }
 147
 148 #ifdef CONFIG_MIPS_MT_SMP
 149
 150 #define MIPS_CPU_IPI_RESCHED_IRQ 0      /* SW int 0 for resched */
 151 #define C_RESCHED C_SW0
 152 #define MIPS_CPU_IPI_CALL_IRQ 1         /* SW int 1 for resched */
 153 #define C_CALL C_SW1
 154 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
 155
 156 static void ipi_resched_dispatch(void)
 157 {
 158         do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
 159 }
 160
 161 static void ipi_call_dispatch(void)
 162 {
 163         do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
 164 }
 165
 166 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
 167 {
 168 #ifdef CONFIG_MIPS_VPE_APSP_API_CMP
 169         if (aprp_hook)
 170                 aprp_hook();
 171 #endif
 172
 173         scheduler_ipi();
 174
 175         return IRQ_HANDLED;
 176 }
 177
 178 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
 179 {
 180         generic_smp_call_function_interrupt();
 181
 182         return IRQ_HANDLED;
 183 }
 184
 185 static struct irqaction irq_resched = {
 186         .handler        = ipi_resched_interrupt,
 187         .flags          = IRQF_PERCPU,
 188         .name           = "IPI_resched"
 189 };
 190
 191 static struct irqaction irq_call = {
 192         .handler        = ipi_call_interrupt,
 193         .flags          = IRQF_PERCPU,
 194         .name           = "IPI_call"
 195 };
 196 #endif /* CONFIG_MIPS_MT_SMP */
 197
 198 static struct irqaction corehi_irqaction = {
 199         .handler = corehi_handler,
 200         .name = "CoreHi",
 201         .flags = IRQF_NO_THREAD,
 202 };
 203
 204 static msc_irqmap_t msc_irqmap[] __initdata = {
 205         {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
 206         {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 207 };
 208 static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
 209
 210 static msc_irqmap_t msc_eicirqmap[] __initdata = {
 211         {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
 212         {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
 213         {MSC01E_INT_I8259A,             MSC01_IRQ_LEVEL, 0},
 214         {MSC01E_INT_SMI,                MSC01_IRQ_LEVEL, 0},
 215         {MSC01E_INT_COREHI,             MSC01_IRQ_LEVEL, 0},
 216         {MSC01E_INT_CORELO,             MSC01_IRQ_LEVEL, 0},
 217         {MSC01E_INT_TMR,                MSC01_IRQ_EDGE, 0},
 218         {MSC01E_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 219         {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
 220         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
 221 };
 222
 223 static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
 224
 225 void __init arch_init_ipiirq(int irq, struct irqaction *action)
 226 {
 227         setup_irq(irq, action);
 228         irq_set_handler(irq, handle_percpu_irq);
 229 }
 230
 231 void __init arch_init_irq(void)
 232 {
 233         int corehi_irq;
 234
 235         i8259_set_poll(mips_pcibios_iack);
 236         irqchip_init();
 237
 238         switch (mips_revision_sconid) {
 239         case MIPS_REVISION_SCON_SOCIT:
 240         case MIPS_REVISION_SCON_ROCIT:
 241                 if (cpu_has_veic)
 242                         init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
 243                                         MSC01E_INT_BASE, msc_eicirqmap,
 244                                         msc_nr_eicirqs);
 245                 else
 246                         init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
 247                                         MSC01C_INT_BASE, msc_irqmap,
 248                                         msc_nr_irqs);
 249                 break;
 250
 251         case MIPS_REVISION_SCON_SOCITSC:
 252         case MIPS_REVISION_SCON_SOCITSCP:
 253                 if (cpu_has_veic)
 254                         init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
 255                                         MSC01E_INT_BASE, msc_eicirqmap,
 256                                         msc_nr_eicirqs);
 257                 else
 258                         init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
 259                                         MSC01C_INT_BASE, msc_irqmap,
 260                                         msc_nr_irqs);
 261         }
 262
 263         if (gic_present) {
 264                 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
 265         } else {
 266 #if defined(CONFIG_MIPS_MT_SMP)
 267                 /* set up ipi interrupts */
 268                 if (cpu_has_veic) {
 269                         set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
 270                         set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
 271                         cpu_ipi_resched_irq = MSC01E_INT_SW0;
 272                         cpu_ipi_call_irq = MSC01E_INT_SW1;
 273                 } else {
 274                         cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
 275                                 MIPS_CPU_IPI_RESCHED_IRQ;
 276                         cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
 277                                 MIPS_CPU_IPI_CALL_IRQ;
 278                 }
 279                 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
 280                 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
 281 #endif
 282                 if (cpu_has_veic) {
 283                         set_vi_handler(MSC01E_INT_COREHI,
 284                                        corehi_irqdispatch);
 285                         corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
 286                 } else {
 287                         corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
 288                 }
 289         }
 290
 291         setup_irq(corehi_irq, &corehi_irqaction);
 292 }