drivers/clk/clk-axi-clkgen.c

   1 /*
   2  * AXI clkgen driver
   3  *
   4  * Copyright 2012-2013 Analog Devices Inc.
   5  *  Author: Lars-Peter Clausen <lars@metafoo.de>
   6  *
   7  * Licensed under the GPL-2.
   8  *
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/slab.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/module.h>
  17 #include <linux/err.h>
  18
  19 #define AXI_CLKGEN_V2_REG_RESET         0x40
  20 #define AXI_CLKGEN_V2_REG_CLKSEL        0x44
  21 #define AXI_CLKGEN_V2_REG_DRP_CNTRL     0x70
  22 #define AXI_CLKGEN_V2_REG_DRP_STATUS    0x74
  23
  24 #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
  25 #define AXI_CLKGEN_V2_RESET_ENABLE      BIT(0)
  26
  27 #define AXI_CLKGEN_V2_DRP_CNTRL_SEL     BIT(29)
  28 #define AXI_CLKGEN_V2_DRP_CNTRL_READ    BIT(28)
  29
  30 #define AXI_CLKGEN_V2_DRP_STATUS_BUSY   BIT(16)
  31
  32 #define MMCM_REG_CLKOUT0_1      0x08
  33 #define MMCM_REG_CLKOUT0_2      0x09
  34 #define MMCM_REG_CLK_FB1        0x14
  35 #define MMCM_REG_CLK_FB2        0x15
  36 #define MMCM_REG_CLK_DIV        0x16
  37 #define MMCM_REG_LOCK1          0x18
  38 #define MMCM_REG_LOCK2          0x19
  39 #define MMCM_REG_LOCK3          0x1a
  40 #define MMCM_REG_FILTER1        0x4e
  41 #define MMCM_REG_FILTER2        0x4f
  42
  43 #define MMCM_CLKOUT_NOCOUNT     BIT(6)
  44
  45 #define MMCM_CLK_DIV_NOCOUNT    BIT(12)
  46
  47 struct axi_clkgen {
  48         void __iomem *base;
  49         struct clk_hw clk_hw;
  50 };
  51
  52 static uint32_t axi_clkgen_lookup_filter(unsigned int m)
  53 {
  54         switch (m) {
  55         case 0:
  56                 return 0x01001990;
  57         case 1:
  58                 return 0x01001190;
  59         case 2:
  60                 return 0x01009890;
  61         case 3:
  62                 return 0x01001890;
  63         case 4:
  64                 return 0x01008890;
  65         case 5 ... 8:
  66                 return 0x01009090;
  67         case 9 ... 11:
  68                 return 0x01000890;
  69         case 12:
  70                 return 0x08009090;
  71         case 13 ... 22:
  72                 return 0x01001090;
  73         case 23 ... 36:
  74                 return 0x01008090;
  75         case 37 ... 46:
  76                 return 0x08001090;
  77         default:
  78                 return 0x08008090;
  79         }
  80 }
  81
  82 static const uint32_t axi_clkgen_lock_table[] = {
  83         0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
  84         0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
  85         0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
  86         0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
  87         0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
  88         0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
  89         0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
  90         0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
  91         0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
  92 };
  93
  94 static uint32_t axi_clkgen_lookup_lock(unsigned int m)
  95 {
  96         if (m < ARRAY_SIZE(axi_clkgen_lock_table))
  97                 return axi_clkgen_lock_table[m];
  98         return 0x1f1f00fa;
  99 }
 100
 101 static const unsigned int fpfd_min = 10000;
 102 static const unsigned int fpfd_max = 300000;
 103 static const unsigned int fvco_min = 600000;
 104 static const unsigned int fvco_max = 1200000;
 105
 106 static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
 107         unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
 108 {
 109         unsigned long d, d_min, d_max, _d_min, _d_max;
 110         unsigned long m, m_min, m_max;
 111         unsigned long f, dout, best_f, fvco;
 112
 113         fin /= 1000;
 114         fout /= 1000;
 115
 116         best_f = ULONG_MAX;
 117         *best_d = 0;
 118         *best_m = 0;
 119         *best_dout = 0;
 120
 121         d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
 122         d_max = min_t(unsigned long, fin / fpfd_min, 80);
 123
 124         m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min, fin) * d_min, 1);
 125         m_max = min_t(unsigned long, fvco_max * d_max / fin, 64);
 126
 127         for (m = m_min; m <= m_max; m++) {
 128                 _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max));
 129                 _d_max = min(d_max, fin * m / fvco_min);
 130
 131                 for (d = _d_min; d <= _d_max; d++) {
 132                         fvco = fin * m / d;
 133
 134                         dout = DIV_ROUND_CLOSEST(fvco, fout);
 135                         dout = clamp_t(unsigned long, dout, 1, 128);
 136                         f = fvco / dout;
 137                         if (abs(f - fout) < abs(best_f - fout)) {
 138                                 best_f = f;
 139                                 *best_d = d;
 140                                 *best_m = m;
 141                                 *best_dout = dout;
 142                                 if (best_f == fout)
 143                                         return;
 144                         }
 145                 }
 146         }
 147 }
 148
 149 static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low,
 150         unsigned int *high, unsigned int *edge, unsigned int *nocount)
 151 {
 152         if (divider == 1)
 153                 *nocount = 1;
 154         else
 155                 *nocount = 0;
 156
 157         *high = divider / 2;
 158         *edge = divider % 2;
 159         *low = divider - *high;
 160 }
 161
 162 static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
 163         unsigned int reg, unsigned int val)
 164 {
 165         writel(val, axi_clkgen->base + reg);
 166 }
 167
 168 static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
 169         unsigned int reg, unsigned int *val)
 170 {
 171         *val = readl(axi_clkgen->base + reg);
 172 }
 173
 174 static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
 175 {
 176         unsigned int timeout = 10000;
 177         unsigned int val;
 178
 179         do {
 180                 axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
 181         } while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
 182
 183         if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
 184                 return -EIO;
 185
 186         return val & 0xffff;
 187 }
 188
 189 static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
 190         unsigned int reg, unsigned int *val)
 191 {
 192         unsigned int reg_val;
 193         int ret;
 194
 195         ret = axi_clkgen_wait_non_busy(axi_clkgen);
 196         if (ret < 0)
 197                 return ret;
 198
 199         reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
 200         reg_val |= (reg << 16);
 201
 202         axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
 203
 204         ret = axi_clkgen_wait_non_busy(axi_clkgen);
 205         if (ret < 0)
 206                 return ret;
 207
 208         *val = ret;
 209
 210         return 0;
 211 }
 212
 213 static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
 214         unsigned int reg, unsigned int val, unsigned int mask)
 215 {
 216         unsigned int reg_val = 0;
 217         int ret;
 218
 219         ret = axi_clkgen_wait_non_busy(axi_clkgen);
 220         if (ret < 0)
 221                 return ret;
 222
 223         if (mask != 0xffff) {
 224                 axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
 225                 reg_val &= ~mask;
 226         }
 227
 228         reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
 229
 230         axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
 231
 232         return 0;
 233 }
 234
 235 static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
 236         bool enable)
 237 {
 238         unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
 239
 240         if (enable)
 241                 val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
 242
 243         axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
 244 }
 245
 246 static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
 247 {
 248         return container_of(clk_hw, struct axi_clkgen, clk_hw);
 249 }
 250
 251 static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
 252         unsigned long rate, unsigned long parent_rate)
 253 {
 254         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 255         unsigned int d, m, dout;
 256         unsigned int nocount;
 257         unsigned int high;
 258         unsigned int edge;
 259         unsigned int low;
 260         uint32_t filter;
 261         uint32_t lock;
 262
 263         if (parent_rate == 0 || rate == 0)
 264                 return -EINVAL;
 265
 266         axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
 267
 268         if (d == 0 || dout == 0 || m == 0)
 269                 return -EINVAL;
 270
 271         filter = axi_clkgen_lookup_filter(m - 1);
 272         lock = axi_clkgen_lookup_lock(m - 1);
 273
 274         axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount);
 275         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_1,
 276                 (high << 6) | low, 0xefff);
 277         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_2,
 278                 (edge << 7) | (nocount << 6), 0x03ff);
 279
 280         axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount);
 281         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
 282                 (edge << 13) | (nocount << 12) | (high << 6) | low, 0x3fff);
 283
 284         axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount);
 285         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB1,
 286                 (high << 6) | low, 0xefff);
 287         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB2,
 288                 (edge << 7) | (nocount << 6), 0x03ff);
 289
 290         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
 291         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
 292                 (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
 293         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
 294                 (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
 295         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
 296         axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
 297
 298         return 0;
 299 }
 300
 301 static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
 302         unsigned long *parent_rate)
 303 {
 304         unsigned int d, m, dout;
 305         unsigned long long tmp;
 306
 307         axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
 308
 309         if (d == 0 || dout == 0 || m == 0)
 310                 return -EINVAL;
 311
 312         tmp = (unsigned long long)*parent_rate * m;
 313         tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
 314
 315         return min_t(unsigned long long, tmp, LONG_MAX);
 316 }
 317
 318 static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
 319         unsigned long parent_rate)
 320 {
 321         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 322         unsigned int d, m, dout;
 323         unsigned int reg;
 324         unsigned long long tmp;
 325
 326         axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, &reg);
 327         if (reg & MMCM_CLKOUT_NOCOUNT) {
 328                 dout = 1;
 329         } else {
 330                 axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, &reg);
 331                 dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
 332         }
 333
 334         axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &reg);
 335         if (reg & MMCM_CLK_DIV_NOCOUNT)
 336                 d = 1;
 337         else
 338                 d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
 339
 340         axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, &reg);
 341         if (reg & MMCM_CLKOUT_NOCOUNT) {
 342                 m = 1;
 343         } else {
 344                 axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, &reg);
 345                 m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
 346         }
 347
 348         if (d == 0 || dout == 0)
 349                 return 0;
 350
 351         tmp = (unsigned long long)parent_rate * m;
 352         tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
 353
 354         return min_t(unsigned long long, tmp, ULONG_MAX);
 355 }
 356
 357 static int axi_clkgen_enable(struct clk_hw *clk_hw)
 358 {
 359         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 360
 361         axi_clkgen_mmcm_enable(axi_clkgen, true);
 362
 363         return 0;
 364 }
 365
 366 static void axi_clkgen_disable(struct clk_hw *clk_hw)
 367 {
 368         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 369
 370         axi_clkgen_mmcm_enable(axi_clkgen, false);
 371 }
 372
 373 static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
 374 {
 375         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 376
 377         axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
 378
 379         return 0;
 380 }
 381
 382 static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
 383 {
 384         struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
 385         unsigned int parent;
 386
 387         axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
 388
 389         return parent;
 390 }
 391
 392 static const struct clk_ops axi_clkgen_ops = {
 393         .recalc_rate = axi_clkgen_recalc_rate,
 394         .round_rate = axi_clkgen_round_rate,
 395         .set_rate = axi_clkgen_set_rate,
 396         .enable = axi_clkgen_enable,
 397         .disable = axi_clkgen_disable,
 398         .set_parent = axi_clkgen_set_parent,
 399         .get_parent = axi_clkgen_get_parent,
 400 };
 401
 402 static const struct of_device_id axi_clkgen_ids[] = {
 403         {
 404                 .compatible = "adi,axi-clkgen-2.00.a",
 405         },
 406         { },
 407 };
 408 MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
 409
 410 static int axi_clkgen_probe(struct platform_device *pdev)
 411 {
 412         const struct of_device_id *id;
 413         struct axi_clkgen *axi_clkgen;
 414         struct clk_init_data init;
 415         const char *parent_names[2];
 416         const char *clk_name;
 417         struct resource *mem;
 418         unsigned int i;
 419         int ret;
 420
 421         if (!pdev->dev.of_node)
 422                 return -ENODEV;
 423
 424         id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);
 425         if (!id)
 426                 return -ENODEV;
 427
 428         axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
 429         if (!axi_clkgen)
 430                 return -ENOMEM;
 431
 432         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 433         axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
 434         if (IS_ERR(axi_clkgen->base))
 435                 return PTR_ERR(axi_clkgen->base);
 436
 437         init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
 438         if (init.num_parents < 1 || init.num_parents > 2)
 439                 return -EINVAL;
 440
 441         for (i = 0; i < init.num_parents; i++) {
 442                 parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
 443                 if (!parent_names[i])
 444                         return -EINVAL;
 445         }
 446
 447         clk_name = pdev->dev.of_node->name;
 448         of_property_read_string(pdev->dev.of_node, "clock-output-names",
 449                 &clk_name);
 450
 451         init.name = clk_name;
 452         init.ops = &axi_clkgen_ops;
 453         init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
 454         init.parent_names = parent_names;
 455
 456         axi_clkgen_mmcm_enable(axi_clkgen, false);
 457
 458         axi_clkgen->clk_hw.init = &init;
 459         ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
 460         if (ret)
 461                 return ret;
 462
 463         return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
 464                                       &axi_clkgen->clk_hw);
 465 }
 466
 467 static int axi_clkgen_remove(struct platform_device *pdev)
 468 {
 469         of_clk_del_provider(pdev->dev.of_node);
 470
 471         return 0;
 472 }
 473
 474 static struct platform_driver axi_clkgen_driver = {
 475         .driver = {
 476                 .name = "adi-axi-clkgen",
 477                 .of_match_table = axi_clkgen_ids,
 478         },
 479         .probe = axi_clkgen_probe,
 480         .remove = axi_clkgen_remove,
 481 };
 482 module_platform_driver(axi_clkgen_driver);
 483
 484 MODULE_LICENSE("GPL v2");
 485 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 486 MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");