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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / clk / mvebu / armada-37xx-periph.c
blob499f5962c8b062d70d40d36d3aadfc23cfeb43a2
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell Armada 37xx SoC Peripheral clocks
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 *
9 * Most of the peripheral clocks can be modelled like this:
10 * _____ _______ _______
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
13 * TBG-A-S --| | | | | | |______|
14 * TBG-B-S --|_____| |_______| |_______|
15 *
16 * However some clocks may use only one or two block or and use the
17 * xtal clock as parent.
18 */
19
20 #include <linux/clk-provider.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/slab.h>
27
28 #define TBG_SEL 0x0
29 #define DIV_SEL0 0x4
30 #define DIV_SEL1 0x8
31 #define DIV_SEL2 0xC
32 #define CLK_SEL 0x10
33 #define CLK_DIS 0x14
34
35 #define ARMADA_37XX_DVFS_LOAD_1 1
36 #define LOAD_LEVEL_NR 4
37
38 #define ARMADA_37XX_NB_L0L1 0x18
39 #define ARMADA_37XX_NB_L2L3 0x1C
40 #define ARMADA_37XX_NB_TBG_DIV_OFF 13
41 #define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
42 #define ARMADA_37XX_NB_CLK_SEL_OFF 11
43 #define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
44 #define ARMADA_37XX_NB_TBG_SEL_OFF 9
45 #define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
46 #define ARMADA_37XX_NB_CONFIG_SHIFT 16
47 #define ARMADA_37XX_NB_DYN_MOD 0x24
48 #define ARMADA_37XX_NB_DFS_EN 31
49 #define ARMADA_37XX_NB_CPU_LOAD 0x30
50 #define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
51 #define ARMADA_37XX_DVFS_LOAD_0 0
52 #define ARMADA_37XX_DVFS_LOAD_1 1
53 #define ARMADA_37XX_DVFS_LOAD_2 2
54 #define ARMADA_37XX_DVFS_LOAD_3 3
55
56 struct clk_periph_driver_data {
57 struct clk_hw_onecell_data *hw_data;
58 spinlock_t lock;
59 };
60
61 struct clk_double_div {
62 struct clk_hw hw;
63 void __iomem *reg1;
64 u8 shift1;
65 void __iomem *reg2;
66 u8 shift2;
67 };
68
69 struct clk_pm_cpu {
70 struct clk_hw hw;
71 void __iomem *reg_mux;
72 u8 shift_mux;
73 u32 mask_mux;
74 void __iomem *reg_div;
75 u8 shift_div;
76 struct regmap *nb_pm_base;
77 };
78
79 #define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
80 #define to_clk_pm_cpu(_hw) container_of(_hw, struct clk_pm_cpu, hw)
81
82 struct clk_periph_data {
83 const char *name;
84 const char * const *parent_names;
85 int num_parents;
86 struct clk_hw *mux_hw;
87 struct clk_hw *rate_hw;
88 struct clk_hw *gate_hw;
89 struct clk_hw *muxrate_hw;
90 bool is_double_div;
91 };
92
93 static const struct clk_div_table clk_table6[] = {
94 { .val = 1, .div = 1, },
95 { .val = 2, .div = 2, },
96 { .val = 3, .div = 3, },
97 { .val = 4, .div = 4, },
98 { .val = 5, .div = 5, },
99 { .val = 6, .div = 6, },
100 { .val = 0, .div = 0, }, /* last entry */
101 };
102
103 static const struct clk_div_table clk_table1[] = {
104 { .val = 0, .div = 1, },
105 { .val = 1, .div = 2, },
106 { .val = 0, .div = 0, }, /* last entry */
107 };
108
109 static const struct clk_div_table clk_table2[] = {
110 { .val = 0, .div = 2, },
111 { .val = 1, .div = 4, },
112 { .val = 0, .div = 0, }, /* last entry */
113 };
114
115 static const struct clk_ops clk_double_div_ops;
116 static const struct clk_ops clk_pm_cpu_ops;
117
118 #define PERIPH_GATE(_name, _bit) \
119 struct clk_gate gate_##_name = { \
120 .reg = (void *)CLK_DIS, \
121 .bit_idx = _bit, \
122 .hw.init = &(struct clk_init_data){ \
123 .ops = &clk_gate_ops, \
124 } \
125 };
126
127 #define PERIPH_MUX(_name, _shift) \
128 struct clk_mux mux_##_name = { \
129 .reg = (void *)TBG_SEL, \
130 .shift = _shift, \
131 .mask = 3, \
132 .hw.init = &(struct clk_init_data){ \
133 .ops = &clk_mux_ro_ops, \
134 } \
135 };
136
137 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \
138 struct clk_double_div rate_##_name = { \
139 .reg1 = (void *)_reg1, \
140 .reg2 = (void *)_reg2, \
141 .shift1 = _shift1, \
142 .shift2 = _shift2, \
143 .hw.init = &(struct clk_init_data){ \
144 .ops = &clk_double_div_ops, \
145 } \
146 };
147
148 #define PERIPH_DIV(_name, _reg, _shift, _table) \
149 struct clk_divider rate_##_name = { \
150 .reg = (void *)_reg, \
151 .table = _table, \
152 .shift = _shift, \
153 .hw.init = &(struct clk_init_data){ \
154 .ops = &clk_divider_ro_ops, \
155 } \
156 };
157
158 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \
159 struct clk_pm_cpu muxrate_##_name = { \
160 .reg_mux = (void *)TBG_SEL, \
161 .mask_mux = 3, \
162 .shift_mux = _shift1, \
163 .reg_div = (void *)_reg, \
164 .shift_div = _shift2, \
165 .hw.init = &(struct clk_init_data){ \
166 .ops = &clk_pm_cpu_ops, \
167 } \
168 };
169
170 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
171 static PERIPH_GATE(_name, _bit); \
172 static PERIPH_MUX(_name, _shift); \
173 static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
174
175 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \
176 static PERIPH_GATE(_name, _bit); \
177 static PERIPH_MUX(_name, _shift); \
178 static PERIPH_DIV(_name, _reg, _shift1, _table);
179
180 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \
181 static PERIPH_GATE(_name, _bit); \
182 static PERIPH_DIV(_name, _reg, _shift, _table);
183
184 #define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
185 static PERIPH_MUX(_name, _shift); \
186 static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
187
188 #define REF_CLK_FULL(_name) \
189 { .name = #_name, \
190 .parent_names = (const char *[]){ "TBG-A-P", \
191 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
192 .num_parents = 4, \
193 .mux_hw = &mux_##_name.hw, \
194 .gate_hw = &gate_##_name.hw, \
195 .rate_hw = &rate_##_name.hw, \
196 }
197
198 #define REF_CLK_FULL_DD(_name) \
199 { .name = #_name, \
200 .parent_names = (const char *[]){ "TBG-A-P", \
201 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
202 .num_parents = 4, \
203 .mux_hw = &mux_##_name.hw, \
204 .gate_hw = &gate_##_name.hw, \
205 .rate_hw = &rate_##_name.hw, \
206 .is_double_div = true, \
207 }
208
209 #define REF_CLK_GATE(_name, _parent_name) \
210 { .name = #_name, \
211 .parent_names = (const char *[]){ _parent_name}, \
212 .num_parents = 1, \
213 .gate_hw = &gate_##_name.hw, \
214 }
215
216 #define REF_CLK_GATE_DIV(_name, _parent_name) \
217 { .name = #_name, \
218 .parent_names = (const char *[]){ _parent_name}, \
219 .num_parents = 1, \
220 .gate_hw = &gate_##_name.hw, \
221 .rate_hw = &rate_##_name.hw, \
222 }
223
224 #define REF_CLK_PM_CPU(_name) \
225 { .name = #_name, \
226 .parent_names = (const char *[]){ "TBG-A-P", \
227 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
228 .num_parents = 4, \
229 .muxrate_hw = &muxrate_##_name.hw, \
230 }
231
232 #define REF_CLK_MUX_DD(_name) \
233 { .name = #_name, \
234 .parent_names = (const char *[]){ "TBG-A-P", \
235 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
236 .num_parents = 4, \
237 .mux_hw = &mux_##_name.hw, \
238 .rate_hw = &rate_##_name.hw, \
239 .is_double_div = true, \
240 }
241
242 /* NB periph clocks */
243 PERIPH_CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13);
244 PERIPH_CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7);
245 PERIPH_CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0);
246 PERIPH_CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6);
247 PERIPH_CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12);
248 PERIPH_CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, clk_table6);
249 static PERIPH_GATE(avs, 11);
250 PERIPH_CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0);
251 PERIPH_CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24);
252 static PERIPH_GATE(i2c_2, 16);
253 static PERIPH_GATE(i2c_1, 17);
254 PERIPH_CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, clk_table2);
255 PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
256 PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
257 PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
258 PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
259 static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28);
260
261 static struct clk_periph_data data_nb[] = {
262 REF_CLK_FULL_DD(mmc),
263 REF_CLK_FULL_DD(sata_host),
264 REF_CLK_FULL_DD(sec_at),
265 REF_CLK_FULL_DD(sec_dap),
266 REF_CLK_FULL_DD(tscem),
267 REF_CLK_FULL(tscem_tmx),
268 REF_CLK_GATE(avs, "xtal"),
269 REF_CLK_FULL_DD(sqf),
270 REF_CLK_FULL_DD(pwm),
271 REF_CLK_GATE(i2c_2, "xtal"),
272 REF_CLK_GATE(i2c_1, "xtal"),
273 REF_CLK_GATE_DIV(ddr_phy, "TBG-A-S"),
274 REF_CLK_FULL_DD(ddr_fclk),
275 REF_CLK_FULL(trace),
276 REF_CLK_FULL(counter),
277 REF_CLK_FULL_DD(eip97),
278 REF_CLK_PM_CPU(cpu),
279 { },
280 };
281
282 /* SB periph clocks */
283 PERIPH_CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9);
284 PERIPH_CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21);
285 PERIPH_CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9);
286 static PERIPH_GATE(gbe1_50, 0);
287 static PERIPH_GATE(gbe0_50, 1);
288 static PERIPH_GATE(gbe1_125, 2);
289 static PERIPH_GATE(gbe0_125, 3);
290 PERIPH_CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, clk_table1);
291 PERIPH_CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, clk_table1);
292 PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1);
293 PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
294 PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
295 PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
296
297 static struct clk_periph_data data_sb[] = {
298 REF_CLK_MUX_DD(gbe_50),
299 REF_CLK_MUX_DD(gbe_core),
300 REF_CLK_MUX_DD(gbe_125),
301 REF_CLK_GATE(gbe1_50, "gbe_50"),
302 REF_CLK_GATE(gbe0_50, "gbe_50"),
303 REF_CLK_GATE(gbe1_125, "gbe_125"),
304 REF_CLK_GATE(gbe0_125, "gbe_125"),
305 REF_CLK_GATE_DIV(gbe1_core, "gbe_core"),
306 REF_CLK_GATE_DIV(gbe0_core, "gbe_core"),
307 REF_CLK_GATE_DIV(gbe_bm, "gbe_core"),
308 REF_CLK_FULL_DD(sdio),
309 REF_CLK_FULL_DD(usb32_usb2_sys),
310 REF_CLK_FULL_DD(usb32_ss_sys),
311 { },
312 };
313
314 static unsigned int get_div(void __iomem *reg, int shift)
315 {
316 u32 val;
317
318 val = (readl(reg) >> shift) & 0x7;
319 if (val > 6)
320 return 0;
321 return val;
322 }
323
324 static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
325 unsigned long parent_rate)
326 {
327 struct clk_double_div *double_div = to_clk_double_div(hw);
328 unsigned int div;
329
330 div = get_div(double_div->reg1, double_div->shift1);
331 div *= get_div(double_div->reg2, double_div->shift2);
332
333 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
334 }
335
336 static const struct clk_ops clk_double_div_ops = {
337 .recalc_rate = clk_double_div_recalc_rate,
338 };
339
340 static void armada_3700_pm_dvfs_update_regs(unsigned int load_level,
341 unsigned int *reg,
342 unsigned int *offset)
343 {
344 if (load_level <= ARMADA_37XX_DVFS_LOAD_1)
345 *reg = ARMADA_37XX_NB_L0L1;
346 else
347 *reg = ARMADA_37XX_NB_L2L3;
348
349 if (load_level == ARMADA_37XX_DVFS_LOAD_0 ||
350 load_level == ARMADA_37XX_DVFS_LOAD_2)
351 *offset += ARMADA_37XX_NB_CONFIG_SHIFT;
352 }
353
354 static bool armada_3700_pm_dvfs_is_enabled(struct regmap *base)
355 {
356 unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD;
357
358 if (IS_ERR(base))
359 return false;
360
361 regmap_read(base, reg, &val);
362
363 return !!(val & BIT(ARMADA_37XX_NB_DFS_EN));
364 }
365
366 static unsigned int armada_3700_pm_dvfs_get_cpu_div(struct regmap *base)
367 {
368 unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
369 unsigned int offset = ARMADA_37XX_NB_TBG_DIV_OFF;
370 unsigned int load_level, div;
371
372 /*
373 * This function is always called after the function
374 * armada_3700_pm_dvfs_is_enabled, so no need to check again
375 * if the base is valid.
376 */
377 regmap_read(base, reg, &load_level);
378
379 /*
380 * The register and the offset inside this register accessed to
381 * read the current divider depend on the load level
382 */
383 load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
384 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
385
386 regmap_read(base, reg, &div);
387
388 return (div >> offset) & ARMADA_37XX_NB_TBG_DIV_MASK;
389 }
390
391 static unsigned int armada_3700_pm_dvfs_get_cpu_parent(struct regmap *base)
392 {
393 unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
394 unsigned int offset = ARMADA_37XX_NB_TBG_SEL_OFF;
395 unsigned int load_level, sel;
396
397 /*
398 * This function is always called after the function
399 * armada_3700_pm_dvfs_is_enabled, so no need to check again
400 * if the base is valid
401 */
402 regmap_read(base, reg, &load_level);
403
404 /*
405 * The register and the offset inside this register accessed to
406 * read the current divider depend on the load level
407 */
408 load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
409 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
410
411 regmap_read(base, reg, &sel);
412
413 return (sel >> offset) & ARMADA_37XX_NB_TBG_SEL_MASK;
414 }
415
416 static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
417 {
418 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
419 u32 val;
420
421 if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) {
422 val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base);
423 } else {
424 val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux;
425 val &= pm_cpu->mask_mux;
426 }
427
428 return val;
429 }
430
431 static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
432 {
433 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
434 struct regmap *base = pm_cpu->nb_pm_base;
435 int load_level;
436
437 /*
438 * We set the clock parent only if the DVFS is available but
439 * not enabled.
440 */
441 if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base))
442 return -EINVAL;
443
444 /* Set the parent clock for all the load level */
445 for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
446 unsigned int reg, mask, val,
447 offset = ARMADA_37XX_NB_TBG_SEL_OFF;
448
449 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
450
451 val = index << offset;
452 mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
453 regmap_update_bits(base, reg, mask, val);
454 }
455 return 0;
456 }
457
458 static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
459 unsigned long parent_rate)
460 {
461 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
462 unsigned int div;
463
464 if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base))
465 div = armada_3700_pm_dvfs_get_cpu_div(pm_cpu->nb_pm_base);
466 else
467 div = get_div(pm_cpu->reg_div, pm_cpu->shift_div);
468 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
469 }
470
471 static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
472 unsigned long *parent_rate)
473 {
474 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
475 struct regmap *base = pm_cpu->nb_pm_base;
476 unsigned int div = *parent_rate / rate;
477 unsigned int load_level;
478 /* only available when DVFS is enabled */
479 if (!armada_3700_pm_dvfs_is_enabled(base))
480 return -EINVAL;
481
482 for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
483 unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF;
484
485 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
486
487 regmap_read(base, reg, &val);
488
489 val >>= offset;
490 val &= ARMADA_37XX_NB_TBG_DIV_MASK;
491 if (val == div)
492 /*
493 * We found a load level matching the target
494 * divider, switch to this load level and
495 * return.
496 */
497 return *parent_rate / div;
498 }
499
500 /* We didn't find any valid divider */
501 return -EINVAL;
502 }
503
504 /*
505 * Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
506 * respectively) to L0 frequency (1.2 Ghz) requires a significant
507 * amount of time to let VDD stabilize to the appropriate
508 * voltage. This amount of time is large enough that it cannot be
509 * covered by the hardware countdown register. Due to this, the CPU
510 * might start operating at L0 before the voltage is stabilized,
511 * leading to CPU stalls.
512 *
513 * To work around this problem, we prevent switching directly from the
514 * L2/L3 frequencies to the L0 frequency, and instead switch to the L1
515 * frequency in-between. The sequence therefore becomes:
516 * 1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
517 * 2. Sleep 20ms for stabling VDD voltage
518 * 3. Then switch from L1(600MHZ) to L0(1200Mhz).
519 */
520 static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base)
521 {
522 unsigned int cur_level;
523
524 if (rate != 1200 * 1000 * 1000)
525 return;
526
527 regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level);
528 cur_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
529 if (cur_level <= ARMADA_37XX_DVFS_LOAD_1)
530 return;
531
532 regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD,
533 ARMADA_37XX_NB_CPU_LOAD_MASK,
534 ARMADA_37XX_DVFS_LOAD_1);
535 msleep(20);
536 }
537
538 static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
539 unsigned long parent_rate)
540 {
541 struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
542 struct regmap *base = pm_cpu->nb_pm_base;
543 unsigned int div = parent_rate / rate;
544 unsigned int load_level;
545
546 /* only available when DVFS is enabled */
547 if (!armada_3700_pm_dvfs_is_enabled(base))
548 return -EINVAL;
549
550 for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
551 unsigned int reg, mask, val,
552 offset = ARMADA_37XX_NB_TBG_DIV_OFF;
553
554 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
555
556 regmap_read(base, reg, &val);
557 val >>= offset;
558 val &= ARMADA_37XX_NB_TBG_DIV_MASK;
559
560 if (val == div) {
561 /*
562 * We found a load level matching the target
563 * divider, switch to this load level and
564 * return.
565 */
566 reg = ARMADA_37XX_NB_CPU_LOAD;
567 mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
568
569 clk_pm_cpu_set_rate_wa(rate, base);
570
571 regmap_update_bits(base, reg, mask, load_level);
572
573 return rate;
574 }
575 }
576
577 /* We didn't find any valid divider */
578 return -EINVAL;
579 }
580
581 static const struct clk_ops clk_pm_cpu_ops = {
582 .get_parent = clk_pm_cpu_get_parent,
583 .set_parent = clk_pm_cpu_set_parent,
584 .round_rate = clk_pm_cpu_round_rate,
585 .set_rate = clk_pm_cpu_set_rate,
586 .recalc_rate = clk_pm_cpu_recalc_rate,
587 };
588
589 static const struct of_device_id armada_3700_periph_clock_of_match[] = {
590 { .compatible = "marvell,armada-3700-periph-clock-nb",
591 .data = data_nb, },
592 { .compatible = "marvell,armada-3700-periph-clock-sb",
593 .data = data_sb, },
594 { }
595 };
596
597 static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
598 void __iomem *reg, spinlock_t *lock,
599 struct device *dev, struct clk_hw **hw)
600 {
601 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
602 *rate_ops = NULL;
603 struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *rate_hw = NULL;
604
605 if (data->mux_hw) {
606 struct clk_mux *mux;
607
608 mux_hw = data->mux_hw;
609 mux = to_clk_mux(mux_hw);
610 mux->lock = lock;
611 mux_ops = mux_hw->init->ops;
612 mux->reg = reg + (u64)mux->reg;
613 }
614
615 if (data->gate_hw) {
616 struct clk_gate *gate;
617
618 gate_hw = data->gate_hw;
619 gate = to_clk_gate(gate_hw);
620 gate->lock = lock;
621 gate_ops = gate_hw->init->ops;
622 gate->reg = reg + (u64)gate->reg;
623 gate->flags = CLK_GATE_SET_TO_DISABLE;
624 }
625
626 if (data->rate_hw) {
627 rate_hw = data->rate_hw;
628 rate_ops = rate_hw->init->ops;
629 if (data->is_double_div) {
630 struct clk_double_div *rate;
631
632 rate = to_clk_double_div(rate_hw);
633 rate->reg1 = reg + (u64)rate->reg1;
634 rate->reg2 = reg + (u64)rate->reg2;
635 } else {
636 struct clk_divider *rate = to_clk_divider(rate_hw);
637 const struct clk_div_table *clkt;
638 int table_size = 0;
639
640 rate->reg = reg + (u64)rate->reg;
641 for (clkt = rate->table; clkt->div; clkt++)
642 table_size++;
643 rate->width = order_base_2(table_size);
644 rate->lock = lock;
645 }
646 }
647
648 if (data->muxrate_hw) {
649 struct clk_pm_cpu *pmcpu_clk;
650 struct clk_hw *muxrate_hw = data->muxrate_hw;
651 struct regmap *map;
652
653 pmcpu_clk = to_clk_pm_cpu(muxrate_hw);
654 pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux;
655 pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div;
656
657 mux_hw = muxrate_hw;
658 rate_hw = muxrate_hw;
659 mux_ops = muxrate_hw->init->ops;
660 rate_ops = muxrate_hw->init->ops;
661
662 map = syscon_regmap_lookup_by_compatible(
663 "marvell,armada-3700-nb-pm");
664 pmcpu_clk->nb_pm_base = map;
665 }
666
667 *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
668 data->num_parents, mux_hw,
669 mux_ops, rate_hw, rate_ops,
670 gate_hw, gate_ops, CLK_IGNORE_UNUSED);
671
672 return PTR_ERR_OR_ZERO(*hw);
673 }
674
675 static int armada_3700_periph_clock_probe(struct platform_device *pdev)
676 {
677 struct clk_periph_driver_data *driver_data;
678 struct device_node *np = pdev->dev.of_node;
679 const struct clk_periph_data *data;
680 struct device *dev = &pdev->dev;
681 int num_periph = 0, i, ret;
682 struct resource *res;
683 void __iomem *reg;
684
685 data = of_device_get_match_data(dev);
686 if (!data)
687 return -ENODEV;
688
689 while (data[num_periph].name)
690 num_periph++;
691
692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
693 reg = devm_ioremap_resource(dev, res);
694 if (IS_ERR(reg))
695 return PTR_ERR(reg);
696
697 driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
698 if (!driver_data)
699 return -ENOMEM;
700
701 driver_data->hw_data = devm_kzalloc(dev,
702 struct_size(driver_data->hw_data,
703 hws, num_periph),
704 GFP_KERNEL);
705 if (!driver_data->hw_data)
706 return -ENOMEM;
707 driver_data->hw_data->num = num_periph;
708
709 spin_lock_init(&driver_data->lock);
710
711 for (i = 0; i < num_periph; i++) {
712 struct clk_hw **hw = &driver_data->hw_data->hws[i];
713
714 if (armada_3700_add_composite_clk(&data[i], reg,
715 &driver_data->lock, dev, hw))
716 dev_err(dev, "Can't register periph clock %s\n",
717 data[i].name);
718 }
719
720 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
721 driver_data->hw_data);
722 if (ret) {
723 for (i = 0; i < num_periph; i++)
724 clk_hw_unregister(driver_data->hw_data->hws[i]);
725 return ret;
726 }
727
728 platform_set_drvdata(pdev, driver_data);
729 return 0;
730 }
731
732 static int armada_3700_periph_clock_remove(struct platform_device *pdev)
733 {
734 struct clk_periph_driver_data *data = platform_get_drvdata(pdev);
735 struct clk_hw_onecell_data *hw_data = data->hw_data;
736 int i;
737
738 of_clk_del_provider(pdev->dev.of_node);
739
740 for (i = 0; i < hw_data->num; i++)
741 clk_hw_unregister(hw_data->hws[i]);
742
743 return 0;
744 }
745
746 static struct platform_driver armada_3700_periph_clock_driver = {
747 .probe = armada_3700_periph_clock_probe,
748 .remove = armada_3700_periph_clock_remove,
749 .driver = {
750 .name = "marvell-armada-3700-periph-clock",
751 .of_match_table = armada_3700_periph_clock_of_match,
752 },
753 };
754
755 builtin_platform_driver(armada_3700_periph_clock_driver);
Linux with added FPC-III support