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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / clk / renesas / r8a7745-cpg-mssr.c
blob4b0a9243b7481176ca2c8701451f03421bd3de59
1 /*
2 * r8a7745 Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation; of the License.
9 */
10
11 #include <linux/device.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/soc/renesas/rcar-rst.h>
15
16 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
17
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
20
21 enum clk_ids {
22 /* Core Clock Outputs exported to DT */
23 LAST_DT_CORE_CLK = R8A7745_CLK_OSC,
24
25 /* External Input Clocks */
26 CLK_EXTAL,
27 CLK_USB_EXTAL,
28
29 /* Internal Core Clocks */
30 CLK_MAIN,
31 CLK_PLL0,
32 CLK_PLL1,
33 CLK_PLL3,
34 CLK_PLL1_DIV2,
35
36 /* Module Clocks */
37 MOD_CLK_BASE
38 };
39
40 static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
41 /* External Clock Inputs */
42 DEF_INPUT("extal", CLK_EXTAL),
43 DEF_INPUT("usb_extal", CLK_USB_EXTAL),
44
45 /* Internal Core Clocks */
46 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
47 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
48 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
49 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
50
51 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
52
53 /* Core Clock Outputs */
54 DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
55 DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
56 DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
57 DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
58
59 DEF_FIXED("z2", R8A7745_CLK_Z2, CLK_PLL0, 1, 1),
60 DEF_FIXED("zg", R8A7745_CLK_ZG, CLK_PLL1, 6, 1),
61 DEF_FIXED("zx", R8A7745_CLK_ZX, CLK_PLL1, 3, 1),
62 DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1),
63 DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1),
64 DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1),
65 DEF_FIXED("lb", R8A7745_CLK_LB, CLK_PLL1, 24, 1),
66 DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1),
67 DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1),
68 DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1),
69 DEF_FIXED("m2", R8A7745_CLK_M2, CLK_PLL1, 8, 1),
70 DEF_FIXED("zb3", R8A7745_CLK_ZB3, CLK_PLL3, 4, 1),
71 DEF_FIXED("zb3d2", R8A7745_CLK_ZB3D2, CLK_PLL3, 8, 1),
72 DEF_FIXED("ddr", R8A7745_CLK_DDR, CLK_PLL3, 8, 1),
73 DEF_FIXED("mp", R8A7745_CLK_MP, CLK_PLL1_DIV2, 15, 1),
74 DEF_FIXED("cpex", R8A7745_CLK_CPEX, CLK_EXTAL, 2, 1),
75 DEF_FIXED("r", R8A7745_CLK_R, CLK_PLL1, 49152, 1),
76 DEF_FIXED("osc", R8A7745_CLK_OSC, CLK_PLL1, 12288, 1),
77
78 DEF_DIV6P1("sd2", R8A7745_CLK_SD2, CLK_PLL1_DIV2, 0x078),
79 DEF_DIV6P1("sd3", R8A7745_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
80 DEF_DIV6P1("mmc0", R8A7745_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
81 };
82
83 static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
84 DEF_MOD("msiof0", 0, R8A7745_CLK_MP),
85 DEF_MOD("vcp0", 101, R8A7745_CLK_ZS),
86 DEF_MOD("vpc0", 103, R8A7745_CLK_ZS),
87 DEF_MOD("tmu1", 111, R8A7745_CLK_P),
88 DEF_MOD("3dg", 112, R8A7745_CLK_ZG),
89 DEF_MOD("2d-dmac", 115, R8A7745_CLK_ZS),
90 DEF_MOD("fdp1-0", 119, R8A7745_CLK_ZS),
91 DEF_MOD("tmu3", 121, R8A7745_CLK_P),
92 DEF_MOD("tmu2", 122, R8A7745_CLK_P),
93 DEF_MOD("cmt0", 124, R8A7745_CLK_R),
94 DEF_MOD("tmu0", 125, R8A7745_CLK_CP),
95 DEF_MOD("vsp1du0", 128, R8A7745_CLK_ZS),
96 DEF_MOD("vsp1-sy", 131, R8A7745_CLK_ZS),
97 DEF_MOD("scifa2", 202, R8A7745_CLK_MP),
98 DEF_MOD("scifa1", 203, R8A7745_CLK_MP),
99 DEF_MOD("scifa0", 204, R8A7745_CLK_MP),
100 DEF_MOD("msiof2", 205, R8A7745_CLK_MP),
101 DEF_MOD("scifb0", 206, R8A7745_CLK_MP),
102 DEF_MOD("scifb1", 207, R8A7745_CLK_MP),
103 DEF_MOD("msiof1", 208, R8A7745_CLK_MP),
104 DEF_MOD("scifb2", 216, R8A7745_CLK_MP),
105 DEF_MOD("sys-dmac1", 218, R8A7745_CLK_ZS),
106 DEF_MOD("sys-dmac0", 219, R8A7745_CLK_ZS),
107 DEF_MOD("tpu0", 304, R8A7745_CLK_CP),
108 DEF_MOD("sdhi3", 311, R8A7745_CLK_SD3),
109 DEF_MOD("sdhi2", 312, R8A7745_CLK_SD2),
110 DEF_MOD("sdhi0", 314, R8A7745_CLK_SD0),
111 DEF_MOD("mmcif0", 315, R8A7745_CLK_MMC0),
112 DEF_MOD("iic0", 318, R8A7745_CLK_HP),
113 DEF_MOD("iic1", 323, R8A7745_CLK_HP),
114 DEF_MOD("cmt1", 329, R8A7745_CLK_R),
115 DEF_MOD("usbhs-dmac0", 330, R8A7745_CLK_HP),
116 DEF_MOD("usbhs-dmac1", 331, R8A7745_CLK_HP),
117 DEF_MOD("rwdt", 402, R8A7745_CLK_R),
118 DEF_MOD("irqc", 407, R8A7745_CLK_CP),
119 DEF_MOD("intc-sys", 408, R8A7745_CLK_ZS),
120 DEF_MOD("audio-dmac0", 502, R8A7745_CLK_HP),
121 DEF_MOD("pwm", 523, R8A7745_CLK_P),
122 DEF_MOD("usb-ehci", 703, R8A7745_CLK_MP),
123 DEF_MOD("usbhs", 704, R8A7745_CLK_HP),
124 DEF_MOD("hscif2", 713, R8A7745_CLK_ZS),
125 DEF_MOD("scif5", 714, R8A7745_CLK_P),
126 DEF_MOD("scif4", 715, R8A7745_CLK_P),
127 DEF_MOD("hscif1", 716, R8A7745_CLK_ZS),
128 DEF_MOD("hscif0", 717, R8A7745_CLK_ZS),
129 DEF_MOD("scif3", 718, R8A7745_CLK_P),
130 DEF_MOD("scif2", 719, R8A7745_CLK_P),
131 DEF_MOD("scif1", 720, R8A7745_CLK_P),
132 DEF_MOD("scif0", 721, R8A7745_CLK_P),
133 DEF_MOD("du1", 723, R8A7745_CLK_ZX),
134 DEF_MOD("du0", 724, R8A7745_CLK_ZX),
135 DEF_MOD("ipmmu-sgx", 800, R8A7745_CLK_ZX),
136 DEF_MOD("vin1", 810, R8A7745_CLK_ZG),
137 DEF_MOD("vin0", 811, R8A7745_CLK_ZG),
138 DEF_MOD("etheravb", 812, R8A7745_CLK_HP),
139 DEF_MOD("ether", 813, R8A7745_CLK_P),
140 DEF_MOD("gpio6", 905, R8A7745_CLK_CP),
141 DEF_MOD("gpio5", 907, R8A7745_CLK_CP),
142 DEF_MOD("gpio4", 908, R8A7745_CLK_CP),
143 DEF_MOD("gpio3", 909, R8A7745_CLK_CP),
144 DEF_MOD("gpio2", 910, R8A7745_CLK_CP),
145 DEF_MOD("gpio1", 911, R8A7745_CLK_CP),
146 DEF_MOD("gpio0", 912, R8A7745_CLK_CP),
147 DEF_MOD("can1", 915, R8A7745_CLK_P),
148 DEF_MOD("can0", 916, R8A7745_CLK_P),
149 DEF_MOD("qspi_mod", 917, R8A7745_CLK_QSPI),
150 DEF_MOD("i2c5", 925, R8A7745_CLK_HP),
151 DEF_MOD("i2c4", 927, R8A7745_CLK_HP),
152 DEF_MOD("i2c3", 928, R8A7745_CLK_HP),
153 DEF_MOD("i2c2", 929, R8A7745_CLK_HP),
154 DEF_MOD("i2c1", 930, R8A7745_CLK_HP),
155 DEF_MOD("i2c0", 931, R8A7745_CLK_HP),
156 DEF_MOD("ssi-all", 1005, R8A7745_CLK_P),
157 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
158 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
159 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
160 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
161 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
162 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
163 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
164 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
165 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
166 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
167 DEF_MOD("scu-all", 1017, R8A7745_CLK_P),
168 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
169 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
170 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
171 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
172 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
173 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
174 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
175 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
176 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
177 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
178 DEF_MOD("scifa3", 1106, R8A7745_CLK_MP),
179 DEF_MOD("scifa4", 1107, R8A7745_CLK_MP),
180 DEF_MOD("scifa5", 1108, R8A7745_CLK_MP),
181 };
182
183 static const unsigned int r8a7745_crit_mod_clks[] __initconst = {
184 MOD_CLK_ID(402), /* RWDT */
185 MOD_CLK_ID(408), /* INTC-SYS (GIC) */
186 };
187
188 /*
189 * CPG Clock Data
190 */
191
192 /*
193 * MD EXTAL PLL0 PLL1 PLL3
194 * 14 13 19 (MHz) *1 *2
195 *---------------------------------------------------
196 * 0 0 1 15 x200/3 x208/2 x88
197 * 0 1 1 20 x150/3 x156/2 x66
198 * 1 0 1 26 / 2 x230/3 x240/2 x102
199 * 1 1 1 30 / 2 x200/3 x208/2 x88
200 *
201 * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
202 * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
203 */
204 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
205 (((md) & BIT(13)) >> 13))
206
207 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
208 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
209 { 1, 208, 88, 200 },
210 { 1, 156, 66, 150 },
211 { 2, 240, 102, 230 },
212 { 2, 208, 88, 200 },
213 };
214
215 static int __init r8a7745_cpg_mssr_init(struct device *dev)
216 {
217 const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
218 u32 cpg_mode;
219 int error;
220
221 error = rcar_rst_read_mode_pins(&cpg_mode);
222 if (error)
223 return error;
224
225 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
226
227 return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
228 }
229
230 const struct cpg_mssr_info r8a7745_cpg_mssr_info __initconst = {
231 /* Core Clocks */
232 .core_clks = r8a7745_core_clks,
233 .num_core_clks = ARRAY_SIZE(r8a7745_core_clks),
234 .last_dt_core_clk = LAST_DT_CORE_CLK,
235 .num_total_core_clks = MOD_CLK_BASE,
236
237 /* Module Clocks */
238 .mod_clks = r8a7745_mod_clks,
239 .num_mod_clks = ARRAY_SIZE(r8a7745_mod_clks),
240 .num_hw_mod_clks = 12 * 32,
241
242 /* Critical Module Clocks */
243 .crit_mod_clks = r8a7745_crit_mod_clks,
244 .num_crit_mod_clks = ARRAY_SIZE(r8a7745_crit_mod_clks),
245
246 /* Callbacks */
247 .init = r8a7745_cpg_mssr_init,
248 .cpg_clk_register = rcar_gen2_cpg_clk_register,
249 };
Linux with added FPC-III support