drivers/crypto/chelsio/chcr_core.h

   1 /*
   2  * This file is part of the Chelsio T6 Crypto driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  *
  34  */
  35
  36 #ifndef __CHCR_CORE_H__
  37 #define __CHCR_CORE_H__
  38
  39 #include <crypto/algapi.h>
  40 #include "t4_hw.h"
  41 #include "cxgb4.h"
  42 #include "t4_msg.h"
  43 #include "cxgb4_uld.h"
  44
  45 #define DRV_MODULE_NAME "chcr"
  46 #define DRV_VERSION "1.0.0.0"
  47
  48 #define MAX_PENDING_REQ_TO_HW 20
  49 #define CHCR_TEST_RESPONSE_TIMEOUT 1000
  50
  51 #define PAD_ERROR_BIT           1
  52 #define CHK_PAD_ERR_BIT(x)      (((x) >> PAD_ERROR_BIT) & 1)
  53
  54 #define MAC_ERROR_BIT           0
  55 #define CHK_MAC_ERR_BIT(x)      (((x) >> MAC_ERROR_BIT) & 1)
  56 #define MAX_SALT                4
  57 #define CIP_WR_MIN_LEN (sizeof(struct chcr_wr) + \
  58                     sizeof(struct cpl_rx_phys_dsgl) + \
  59                     sizeof(struct ulptx_sgl) + 16) //IV
  60
  61 #define HASH_WR_MIN_LEN (sizeof(struct chcr_wr) + \
  62                         DUMMY_BYTES + \
  63                     sizeof(struct ulptx_sgl))
  64
  65 #define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev)
  66
  67 struct uld_ctx;
  68
  69 struct _key_ctx {
  70         __be32 ctx_hdr;
  71         u8 salt[MAX_SALT];
  72         __be64 iv_to_auth;
  73         unsigned char key[0];
  74 };
  75
  76 #define KEYCTX_TX_WR_IV_S  55
  77 #define KEYCTX_TX_WR_IV_M  0x1ffULL
  78 #define KEYCTX_TX_WR_IV_V(x) ((x) << KEYCTX_TX_WR_IV_S)
  79 #define KEYCTX_TX_WR_IV_G(x) \
  80         (((x) >> KEYCTX_TX_WR_IV_S) & KEYCTX_TX_WR_IV_M)
  81
  82 #define KEYCTX_TX_WR_AAD_S 47
  83 #define KEYCTX_TX_WR_AAD_M 0xffULL
  84 #define KEYCTX_TX_WR_AAD_V(x) ((x) << KEYCTX_TX_WR_AAD_S)
  85 #define KEYCTX_TX_WR_AAD_G(x) (((x) >> KEYCTX_TX_WR_AAD_S) & \
  86                                 KEYCTX_TX_WR_AAD_M)
  87
  88 #define KEYCTX_TX_WR_AADST_S 39
  89 #define KEYCTX_TX_WR_AADST_M 0xffULL
  90 #define KEYCTX_TX_WR_AADST_V(x) ((x) << KEYCTX_TX_WR_AADST_S)
  91 #define KEYCTX_TX_WR_AADST_G(x) \
  92         (((x) >> KEYCTX_TX_WR_AADST_S) & KEYCTX_TX_WR_AADST_M)
  93
  94 #define KEYCTX_TX_WR_CIPHER_S 30
  95 #define KEYCTX_TX_WR_CIPHER_M 0x1ffULL
  96 #define KEYCTX_TX_WR_CIPHER_V(x) ((x) << KEYCTX_TX_WR_CIPHER_S)
  97 #define KEYCTX_TX_WR_CIPHER_G(x) \
  98         (((x) >> KEYCTX_TX_WR_CIPHER_S) & KEYCTX_TX_WR_CIPHER_M)
  99
 100 #define KEYCTX_TX_WR_CIPHERST_S 23
 101 #define KEYCTX_TX_WR_CIPHERST_M 0x7f
 102 #define KEYCTX_TX_WR_CIPHERST_V(x) ((x) << KEYCTX_TX_WR_CIPHERST_S)
 103 #define KEYCTX_TX_WR_CIPHERST_G(x) \
 104         (((x) >> KEYCTX_TX_WR_CIPHERST_S) & KEYCTX_TX_WR_CIPHERST_M)
 105
 106 #define KEYCTX_TX_WR_AUTH_S 14
 107 #define KEYCTX_TX_WR_AUTH_M 0x1ff
 108 #define KEYCTX_TX_WR_AUTH_V(x) ((x) << KEYCTX_TX_WR_AUTH_S)
 109 #define KEYCTX_TX_WR_AUTH_G(x) \
 110         (((x) >> KEYCTX_TX_WR_AUTH_S) & KEYCTX_TX_WR_AUTH_M)
 111
 112 #define KEYCTX_TX_WR_AUTHST_S 7
 113 #define KEYCTX_TX_WR_AUTHST_M 0x7f
 114 #define KEYCTX_TX_WR_AUTHST_V(x) ((x) << KEYCTX_TX_WR_AUTHST_S)
 115 #define KEYCTX_TX_WR_AUTHST_G(x) \
 116         (((x) >> KEYCTX_TX_WR_AUTHST_S) & KEYCTX_TX_WR_AUTHST_M)
 117
 118 #define KEYCTX_TX_WR_AUTHIN_S 0
 119 #define KEYCTX_TX_WR_AUTHIN_M 0x7f
 120 #define KEYCTX_TX_WR_AUTHIN_V(x) ((x) << KEYCTX_TX_WR_AUTHIN_S)
 121 #define KEYCTX_TX_WR_AUTHIN_G(x) \
 122         (((x) >> KEYCTX_TX_WR_AUTHIN_S) & KEYCTX_TX_WR_AUTHIN_M)
 123
 124 struct chcr_wr {
 125         struct fw_crypto_lookaside_wr wreq;
 126         struct ulp_txpkt ulptx;
 127         struct ulptx_idata sc_imm;
 128         struct cpl_tx_sec_pdu sec_cpl;
 129         struct _key_ctx key_ctx;
 130 };
 131
 132 struct chcr_dev {
 133         spinlock_t lock_chcr_dev;
 134         struct uld_ctx *u_ctx;
 135         unsigned char tx_channel_id;
 136         unsigned char rx_channel_id;
 137 };
 138
 139 struct uld_ctx {
 140         struct list_head entry;
 141         struct cxgb4_lld_info lldi;
 142         struct chcr_dev *dev;
 143 };
 144
 145 struct sge_opaque_hdr {
 146         void *dev;
 147         dma_addr_t addr[MAX_SKB_FRAGS + 1];
 148 };
 149
 150 struct chcr_ipsec_req {
 151         struct ulp_txpkt ulptx;
 152         struct ulptx_idata sc_imm;
 153         struct cpl_tx_sec_pdu sec_cpl;
 154         struct _key_ctx key_ctx;
 155 };
 156
 157 struct chcr_ipsec_wr {
 158         struct fw_ulptx_wr wreq;
 159         struct chcr_ipsec_req req;
 160 };
 161
 162 struct ipsec_sa_entry {
 163         int hmac_ctrl;
 164         unsigned int enckey_len;
 165         unsigned int kctx_len;
 166         unsigned int authsize;
 167         __be32 key_ctx_hdr;
 168         char salt[MAX_SALT];
 169         char key[2 * AES_MAX_KEY_SIZE];
 170 };
 171
 172 /*
 173  *      sgl_len - calculates the size of an SGL of the given capacity
 174  *      @n: the number of SGL entries
 175  *      Calculates the number of flits needed for a scatter/gather list that
 176  *      can hold the given number of entries.
 177  */
 178 static inline unsigned int sgl_len(unsigned int n)
 179 {
 180         n--;
 181         return (3 * n) / 2 + (n & 1) + 2;
 182 }
 183
 184 struct uld_ctx *assign_chcr_device(void);
 185 int chcr_send_wr(struct sk_buff *skb);
 186 int start_crypto(void);
 187 int stop_crypto(void);
 188 int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
 189                         const struct pkt_gl *pgl);
 190 int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev);
 191 int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
 192                      int err);
 193 int chcr_ipsec_xmit(struct sk_buff *skb, struct net_device *dev);
 194 void chcr_add_xfrmops(const struct cxgb4_lld_info *lld);
 195 #endif /* __CHCR_CORE_H__ */