drivers/fsi/fsi-master-hub.c

   1 /*
   2  * FSI hub master driver
   3  *
   4  * Copyright (C) IBM Corporation 2016
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/fsi.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/slab.h>
  21
  22 #include "fsi-master.h"
  23
  24 /* Control Registers */
  25 #define FSI_MMODE               0x0             /* R/W: mode */
  26 #define FSI_MDLYR               0x4             /* R/W: delay */
  27 #define FSI_MCRSP               0x8             /* R/W: clock rate */
  28 #define FSI_MENP0               0x10            /* R/W: enable */
  29 #define FSI_MLEVP0              0x18            /* R: plug detect */
  30 #define FSI_MSENP0              0x18            /* S: Set enable */
  31 #define FSI_MCENP0              0x20            /* C: Clear enable */
  32 #define FSI_MAEB                0x70            /* R: Error address */
  33 #define FSI_MVER                0x74            /* R: master version/type */
  34 #define FSI_MRESP0              0xd0            /* W: Port reset */
  35 #define FSI_MESRB0              0x1d0           /* R: Master error status */
  36 #define FSI_MRESB0              0x1d0           /* W: Reset bridge */
  37 #define FSI_MECTRL              0x2e0           /* W: Error control */
  38
  39 /* MMODE: Mode control */
  40 #define FSI_MMODE_EIP           0x80000000      /* Enable interrupt polling */
  41 #define FSI_MMODE_ECRC          0x40000000      /* Enable error recovery */
  42 #define FSI_MMODE_EPC           0x10000000      /* Enable parity checking */
  43 #define FSI_MMODE_P8_TO_LSB     0x00000010      /* Timeout value LSB */
  44                                                 /*   MSB=1, LSB=0 is 0.8 ms */
  45                                                 /*   MSB=0, LSB=1 is 0.9 ms */
  46 #define FSI_MMODE_CRS0SHFT      18              /* Clk rate selection 0 shift */
  47 #define FSI_MMODE_CRS0MASK      0x3ff           /* Clk rate selection 0 mask */
  48 #define FSI_MMODE_CRS1SHFT      8               /* Clk rate selection 1 shift */
  49 #define FSI_MMODE_CRS1MASK      0x3ff           /* Clk rate selection 1 mask */
  50
  51 /* MRESB: Reset brindge */
  52 #define FSI_MRESB_RST_GEN       0x80000000      /* General reset */
  53 #define FSI_MRESB_RST_ERR       0x40000000      /* Error Reset */
  54
  55 /* MRESB: Reset port */
  56 #define FSI_MRESP_RST_ALL_MASTER 0x20000000     /* Reset all FSI masters */
  57 #define FSI_MRESP_RST_ALL_LINK  0x10000000      /* Reset all FSI port contr. */
  58 #define FSI_MRESP_RST_MCR       0x08000000      /* Reset FSI master reg. */
  59 #define FSI_MRESP_RST_PYE       0x04000000      /* Reset FSI parity error */
  60 #define FSI_MRESP_RST_ALL       0xfc000000      /* Reset any error */
  61
  62 /* MECTRL: Error control */
  63 #define FSI_MECTRL_EOAE         0x8000          /* Enable machine check when */
  64                                                 /* master 0 in error */
  65 #define FSI_MECTRL_P8_AUTO_TERM 0x4000          /* Auto terminate */
  66
  67 #define FSI_ENGID_HUB_MASTER            0x1c
  68 #define FSI_HUB_LINK_OFFSET             0x80000
  69 #define FSI_HUB_LINK_SIZE               0x80000
  70 #define FSI_HUB_MASTER_MAX_LINKS        8
  71
  72 #define FSI_LINK_ENABLE_SETUP_TIME      10      /* in mS */
  73
  74 /*
  75  * FSI hub master support
  76  *
  77  * A hub master increases the number of potential target devices that the
  78  * primary FSI master can access. For each link a primary master supports,
  79  * each of those links can in turn be chained to a hub master with multiple
  80  * links of its own.
  81  *
  82  * The hub is controlled by a set of control registers exposed as a regular fsi
  83  * device (the hub->upstream device), and provides access to the downstream FSI
  84  * bus as through an address range on the slave itself (->addr and ->size).
  85  *
  86  * [This differs from "cascaded" masters, which expose the entire downstream
  87  * bus entirely through the fsi device address range, and so have a smaller
  88  * accessible address space.]
  89  */
  90 struct fsi_master_hub {
  91         struct fsi_master       master;
  92         struct fsi_device       *upstream;
  93         uint32_t                addr, size;     /* slave-relative addr of */
  94                                                 /* master address space */
  95 };
  96
  97 #define to_fsi_master_hub(m) container_of(m, struct fsi_master_hub, master)
  98
  99 static int hub_master_read(struct fsi_master *master, int link,
 100                         uint8_t id, uint32_t addr, void *val, size_t size)
 101 {
 102         struct fsi_master_hub *hub = to_fsi_master_hub(master);
 103
 104         if (id != 0)
 105                 return -EINVAL;
 106
 107         addr += hub->addr + (link * FSI_HUB_LINK_SIZE);
 108         return fsi_slave_read(hub->upstream->slave, addr, val, size);
 109 }
 110
 111 static int hub_master_write(struct fsi_master *master, int link,
 112                         uint8_t id, uint32_t addr, const void *val, size_t size)
 113 {
 114         struct fsi_master_hub *hub = to_fsi_master_hub(master);
 115
 116         if (id != 0)
 117                 return -EINVAL;
 118
 119         addr += hub->addr + (link * FSI_HUB_LINK_SIZE);
 120         return fsi_slave_write(hub->upstream->slave, addr, val, size);
 121 }
 122
 123 static int hub_master_break(struct fsi_master *master, int link)
 124 {
 125         uint32_t addr;
 126         __be32 cmd;
 127
 128         addr = 0x4;
 129         cmd = cpu_to_be32(0xc0de0000);
 130
 131         return hub_master_write(master, link, 0, addr, &cmd, sizeof(cmd));
 132 }
 133
 134 static int hub_master_link_enable(struct fsi_master *master, int link)
 135 {
 136         struct fsi_master_hub *hub = to_fsi_master_hub(master);
 137         int idx, bit;
 138         __be32 reg;
 139         int rc;
 140
 141         idx = link / 32;
 142         bit = link % 32;
 143
 144         reg = cpu_to_be32(0x80000000 >> bit);
 145
 146         rc = fsi_device_write(hub->upstream, FSI_MSENP0 + (4 * idx), &reg, 4);
 147
 148         mdelay(FSI_LINK_ENABLE_SETUP_TIME);
 149
 150         fsi_device_read(hub->upstream, FSI_MENP0 + (4 * idx), &reg, 4);
 151
 152         return rc;
 153 }
 154
 155 static void hub_master_release(struct device *dev)
 156 {
 157         struct fsi_master_hub *hub = to_fsi_master_hub(dev_to_fsi_master(dev));
 158
 159         kfree(hub);
 160 }
 161
 162 /* mmode encoders */
 163 static inline u32 fsi_mmode_crs0(u32 x)
 164 {
 165         return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT;
 166 }
 167
 168 static inline u32 fsi_mmode_crs1(u32 x)
 169 {
 170         return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT;
 171 }
 172
 173 static int hub_master_init(struct fsi_master_hub *hub)
 174 {
 175         struct fsi_device *dev = hub->upstream;
 176         __be32 reg;
 177         int rc;
 178
 179         reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
 180                         | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
 181         rc = fsi_device_write(dev, FSI_MRESP0, &reg, sizeof(reg));
 182         if (rc)
 183                 return rc;
 184
 185         /* Initialize the MFSI (hub master) engine */
 186         reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
 187                         | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
 188         rc = fsi_device_write(dev, FSI_MRESP0, &reg, sizeof(reg));
 189         if (rc)
 190                 return rc;
 191
 192         reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM);
 193         rc = fsi_device_write(dev, FSI_MECTRL, &reg, sizeof(reg));
 194         if (rc)
 195                 return rc;
 196
 197         reg = cpu_to_be32(FSI_MMODE_EIP | FSI_MMODE_ECRC | FSI_MMODE_EPC
 198                         | fsi_mmode_crs0(1) | fsi_mmode_crs1(1)
 199                         | FSI_MMODE_P8_TO_LSB);
 200         rc = fsi_device_write(dev, FSI_MMODE, &reg, sizeof(reg));
 201         if (rc)
 202                 return rc;
 203
 204         reg = cpu_to_be32(0xffff0000);
 205         rc = fsi_device_write(dev, FSI_MDLYR, &reg, sizeof(reg));
 206         if (rc)
 207                 return rc;
 208
 209         reg = cpu_to_be32(~0);
 210         rc = fsi_device_write(dev, FSI_MSENP0, &reg, sizeof(reg));
 211         if (rc)
 212                 return rc;
 213
 214         /* Leave enabled long enough for master logic to set up */
 215         mdelay(FSI_LINK_ENABLE_SETUP_TIME);
 216
 217         rc = fsi_device_write(dev, FSI_MCENP0, &reg, sizeof(reg));
 218         if (rc)
 219                 return rc;
 220
 221         rc = fsi_device_read(dev, FSI_MAEB, &reg, sizeof(reg));
 222         if (rc)
 223                 return rc;
 224
 225         reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK);
 226         rc = fsi_device_write(dev, FSI_MRESP0, &reg, sizeof(reg));
 227         if (rc)
 228                 return rc;
 229
 230         rc = fsi_device_read(dev, FSI_MLEVP0, &reg, sizeof(reg));
 231         if (rc)
 232                 return rc;
 233
 234         /* Reset the master bridge */
 235         reg = cpu_to_be32(FSI_MRESB_RST_GEN);
 236         rc = fsi_device_write(dev, FSI_MRESB0, &reg, sizeof(reg));
 237         if (rc)
 238                 return rc;
 239
 240         reg = cpu_to_be32(FSI_MRESB_RST_ERR);
 241         return fsi_device_write(dev, FSI_MRESB0, &reg, sizeof(reg));
 242 }
 243
 244 static int hub_master_probe(struct device *dev)
 245 {
 246         struct fsi_device *fsi_dev = to_fsi_dev(dev);
 247         struct fsi_master_hub *hub;
 248         uint32_t reg, links;
 249         __be32 __reg;
 250         int rc;
 251
 252         rc = fsi_device_read(fsi_dev, FSI_MVER, &__reg, sizeof(__reg));
 253         if (rc)
 254                 return rc;
 255
 256         reg = be32_to_cpu(__reg);
 257         links = (reg >> 8) & 0xff;
 258         dev_dbg(dev, "hub version %08x (%d links)\n", reg, links);
 259
 260         rc = fsi_slave_claim_range(fsi_dev->slave, FSI_HUB_LINK_OFFSET,
 261                         FSI_HUB_LINK_SIZE * links);
 262         if (rc) {
 263                 dev_err(dev, "can't claim slave address range for links");
 264                 return rc;
 265         }
 266
 267         hub = kzalloc(sizeof(*hub), GFP_KERNEL);
 268         if (!hub) {
 269                 rc = -ENOMEM;
 270                 goto err_release;
 271         }
 272
 273         hub->addr = FSI_HUB_LINK_OFFSET;
 274         hub->size = FSI_HUB_LINK_SIZE * links;
 275         hub->upstream = fsi_dev;
 276
 277         hub->master.dev.parent = dev;
 278         hub->master.dev.release = hub_master_release;
 279         hub->master.dev.of_node = of_node_get(dev_of_node(dev));
 280
 281         hub->master.n_links = links;
 282         hub->master.read = hub_master_read;
 283         hub->master.write = hub_master_write;
 284         hub->master.send_break = hub_master_break;
 285         hub->master.link_enable = hub_master_link_enable;
 286
 287         dev_set_drvdata(dev, hub);
 288
 289         hub_master_init(hub);
 290
 291         rc = fsi_master_register(&hub->master);
 292         if (rc)
 293                 goto err_release;
 294
 295         /* At this point, fsi_master_register performs the device_initialize(),
 296          * and holds the sole reference on master.dev. This means the device
 297          * will be freed (via ->release) during any subsequent call to
 298          * fsi_master_unregister.  We add our own reference to it here, so we
 299          * can perform cleanup (in _remove()) without it being freed before
 300          * we're ready.
 301          */
 302         get_device(&hub->master.dev);
 303         return 0;
 304
 305 err_release:
 306         fsi_slave_release_range(fsi_dev->slave, FSI_HUB_LINK_OFFSET,
 307                         FSI_HUB_LINK_SIZE * links);
 308         return rc;
 309 }
 310
 311 static int hub_master_remove(struct device *dev)
 312 {
 313         struct fsi_master_hub *hub = dev_get_drvdata(dev);
 314
 315         fsi_master_unregister(&hub->master);
 316         fsi_slave_release_range(hub->upstream->slave, hub->addr, hub->size);
 317         of_node_put(hub->master.dev.of_node);
 318
 319         /*
 320          * master.dev will likely be ->release()ed after this, which free()s
 321          * the hub
 322          */
 323         put_device(&hub->master.dev);
 324
 325         return 0;
 326 }
 327
 328 static struct fsi_device_id hub_master_ids[] = {
 329         {
 330                 .engine_type = FSI_ENGID_HUB_MASTER,
 331                 .version = FSI_VERSION_ANY,
 332         },
 333         { 0 }
 334 };
 335
 336 static struct fsi_driver hub_master_driver = {
 337         .id_table = hub_master_ids,
 338         .drv = {
 339                 .name = "fsi-master-hub",
 340                 .bus = &fsi_bus_type,
 341                 .probe = hub_master_probe,
 342                 .remove = hub_master_remove,
 343         }
 344 };
 345
 346 module_fsi_driver(hub_master_driver);
 347 MODULE_LICENSE("GPL");