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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / iio / accel / adxl372.c
blob3b84cb243a87415dd3bb36338bf4b5e44d0f16e9
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ADXL372 3-Axis Digital Accelerometer core driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/regmap.h>
13 #include <linux/spi/spi.h>
14
15 #include <linux/iio/iio.h>
16 #include <linux/iio/sysfs.h>
17 #include <linux/iio/buffer.h>
18 #include <linux/iio/events.h>
19 #include <linux/iio/trigger.h>
20 #include <linux/iio/trigger_consumer.h>
21 #include <linux/iio/triggered_buffer.h>
22
23 #include "adxl372.h"
24
25 /* ADXL372 registers definition */
26 #define ADXL372_DEVID 0x00
27 #define ADXL372_DEVID_MST 0x01
28 #define ADXL372_PARTID 0x02
29 #define ADXL372_STATUS_1 0x04
30 #define ADXL372_STATUS_2 0x05
31 #define ADXL372_FIFO_ENTRIES_2 0x06
32 #define ADXL372_FIFO_ENTRIES_1 0x07
33 #define ADXL372_X_DATA_H 0x08
34 #define ADXL372_X_DATA_L 0x09
35 #define ADXL372_Y_DATA_H 0x0A
36 #define ADXL372_Y_DATA_L 0x0B
37 #define ADXL372_Z_DATA_H 0x0C
38 #define ADXL372_Z_DATA_L 0x0D
39 #define ADXL372_X_MAXPEAK_H 0x15
40 #define ADXL372_X_MAXPEAK_L 0x16
41 #define ADXL372_Y_MAXPEAK_H 0x17
42 #define ADXL372_Y_MAXPEAK_L 0x18
43 #define ADXL372_Z_MAXPEAK_H 0x19
44 #define ADXL372_Z_MAXPEAK_L 0x1A
45 #define ADXL372_OFFSET_X 0x20
46 #define ADXL372_OFFSET_Y 0x21
47 #define ADXL372_OFFSET_Z 0x22
48 #define ADXL372_X_THRESH_ACT_H 0x23
49 #define ADXL372_X_THRESH_ACT_L 0x24
50 #define ADXL372_Y_THRESH_ACT_H 0x25
51 #define ADXL372_Y_THRESH_ACT_L 0x26
52 #define ADXL372_Z_THRESH_ACT_H 0x27
53 #define ADXL372_Z_THRESH_ACT_L 0x28
54 #define ADXL372_TIME_ACT 0x29
55 #define ADXL372_X_THRESH_INACT_H 0x2A
56 #define ADXL372_X_THRESH_INACT_L 0x2B
57 #define ADXL372_Y_THRESH_INACT_H 0x2C
58 #define ADXL372_Y_THRESH_INACT_L 0x2D
59 #define ADXL372_Z_THRESH_INACT_H 0x2E
60 #define ADXL372_Z_THRESH_INACT_L 0x2F
61 #define ADXL372_TIME_INACT_H 0x30
62 #define ADXL372_TIME_INACT_L 0x31
63 #define ADXL372_X_THRESH_ACT2_H 0x32
64 #define ADXL372_X_THRESH_ACT2_L 0x33
65 #define ADXL372_Y_THRESH_ACT2_H 0x34
66 #define ADXL372_Y_THRESH_ACT2_L 0x35
67 #define ADXL372_Z_THRESH_ACT2_H 0x36
68 #define ADXL372_Z_THRESH_ACT2_L 0x37
69 #define ADXL372_HPF 0x38
70 #define ADXL372_FIFO_SAMPLES 0x39
71 #define ADXL372_FIFO_CTL 0x3A
72 #define ADXL372_INT1_MAP 0x3B
73 #define ADXL372_INT2_MAP 0x3C
74 #define ADXL372_TIMING 0x3D
75 #define ADXL372_MEASURE 0x3E
76 #define ADXL372_POWER_CTL 0x3F
77 #define ADXL372_SELF_TEST 0x40
78 #define ADXL372_RESET 0x41
79 #define ADXL372_FIFO_DATA 0x42
80
81 #define ADXL372_DEVID_VAL 0xAD
82 #define ADXL372_PARTID_VAL 0xFA
83 #define ADXL372_RESET_CODE 0x52
84
85 /* ADXL372_POWER_CTL */
86 #define ADXL372_POWER_CTL_MODE_MSK GENMASK_ULL(1, 0)
87 #define ADXL372_POWER_CTL_MODE(x) (((x) & 0x3) << 0)
88
89 /* ADXL372_MEASURE */
90 #define ADXL372_MEASURE_LINKLOOP_MSK GENMASK_ULL(5, 4)
91 #define ADXL372_MEASURE_LINKLOOP_MODE(x) (((x) & 0x3) << 4)
92 #define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK_ULL(2, 0)
93 #define ADXL372_MEASURE_BANDWIDTH_MODE(x) (((x) & 0x7) << 0)
94
95 /* ADXL372_TIMING */
96 #define ADXL372_TIMING_ODR_MSK GENMASK_ULL(7, 5)
97 #define ADXL372_TIMING_ODR_MODE(x) (((x) & 0x7) << 5)
98
99 /* ADXL372_FIFO_CTL */
100 #define ADXL372_FIFO_CTL_FORMAT_MSK GENMASK(5, 3)
101 #define ADXL372_FIFO_CTL_FORMAT_MODE(x) (((x) & 0x7) << 3)
102 #define ADXL372_FIFO_CTL_MODE_MSK GENMASK(2, 1)
103 #define ADXL372_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 1)
104 #define ADXL372_FIFO_CTL_SAMPLES_MSK BIT(1)
105 #define ADXL372_FIFO_CTL_SAMPLES_MODE(x) (((x) > 0xFF) ? 1 : 0)
106
107 /* ADXL372_STATUS_1 */
108 #define ADXL372_STATUS_1_DATA_RDY(x) (((x) >> 0) & 0x1)
109 #define ADXL372_STATUS_1_FIFO_RDY(x) (((x) >> 1) & 0x1)
110 #define ADXL372_STATUS_1_FIFO_FULL(x) (((x) >> 2) & 0x1)
111 #define ADXL372_STATUS_1_FIFO_OVR(x) (((x) >> 3) & 0x1)
112 #define ADXL372_STATUS_1_USR_NVM_BUSY(x) (((x) >> 5) & 0x1)
113 #define ADXL372_STATUS_1_AWAKE(x) (((x) >> 6) & 0x1)
114 #define ADXL372_STATUS_1_ERR_USR_REGS(x) (((x) >> 7) & 0x1)
115
116 /* ADXL372_INT1_MAP */
117 #define ADXL372_INT1_MAP_DATA_RDY_MSK BIT(0)
118 #define ADXL372_INT1_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0)
119 #define ADXL372_INT1_MAP_FIFO_RDY_MSK BIT(1)
120 #define ADXL372_INT1_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1)
121 #define ADXL372_INT1_MAP_FIFO_FULL_MSK BIT(2)
122 #define ADXL372_INT1_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2)
123 #define ADXL372_INT1_MAP_FIFO_OVR_MSK BIT(3)
124 #define ADXL372_INT1_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3)
125 #define ADXL372_INT1_MAP_INACT_MSK BIT(4)
126 #define ADXL372_INT1_MAP_INACT_MODE(x) (((x) & 0x1) << 4)
127 #define ADXL372_INT1_MAP_ACT_MSK BIT(5)
128 #define ADXL372_INT1_MAP_ACT_MODE(x) (((x) & 0x1) << 5)
129 #define ADXL372_INT1_MAP_AWAKE_MSK BIT(6)
130 #define ADXL372_INT1_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6)
131 #define ADXL372_INT1_MAP_LOW_MSK BIT(7)
132 #define ADXL372_INT1_MAP_LOW_MODE(x) (((x) & 0x1) << 7)
133
134 /* The ADXL372 includes a deep, 512 sample FIFO buffer */
135 #define ADXL372_FIFO_SIZE 512
136
137 /*
138 * At +/- 200g with 12-bit resolution, scale is computed as:
139 * (200 + 200) * 9.81 / (2^12 - 1) = 0.958241
140 */
141 #define ADXL372_USCALE 958241
142
143 enum adxl372_op_mode {
144 ADXL372_STANDBY,
145 ADXL372_WAKE_UP,
146 ADXL372_INSTANT_ON,
147 ADXL372_FULL_BW_MEASUREMENT,
148 };
149
150 enum adxl372_act_proc_mode {
151 ADXL372_DEFAULT,
152 ADXL372_LINKED,
153 ADXL372_LOOPED,
154 };
155
156 enum adxl372_th_activity {
157 ADXL372_ACTIVITY,
158 ADXL372_ACTIVITY2,
159 ADXL372_INACTIVITY,
160 };
161
162 enum adxl372_odr {
163 ADXL372_ODR_400HZ,
164 ADXL372_ODR_800HZ,
165 ADXL372_ODR_1600HZ,
166 ADXL372_ODR_3200HZ,
167 ADXL372_ODR_6400HZ,
168 };
169
170 enum adxl372_bandwidth {
171 ADXL372_BW_200HZ,
172 ADXL372_BW_400HZ,
173 ADXL372_BW_800HZ,
174 ADXL372_BW_1600HZ,
175 ADXL372_BW_3200HZ,
176 };
177
178 static const unsigned int adxl372_th_reg_high_addr[3] = {
179 [ADXL372_ACTIVITY] = ADXL372_X_THRESH_ACT_H,
180 [ADXL372_ACTIVITY2] = ADXL372_X_THRESH_ACT2_H,
181 [ADXL372_INACTIVITY] = ADXL372_X_THRESH_INACT_H,
182 };
183
184 enum adxl372_fifo_format {
185 ADXL372_XYZ_FIFO,
186 ADXL372_X_FIFO,
187 ADXL372_Y_FIFO,
188 ADXL372_XY_FIFO,
189 ADXL372_Z_FIFO,
190 ADXL372_XZ_FIFO,
191 ADXL372_YZ_FIFO,
192 ADXL372_XYZ_PEAK_FIFO,
193 };
194
195 enum adxl372_fifo_mode {
196 ADXL372_FIFO_BYPASSED,
197 ADXL372_FIFO_STREAMED,
198 ADXL372_FIFO_TRIGGERED,
199 ADXL372_FIFO_OLD_SAVED
200 };
201
202 static const int adxl372_samp_freq_tbl[5] = {
203 400, 800, 1600, 3200, 6400,
204 };
205
206 static const int adxl372_bw_freq_tbl[5] = {
207 200, 400, 800, 1600, 3200,
208 };
209
210 struct adxl372_axis_lookup {
211 unsigned int bits;
212 enum adxl372_fifo_format fifo_format;
213 };
214
215 static const struct adxl372_axis_lookup adxl372_axis_lookup_table[] = {
216 { BIT(0), ADXL372_X_FIFO },
217 { BIT(1), ADXL372_Y_FIFO },
218 { BIT(2), ADXL372_Z_FIFO },
219 { BIT(0) | BIT(1), ADXL372_XY_FIFO },
220 { BIT(0) | BIT(2), ADXL372_XZ_FIFO },
221 { BIT(1) | BIT(2), ADXL372_YZ_FIFO },
222 { BIT(0) | BIT(1) | BIT(2), ADXL372_XYZ_FIFO },
223 };
224
225 #define ADXL372_ACCEL_CHANNEL(index, reg, axis) { \
226 .type = IIO_ACCEL, \
227 .address = reg, \
228 .modified = 1, \
229 .channel2 = IIO_MOD_##axis, \
230 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
231 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
232 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
233 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
234 .scan_index = index, \
235 .scan_type = { \
236 .sign = 's', \
237 .realbits = 12, \
238 .storagebits = 16, \
239 .shift = 4, \
240 }, \
241 }
242
243 static const struct iio_chan_spec adxl372_channels[] = {
244 ADXL372_ACCEL_CHANNEL(0, ADXL372_X_DATA_H, X),
245 ADXL372_ACCEL_CHANNEL(1, ADXL372_Y_DATA_H, Y),
246 ADXL372_ACCEL_CHANNEL(2, ADXL372_Z_DATA_H, Z),
247 };
248
249 struct adxl372_state {
250 int irq;
251 struct device *dev;
252 struct regmap *regmap;
253 struct iio_trigger *dready_trig;
254 enum adxl372_fifo_mode fifo_mode;
255 enum adxl372_fifo_format fifo_format;
256 enum adxl372_op_mode op_mode;
257 enum adxl372_act_proc_mode act_proc_mode;
258 enum adxl372_odr odr;
259 enum adxl372_bandwidth bw;
260 u32 act_time_ms;
261 u32 inact_time_ms;
262 u8 fifo_set_size;
263 u8 int1_bitmask;
264 u8 int2_bitmask;
265 u16 watermark;
266 __be16 fifo_buf[ADXL372_FIFO_SIZE];
267 };
268
269 static const unsigned long adxl372_channel_masks[] = {
270 BIT(0), BIT(1), BIT(2),
271 BIT(0) | BIT(1),
272 BIT(0) | BIT(2),
273 BIT(1) | BIT(2),
274 BIT(0) | BIT(1) | BIT(2),
275 0
276 };
277
278 static int adxl372_read_axis(struct adxl372_state *st, u8 addr)
279 {
280 __be16 regval;
281 int ret;
282
283 ret = regmap_bulk_read(st->regmap, addr, &regval, sizeof(regval));
284 if (ret < 0)
285 return ret;
286
287 return be16_to_cpu(regval);
288 }
289
290 static int adxl372_set_op_mode(struct adxl372_state *st,
291 enum adxl372_op_mode op_mode)
292 {
293 int ret;
294
295 ret = regmap_update_bits(st->regmap, ADXL372_POWER_CTL,
296 ADXL372_POWER_CTL_MODE_MSK,
297 ADXL372_POWER_CTL_MODE(op_mode));
298 if (ret < 0)
299 return ret;
300
301 st->op_mode = op_mode;
302
303 return ret;
304 }
305
306 static int adxl372_set_odr(struct adxl372_state *st,
307 enum adxl372_odr odr)
308 {
309 int ret;
310
311 ret = regmap_update_bits(st->regmap, ADXL372_TIMING,
312 ADXL372_TIMING_ODR_MSK,
313 ADXL372_TIMING_ODR_MODE(odr));
314 if (ret < 0)
315 return ret;
316
317 st->odr = odr;
318
319 return ret;
320 }
321
322 static int adxl372_find_closest_match(const int *array,
323 unsigned int size, int val)
324 {
325 int i;
326
327 for (i = 0; i < size; i++) {
328 if (val <= array[i])
329 return i;
330 }
331
332 return size - 1;
333 }
334
335 static int adxl372_set_bandwidth(struct adxl372_state *st,
336 enum adxl372_bandwidth bw)
337 {
338 int ret;
339
340 ret = regmap_update_bits(st->regmap, ADXL372_MEASURE,
341 ADXL372_MEASURE_BANDWIDTH_MSK,
342 ADXL372_MEASURE_BANDWIDTH_MODE(bw));
343 if (ret < 0)
344 return ret;
345
346 st->bw = bw;
347
348 return ret;
349 }
350
351 static int adxl372_set_act_proc_mode(struct adxl372_state *st,
352 enum adxl372_act_proc_mode mode)
353 {
354 int ret;
355
356 ret = regmap_update_bits(st->regmap,
357 ADXL372_MEASURE,
358 ADXL372_MEASURE_LINKLOOP_MSK,
359 ADXL372_MEASURE_LINKLOOP_MODE(mode));
360 if (ret < 0)
361 return ret;
362
363 st->act_proc_mode = mode;
364
365 return ret;
366 }
367
368 static int adxl372_set_activity_threshold(struct adxl372_state *st,
369 enum adxl372_th_activity act,
370 bool ref_en, bool enable,
371 unsigned int threshold)
372 {
373 unsigned char buf[6];
374 unsigned char th_reg_high_val, th_reg_low_val, th_reg_high_addr;
375
376 /* scale factor is 100 mg/code */
377 th_reg_high_val = (threshold / 100) >> 3;
378 th_reg_low_val = ((threshold / 100) << 5) | (ref_en << 1) | enable;
379 th_reg_high_addr = adxl372_th_reg_high_addr[act];
380
381 buf[0] = th_reg_high_val;
382 buf[1] = th_reg_low_val;
383 buf[2] = th_reg_high_val;
384 buf[3] = th_reg_low_val;
385 buf[4] = th_reg_high_val;
386 buf[5] = th_reg_low_val;
387
388 return regmap_bulk_write(st->regmap, th_reg_high_addr,
389 buf, ARRAY_SIZE(buf));
390 }
391
392 static int adxl372_set_activity_time_ms(struct adxl372_state *st,
393 unsigned int act_time_ms)
394 {
395 unsigned int reg_val, scale_factor;
396 int ret;
397
398 /*
399 * 3.3 ms per code is the scale factor of the TIME_ACT register for
400 * ODR = 6400 Hz. It is 6.6 ms per code for ODR = 3200 Hz and below.
401 */
402 if (st->odr == ADXL372_ODR_6400HZ)
403 scale_factor = 3300;
404 else
405 scale_factor = 6600;
406
407 reg_val = DIV_ROUND_CLOSEST(act_time_ms * 1000, scale_factor);
408
409 /* TIME_ACT register is 8 bits wide */
410 if (reg_val > 0xFF)
411 reg_val = 0xFF;
412
413 ret = regmap_write(st->regmap, ADXL372_TIME_ACT, reg_val);
414 if (ret < 0)
415 return ret;
416
417 st->act_time_ms = act_time_ms;
418
419 return ret;
420 }
421
422 static int adxl372_set_inactivity_time_ms(struct adxl372_state *st,
423 unsigned int inact_time_ms)
424 {
425 unsigned int reg_val_h, reg_val_l, res, scale_factor;
426 int ret;
427
428 /*
429 * 13 ms per code is the scale factor of the TIME_INACT register for
430 * ODR = 6400 Hz. It is 26 ms per code for ODR = 3200 Hz and below.
431 */
432 if (st->odr == ADXL372_ODR_6400HZ)
433 scale_factor = 13;
434 else
435 scale_factor = 26;
436
437 res = DIV_ROUND_CLOSEST(inact_time_ms, scale_factor);
438 reg_val_h = (res >> 8) & 0xFF;
439 reg_val_l = res & 0xFF;
440
441 ret = regmap_write(st->regmap, ADXL372_TIME_INACT_H, reg_val_h);
442 if (ret < 0)
443 return ret;
444
445 ret = regmap_write(st->regmap, ADXL372_TIME_INACT_L, reg_val_l);
446 if (ret < 0)
447 return ret;
448
449 st->inact_time_ms = inact_time_ms;
450
451 return ret;
452 }
453
454 static int adxl372_set_interrupts(struct adxl372_state *st,
455 unsigned char int1_bitmask,
456 unsigned char int2_bitmask)
457 {
458 int ret;
459
460 ret = regmap_write(st->regmap, ADXL372_INT1_MAP, int1_bitmask);
461 if (ret < 0)
462 return ret;
463
464 return regmap_write(st->regmap, ADXL372_INT2_MAP, int2_bitmask);
465 }
466
467 static int adxl372_configure_fifo(struct adxl372_state *st)
468 {
469 unsigned int fifo_samples, fifo_ctl;
470 int ret;
471
472 /* FIFO must be configured while in standby mode */
473 ret = adxl372_set_op_mode(st, ADXL372_STANDBY);
474 if (ret < 0)
475 return ret;
476
477 fifo_samples = st->watermark & 0xFF;
478 fifo_ctl = ADXL372_FIFO_CTL_FORMAT_MODE(st->fifo_format) |
479 ADXL372_FIFO_CTL_MODE_MODE(st->fifo_mode) |
480 ADXL372_FIFO_CTL_SAMPLES_MODE(st->watermark);
481
482 ret = regmap_write(st->regmap, ADXL372_FIFO_SAMPLES, fifo_samples);
483 if (ret < 0)
484 return ret;
485
486 ret = regmap_write(st->regmap, ADXL372_FIFO_CTL, fifo_ctl);
487 if (ret < 0)
488 return ret;
489
490 return adxl372_set_op_mode(st, ADXL372_FULL_BW_MEASUREMENT);
491 }
492
493 static int adxl372_get_status(struct adxl372_state *st,
494 u8 *status1, u8 *status2,
495 u16 *fifo_entries)
496 {
497 __be32 buf;
498 u32 val;
499 int ret;
500
501 /* STATUS1, STATUS2, FIFO_ENTRIES2 and FIFO_ENTRIES are adjacent regs */
502 ret = regmap_bulk_read(st->regmap, ADXL372_STATUS_1,
503 &buf, sizeof(buf));
504 if (ret < 0)
505 return ret;
506
507 val = be32_to_cpu(buf);
508
509 *status1 = (val >> 24) & 0x0F;
510 *status2 = (val >> 16) & 0x0F;
511 /*
512 * FIFO_ENTRIES contains the least significant byte, and FIFO_ENTRIES2
513 * contains the two most significant bits
514 */
515 *fifo_entries = val & 0x3FF;
516
517 return ret;
518 }
519
520 static irqreturn_t adxl372_trigger_handler(int irq, void *p)
521 {
522 struct iio_poll_func *pf = p;
523 struct iio_dev *indio_dev = pf->indio_dev;
524 struct adxl372_state *st = iio_priv(indio_dev);
525 u8 status1, status2;
526 u16 fifo_entries;
527 int i, ret;
528
529 ret = adxl372_get_status(st, &status1, &status2, &fifo_entries);
530 if (ret < 0)
531 goto err;
532
533 if (st->fifo_mode != ADXL372_FIFO_BYPASSED &&
534 ADXL372_STATUS_1_FIFO_FULL(status1)) {
535 /*
536 * When reading data from multiple axes from the FIFO,
537 * to ensure that data is not overwritten and stored out
538 * of order at least one sample set must be left in the
539 * FIFO after every read.
540 */
541 fifo_entries -= st->fifo_set_size;
542
543 /* Read data from the FIFO */
544 ret = regmap_noinc_read(st->regmap, ADXL372_FIFO_DATA,
545 st->fifo_buf,
546 fifo_entries * sizeof(u16));
547 if (ret < 0)
548 goto err;
549
550 /* Each sample is 2 bytes */
551 for (i = 0; i < fifo_entries * sizeof(u16);
552 i += st->fifo_set_size * sizeof(u16))
553 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
554 }
555 err:
556 iio_trigger_notify_done(indio_dev->trig);
557 return IRQ_HANDLED;
558 }
559
560 static int adxl372_setup(struct adxl372_state *st)
561 {
562 unsigned int regval;
563 int ret;
564
565 ret = regmap_read(st->regmap, ADXL372_DEVID, &regval);
566 if (ret < 0)
567 return ret;
568
569 if (regval != ADXL372_DEVID_VAL) {
570 dev_err(st->dev, "Invalid chip id %x\n", regval);
571 return -ENODEV;
572 }
573
574 ret = adxl372_set_op_mode(st, ADXL372_STANDBY);
575 if (ret < 0)
576 return ret;
577
578 /* Set threshold for activity detection to 1g */
579 ret = adxl372_set_activity_threshold(st, ADXL372_ACTIVITY,
580 true, true, 1000);
581 if (ret < 0)
582 return ret;
583
584 /* Set threshold for inactivity detection to 100mg */
585 ret = adxl372_set_activity_threshold(st, ADXL372_INACTIVITY,
586 true, true, 100);
587 if (ret < 0)
588 return ret;
589
590 /* Set activity processing in Looped mode */
591 ret = adxl372_set_act_proc_mode(st, ADXL372_LOOPED);
592 if (ret < 0)
593 return ret;
594
595 ret = adxl372_set_odr(st, ADXL372_ODR_6400HZ);
596 if (ret < 0)
597 return ret;
598
599 ret = adxl372_set_bandwidth(st, ADXL372_BW_3200HZ);
600 if (ret < 0)
601 return ret;
602
603 /* Set activity timer to 1ms */
604 ret = adxl372_set_activity_time_ms(st, 1);
605 if (ret < 0)
606 return ret;
607
608 /* Set inactivity timer to 10s */
609 ret = adxl372_set_inactivity_time_ms(st, 10000);
610 if (ret < 0)
611 return ret;
612
613 /* Set the mode of operation to full bandwidth measurement mode */
614 return adxl372_set_op_mode(st, ADXL372_FULL_BW_MEASUREMENT);
615 }
616
617 static int adxl372_reg_access(struct iio_dev *indio_dev,
618 unsigned int reg,
619 unsigned int writeval,
620 unsigned int *readval)
621 {
622 struct adxl372_state *st = iio_priv(indio_dev);
623
624 if (readval)
625 return regmap_read(st->regmap, reg, readval);
626 else
627 return regmap_write(st->regmap, reg, writeval);
628 }
629
630 static int adxl372_read_raw(struct iio_dev *indio_dev,
631 struct iio_chan_spec const *chan,
632 int *val, int *val2, long info)
633 {
634 struct adxl372_state *st = iio_priv(indio_dev);
635 int ret;
636
637 switch (info) {
638 case IIO_CHAN_INFO_RAW:
639 ret = iio_device_claim_direct_mode(indio_dev);
640 if (ret)
641 return ret;
642
643 ret = adxl372_read_axis(st, chan->address);
644 iio_device_release_direct_mode(indio_dev);
645 if (ret < 0)
646 return ret;
647
648 *val = sign_extend32(ret >> chan->scan_type.shift,
649 chan->scan_type.realbits - 1);
650 return IIO_VAL_INT;
651 case IIO_CHAN_INFO_SCALE:
652 *val = 0;
653 *val2 = ADXL372_USCALE;
654 return IIO_VAL_INT_PLUS_MICRO;
655 case IIO_CHAN_INFO_SAMP_FREQ:
656 *val = adxl372_samp_freq_tbl[st->odr];
657 return IIO_VAL_INT;
658 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
659 *val = adxl372_bw_freq_tbl[st->bw];
660 return IIO_VAL_INT;
661 }
662
663 return -EINVAL;
664 }
665
666 static int adxl372_write_raw(struct iio_dev *indio_dev,
667 struct iio_chan_spec const *chan,
668 int val, int val2, long info)
669 {
670 struct adxl372_state *st = iio_priv(indio_dev);
671 int odr_index, bw_index, ret;
672
673 switch (info) {
674 case IIO_CHAN_INFO_SAMP_FREQ:
675 odr_index = adxl372_find_closest_match(adxl372_samp_freq_tbl,
676 ARRAY_SIZE(adxl372_samp_freq_tbl),
677 val);
678 ret = adxl372_set_odr(st, odr_index);
679 if (ret < 0)
680 return ret;
681 /*
682 * The timer period depends on the ODR selected.
683 * At 3200 Hz and below, it is 6.6 ms; at 6400 Hz, it is 3.3 ms
684 */
685 ret = adxl372_set_activity_time_ms(st, st->act_time_ms);
686 if (ret < 0)
687 return ret;
688 /*
689 * The timer period depends on the ODR selected.
690 * At 3200 Hz and below, it is 26 ms; at 6400 Hz, it is 13 ms
691 */
692 ret = adxl372_set_inactivity_time_ms(st, st->inact_time_ms);
693 if (ret < 0)
694 return ret;
695 /*
696 * The maximum bandwidth is constrained to at most half of
697 * the ODR to ensure that the Nyquist criteria is not violated
698 */
699 if (st->bw > odr_index)
700 ret = adxl372_set_bandwidth(st, odr_index);
701
702 return ret;
703 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
704 bw_index = adxl372_find_closest_match(adxl372_bw_freq_tbl,
705 ARRAY_SIZE(adxl372_bw_freq_tbl),
706 val);
707 return adxl372_set_bandwidth(st, bw_index);
708 default:
709 return -EINVAL;
710 }
711 }
712
713 static ssize_t adxl372_show_filter_freq_avail(struct device *dev,
714 struct device_attribute *attr,
715 char *buf)
716 {
717 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
718 struct adxl372_state *st = iio_priv(indio_dev);
719 int i;
720 size_t len = 0;
721
722 for (i = 0; i <= st->odr; i++)
723 len += scnprintf(buf + len, PAGE_SIZE - len,
724 "%d ", adxl372_bw_freq_tbl[i]);
725
726 buf[len - 1] = '\n';
727
728 return len;
729 }
730
731 static ssize_t adxl372_get_fifo_enabled(struct device *dev,
732 struct device_attribute *attr,
733 char *buf)
734 {
735 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
736 struct adxl372_state *st = iio_priv(indio_dev);
737
738 return sprintf(buf, "%d\n", st->fifo_mode);
739 }
740
741 static ssize_t adxl372_get_fifo_watermark(struct device *dev,
742 struct device_attribute *attr,
743 char *buf)
744 {
745 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
746 struct adxl372_state *st = iio_priv(indio_dev);
747
748 return sprintf(buf, "%d\n", st->watermark);
749 }
750
751 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
752 static IIO_CONST_ATTR(hwfifo_watermark_max,
753 __stringify(ADXL372_FIFO_SIZE));
754 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
755 adxl372_get_fifo_watermark, NULL, 0);
756 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
757 adxl372_get_fifo_enabled, NULL, 0);
758
759 static const struct attribute *adxl372_fifo_attributes[] = {
760 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
761 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
762 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
763 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
764 NULL,
765 };
766
767 static int adxl372_set_watermark(struct iio_dev *indio_dev, unsigned int val)
768 {
769 struct adxl372_state *st = iio_priv(indio_dev);
770
771 if (val > ADXL372_FIFO_SIZE)
772 val = ADXL372_FIFO_SIZE;
773
774 st->watermark = val;
775
776 return 0;
777 }
778
779 static int adxl372_buffer_postenable(struct iio_dev *indio_dev)
780 {
781 struct adxl372_state *st = iio_priv(indio_dev);
782 unsigned int mask;
783 int i, ret;
784
785 ret = adxl372_set_interrupts(st, ADXL372_INT1_MAP_FIFO_FULL_MSK, 0);
786 if (ret < 0)
787 return ret;
788
789 mask = *indio_dev->active_scan_mask;
790
791 for (i = 0; i < ARRAY_SIZE(adxl372_axis_lookup_table); i++) {
792 if (mask == adxl372_axis_lookup_table[i].bits)
793 break;
794 }
795
796 if (i == ARRAY_SIZE(adxl372_axis_lookup_table))
797 return -EINVAL;
798
799 st->fifo_format = adxl372_axis_lookup_table[i].fifo_format;
800 st->fifo_set_size = bitmap_weight(indio_dev->active_scan_mask,
801 indio_dev->masklength);
802 /*
803 * The 512 FIFO samples can be allotted in several ways, such as:
804 * 170 sample sets of concurrent 3-axis data
805 * 256 sample sets of concurrent 2-axis data (user selectable)
806 * 512 sample sets of single-axis data
807 */
808 if ((st->watermark * st->fifo_set_size) > ADXL372_FIFO_SIZE)
809 st->watermark = (ADXL372_FIFO_SIZE / st->fifo_set_size);
810
811 st->fifo_mode = ADXL372_FIFO_STREAMED;
812
813 ret = adxl372_configure_fifo(st);
814 if (ret < 0) {
815 st->fifo_mode = ADXL372_FIFO_BYPASSED;
816 adxl372_set_interrupts(st, 0, 0);
817 return ret;
818 }
819
820 return iio_triggered_buffer_postenable(indio_dev);
821 }
822
823 static int adxl372_buffer_predisable(struct iio_dev *indio_dev)
824 {
825 struct adxl372_state *st = iio_priv(indio_dev);
826 int ret;
827
828 ret = iio_triggered_buffer_predisable(indio_dev);
829 if (ret < 0)
830 return ret;
831
832 adxl372_set_interrupts(st, 0, 0);
833 st->fifo_mode = ADXL372_FIFO_BYPASSED;
834 adxl372_configure_fifo(st);
835
836 return 0;
837 }
838
839 static const struct iio_buffer_setup_ops adxl372_buffer_ops = {
840 .postenable = adxl372_buffer_postenable,
841 .predisable = adxl372_buffer_predisable,
842 };
843
844 static int adxl372_dready_trig_set_state(struct iio_trigger *trig,
845 bool state)
846 {
847 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
848 struct adxl372_state *st = iio_priv(indio_dev);
849 unsigned long int mask = 0;
850
851 if (state)
852 mask = ADXL372_INT1_MAP_FIFO_FULL_MSK;
853
854 return adxl372_set_interrupts(st, mask, 0);
855 }
856
857 static int adxl372_validate_trigger(struct iio_dev *indio_dev,
858 struct iio_trigger *trig)
859 {
860 struct adxl372_state *st = iio_priv(indio_dev);
861
862 if (st->dready_trig != trig)
863 return -EINVAL;
864
865 return 0;
866 }
867
868 static const struct iio_trigger_ops adxl372_trigger_ops = {
869 .validate_device = &iio_trigger_validate_own_device,
870 .set_trigger_state = adxl372_dready_trig_set_state,
871 };
872
873 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("400 800 1600 3200 6400");
874 static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
875 0444, adxl372_show_filter_freq_avail, NULL, 0);
876
877 static struct attribute *adxl372_attributes[] = {
878 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
879 &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
880 NULL,
881 };
882
883 static const struct attribute_group adxl372_attrs_group = {
884 .attrs = adxl372_attributes,
885 };
886
887 static const struct iio_info adxl372_info = {
888 .validate_trigger = &adxl372_validate_trigger,
889 .attrs = &adxl372_attrs_group,
890 .read_raw = adxl372_read_raw,
891 .write_raw = adxl372_write_raw,
892 .debugfs_reg_access = &adxl372_reg_access,
893 .hwfifo_set_watermark = adxl372_set_watermark,
894 };
895
896 bool adxl372_readable_noinc_reg(struct device *dev, unsigned int reg)
897 {
898 return (reg == ADXL372_FIFO_DATA);
899 }
900 EXPORT_SYMBOL_GPL(adxl372_readable_noinc_reg);
901
902 int adxl372_probe(struct device *dev, struct regmap *regmap,
903 int irq, const char *name)
904 {
905 struct iio_dev *indio_dev;
906 struct adxl372_state *st;
907 int ret;
908
909 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
910 if (!indio_dev)
911 return -ENOMEM;
912
913 st = iio_priv(indio_dev);
914 dev_set_drvdata(dev, indio_dev);
915
916 st->dev = dev;
917 st->regmap = regmap;
918 st->irq = irq;
919
920 indio_dev->channels = adxl372_channels;
921 indio_dev->num_channels = ARRAY_SIZE(adxl372_channels);
922 indio_dev->available_scan_masks = adxl372_channel_masks;
923 indio_dev->dev.parent = dev;
924 indio_dev->name = name;
925 indio_dev->info = &adxl372_info;
926 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
927
928 ret = adxl372_setup(st);
929 if (ret < 0) {
930 dev_err(dev, "ADXL372 setup failed\n");
931 return ret;
932 }
933
934 ret = devm_iio_triggered_buffer_setup(dev,
935 indio_dev, NULL,
936 adxl372_trigger_handler,
937 &adxl372_buffer_ops);
938 if (ret < 0)
939 return ret;
940
941 iio_buffer_set_attrs(indio_dev->buffer, adxl372_fifo_attributes);
942
943 if (st->irq) {
944 st->dready_trig = devm_iio_trigger_alloc(dev,
945 "%s-dev%d",
946 indio_dev->name,
947 indio_dev->id);
948 if (st->dready_trig == NULL)
949 return -ENOMEM;
950
951 st->dready_trig->ops = &adxl372_trigger_ops;
952 st->dready_trig->dev.parent = dev;
953 iio_trigger_set_drvdata(st->dready_trig, indio_dev);
954 ret = devm_iio_trigger_register(dev, st->dready_trig);
955 if (ret < 0)
956 return ret;
957
958 indio_dev->trig = iio_trigger_get(st->dready_trig);
959
960 ret = devm_request_threaded_irq(dev, st->irq,
961 iio_trigger_generic_data_rdy_poll,
962 NULL,
963 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
964 indio_dev->name, st->dready_trig);
965 if (ret < 0)
966 return ret;
967 }
968
969 return devm_iio_device_register(dev, indio_dev);
970 }
971 EXPORT_SYMBOL_GPL(adxl372_probe);
972
973 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
974 MODULE_DESCRIPTION("Analog Devices ADXL372 3-axis accelerometer driver");
975 MODULE_LICENSE("GPL");
Linux with added FPC-III support