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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / iio / adc / ad7793.c
blob4ac3ae62f56f98943b6c719179066e98c716319b
1 /*
2 * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver
3 *
4 * Copyright 2011-2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/trigger.h>
25 #include <linux/iio/trigger_consumer.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/iio/adc/ad_sigma_delta.h>
28 #include <linux/platform_data/ad7793.h>
29
30 /* Registers */
31 #define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */
32 #define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */
33 #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */
34 #define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */
35 #define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */
36 #define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */
37 #define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */
38 #define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit
39 * (AD7792)/24-bit (AD7793)) */
40 #define AD7793_REG_FULLSALE 7 /* Full-Scale Register
41 * (RW, 16-bit (AD7792)/24-bit (AD7793)) */
42
43 /* Communications Register Bit Designations (AD7793_REG_COMM) */
44 #define AD7793_COMM_WEN (1 << 7) /* Write Enable */
45 #define AD7793_COMM_WRITE (0 << 6) /* Write Operation */
46 #define AD7793_COMM_READ (1 << 6) /* Read Operation */
47 #define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
48 #define AD7793_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
49
50 /* Status Register Bit Designations (AD7793_REG_STAT) */
51 #define AD7793_STAT_RDY (1 << 7) /* Ready */
52 #define AD7793_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
53 #define AD7793_STAT_CH3 (1 << 2) /* Channel 3 */
54 #define AD7793_STAT_CH2 (1 << 1) /* Channel 2 */
55 #define AD7793_STAT_CH1 (1 << 0) /* Channel 1 */
56
57 /* Mode Register Bit Designations (AD7793_REG_MODE) */
58 #define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */
59 #define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */
60 #define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */
61 #define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */
62
63 #define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */
64 #define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */
65 #define AD7793_MODE_IDLE 2 /* Idle Mode */
66 #define AD7793_MODE_PWRDN 3 /* Power-Down Mode */
67 #define AD7793_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
68 #define AD7793_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
69 #define AD7793_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
70 #define AD7793_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
71
72 #define AD7793_CLK_INT 0 /* Internal 64 kHz Clock not
73 * available at the CLK pin */
74 #define AD7793_CLK_INT_CO 1 /* Internal 64 kHz Clock available
75 * at the CLK pin */
76 #define AD7793_CLK_EXT 2 /* External 64 kHz Clock */
77 #define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */
78
79 /* Configuration Register Bit Designations (AD7793_REG_CONF) */
80 #define AD7793_CONF_VBIAS(x) (((x) & 0x3) << 14) /* Bias Voltage
81 * Generator Enable */
82 #define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */
83 #define AD7793_CONF_UNIPOLAR (1 << 12) /* Unipolar/Bipolar Enable */
84 #define AD7793_CONF_BOOST (1 << 11) /* Boost Enable */
85 #define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */
86 #define AD7793_CONF_REFSEL(x) ((x) << 6) /* INT/EXT Reference Select */
87 #define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */
88 #define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */
89 #define AD7793_CONF_CHAN_MASK 0xf /* Channel select mask */
90
91 #define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */
92 #define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */
93 #define AD7793_CH_AIN3P_AIN3M 2 /* AIN3(+) - AIN3(-) */
94 #define AD7793_CH_AIN1M_AIN1M 3 /* AIN1(-) - AIN1(-) */
95 #define AD7793_CH_TEMP 6 /* Temp Sensor */
96 #define AD7793_CH_AVDD_MONITOR 7 /* AVDD Monitor */
97
98 #define AD7795_CH_AIN4P_AIN4M 4 /* AIN4(+) - AIN4(-) */
99 #define AD7795_CH_AIN5P_AIN5M 5 /* AIN5(+) - AIN5(-) */
100 #define AD7795_CH_AIN6P_AIN6M 6 /* AIN6(+) - AIN6(-) */
101 #define AD7795_CH_AIN1M_AIN1M 8 /* AIN1(-) - AIN1(-) */
102
103 /* ID Register Bit Designations (AD7793_REG_ID) */
104 #define AD7785_ID 0x3
105 #define AD7792_ID 0xA
106 #define AD7793_ID 0xB
107 #define AD7794_ID 0xF
108 #define AD7795_ID 0xF
109 #define AD7796_ID 0xA
110 #define AD7797_ID 0xB
111 #define AD7798_ID 0x8
112 #define AD7799_ID 0x9
113 #define AD7793_ID_MASK 0xF
114
115 /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */
116 #define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2 0 /* IEXC1 connect to IOUT1,
117 * IEXC2 connect to IOUT2 */
118 #define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1 1 /* IEXC1 connect to IOUT2,
119 * IEXC2 connect to IOUT1 */
120 #define AD7793_IO_IEXC1_IEXC2_IOUT1 2 /* Both current sources
121 * IEXC1,2 connect to IOUT1 */
122 #define AD7793_IO_IEXC1_IEXC2_IOUT2 3 /* Both current sources
123 * IEXC1,2 connect to IOUT2 */
124
125 #define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */
126 #define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */
127 #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */
128
129 /* NOTE:
130 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
131 * In order to avoid contentions on the SPI bus, it's therefore necessary
132 * to use spi bus locking.
133 *
134 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
135 */
136
137 #define AD7793_FLAG_HAS_CLKSEL BIT(0)
138 #define AD7793_FLAG_HAS_REFSEL BIT(1)
139 #define AD7793_FLAG_HAS_VBIAS BIT(2)
140 #define AD7793_HAS_EXITATION_CURRENT BIT(3)
141 #define AD7793_FLAG_HAS_GAIN BIT(4)
142 #define AD7793_FLAG_HAS_BUFFER BIT(5)
143
144 struct ad7793_chip_info {
145 unsigned int id;
146 const struct iio_chan_spec *channels;
147 unsigned int num_channels;
148 unsigned int flags;
149
150 const struct iio_info *iio_info;
151 const u16 *sample_freq_avail;
152 };
153
154 struct ad7793_state {
155 const struct ad7793_chip_info *chip_info;
156 struct regulator *reg;
157 u16 int_vref_mv;
158 u16 mode;
159 u16 conf;
160 u32 scale_avail[8][2];
161
162 struct ad_sigma_delta sd;
163
164 };
165
166 enum ad7793_supported_device_ids {
167 ID_AD7785,
168 ID_AD7792,
169 ID_AD7793,
170 ID_AD7794,
171 ID_AD7795,
172 ID_AD7796,
173 ID_AD7797,
174 ID_AD7798,
175 ID_AD7799,
176 };
177
178 static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd)
179 {
180 return container_of(sd, struct ad7793_state, sd);
181 }
182
183 static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
184 {
185 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
186
187 st->conf &= ~AD7793_CONF_CHAN_MASK;
188 st->conf |= AD7793_CONF_CHAN(channel);
189
190 return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
191 }
192
193 static int ad7793_set_mode(struct ad_sigma_delta *sd,
194 enum ad_sigma_delta_mode mode)
195 {
196 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
197
198 st->mode &= ~AD7793_MODE_SEL_MASK;
199 st->mode |= AD7793_MODE_SEL(mode);
200
201 return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
202 }
203
204 static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
205 .set_channel = ad7793_set_channel,
206 .set_mode = ad7793_set_mode,
207 .has_registers = true,
208 .addr_shift = 3,
209 .read_mask = BIT(6),
210 };
211
212 static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
213 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
214 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
215 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
216 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
217 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
218 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
219 };
220
221 static int ad7793_calibrate_all(struct ad7793_state *st)
222 {
223 return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
224 ARRAY_SIZE(ad7793_calib_arr));
225 }
226
227 static int ad7793_check_platform_data(struct ad7793_state *st,
228 const struct ad7793_platform_data *pdata)
229 {
230 if ((pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT1 ||
231 pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT2) &&
232 ((pdata->exitation_current != AD7793_IX_10uA) &&
233 (pdata->exitation_current != AD7793_IX_210uA)))
234 return -EINVAL;
235
236 if (!(st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) &&
237 pdata->clock_src != AD7793_CLK_SRC_INT)
238 return -EINVAL;
239
240 if (!(st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) &&
241 pdata->refsel != AD7793_REFSEL_REFIN1)
242 return -EINVAL;
243
244 if (!(st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) &&
245 pdata->bias_voltage != AD7793_BIAS_VOLTAGE_DISABLED)
246 return -EINVAL;
247
248 if (!(st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) &&
249 pdata->exitation_current != AD7793_IX_DISABLED)
250 return -EINVAL;
251
252 return 0;
253 }
254
255 static int ad7793_setup(struct iio_dev *indio_dev,
256 const struct ad7793_platform_data *pdata,
257 unsigned int vref_mv)
258 {
259 struct ad7793_state *st = iio_priv(indio_dev);
260 int i, ret;
261 unsigned long long scale_uv;
262 u32 id;
263
264 ret = ad7793_check_platform_data(st, pdata);
265 if (ret)
266 return ret;
267
268 /* reset the serial interface */
269 ret = ad_sd_reset(&st->sd, 32);
270 if (ret < 0)
271 goto out;
272 usleep_range(500, 2000); /* Wait for at least 500us */
273
274 /* write/read test for device presence */
275 ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
276 if (ret)
277 goto out;
278
279 id &= AD7793_ID_MASK;
280
281 if (id != st->chip_info->id) {
282 dev_err(&st->sd.spi->dev, "device ID query failed\n");
283 goto out;
284 }
285
286 st->mode = AD7793_MODE_RATE(1);
287 st->conf = 0;
288
289 if (st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL)
290 st->mode |= AD7793_MODE_CLKSRC(pdata->clock_src);
291 if (st->chip_info->flags & AD7793_FLAG_HAS_REFSEL)
292 st->conf |= AD7793_CONF_REFSEL(pdata->refsel);
293 if (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS)
294 st->conf |= AD7793_CONF_VBIAS(pdata->bias_voltage);
295 if (pdata->buffered || !(st->chip_info->flags & AD7793_FLAG_HAS_BUFFER))
296 st->conf |= AD7793_CONF_BUF;
297 if (pdata->boost_enable &&
298 (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS))
299 st->conf |= AD7793_CONF_BOOST;
300 if (pdata->burnout_current)
301 st->conf |= AD7793_CONF_BO_EN;
302 if (pdata->unipolar)
303 st->conf |= AD7793_CONF_UNIPOLAR;
304
305 if (!(st->chip_info->flags & AD7793_FLAG_HAS_GAIN))
306 st->conf |= AD7793_CONF_GAIN(7);
307
308 ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
309 if (ret)
310 goto out;
311
312 ret = ad7793_set_channel(&st->sd, 0);
313 if (ret)
314 goto out;
315
316 if (st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) {
317 ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO, 1,
318 pdata->exitation_current |
319 (pdata->current_source_direction << 2));
320 if (ret)
321 goto out;
322 }
323
324 ret = ad7793_calibrate_all(st);
325 if (ret)
326 goto out;
327
328 /* Populate available ADC input ranges */
329 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
330 scale_uv = ((u64)vref_mv * 100000000)
331 >> (st->chip_info->channels[0].scan_type.realbits -
332 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
333 scale_uv >>= i;
334
335 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
336 st->scale_avail[i][0] = scale_uv;
337 }
338
339 return 0;
340 out:
341 dev_err(&st->sd.spi->dev, "setup failed\n");
342 return ret;
343 }
344
345 static const u16 ad7793_sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39,
346 33, 19, 17, 16, 12, 10, 8, 6, 4};
347
348 static const u16 ad7797_sample_freq_avail[16] = {0, 0, 0, 123, 62, 50, 0,
349 33, 0, 17, 16, 12, 10, 8, 6, 4};
350
351 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
352 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
353
354 static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797,
355 sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4");
356
357 static ssize_t ad7793_show_scale_available(struct device *dev,
358 struct device_attribute *attr, char *buf)
359 {
360 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
361 struct ad7793_state *st = iio_priv(indio_dev);
362 int i, len = 0;
363
364 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
365 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
366 st->scale_avail[i][1]);
367
368 len += sprintf(buf + len, "\n");
369
370 return len;
371 }
372
373 static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available,
374 in_voltage-voltage_scale_available, S_IRUGO,
375 ad7793_show_scale_available, NULL, 0);
376
377 static struct attribute *ad7793_attributes[] = {
378 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
379 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
380 NULL
381 };
382
383 static const struct attribute_group ad7793_attribute_group = {
384 .attrs = ad7793_attributes,
385 };
386
387 static struct attribute *ad7797_attributes[] = {
388 &iio_const_attr_sampling_frequency_available_ad7797.dev_attr.attr,
389 NULL
390 };
391
392 static const struct attribute_group ad7797_attribute_group = {
393 .attrs = ad7797_attributes,
394 };
395
396 static int ad7793_read_raw(struct iio_dev *indio_dev,
397 struct iio_chan_spec const *chan,
398 int *val,
399 int *val2,
400 long m)
401 {
402 struct ad7793_state *st = iio_priv(indio_dev);
403 int ret;
404 unsigned long long scale_uv;
405 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
406
407 switch (m) {
408 case IIO_CHAN_INFO_RAW:
409 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
410 if (ret < 0)
411 return ret;
412
413 return IIO_VAL_INT;
414
415 case IIO_CHAN_INFO_SCALE:
416 switch (chan->type) {
417 case IIO_VOLTAGE:
418 if (chan->differential) {
419 *val = st->
420 scale_avail[(st->conf >> 8) & 0x7][0];
421 *val2 = st->
422 scale_avail[(st->conf >> 8) & 0x7][1];
423 return IIO_VAL_INT_PLUS_NANO;
424 }
425 /* 1170mV / 2^23 * 6 */
426 scale_uv = (1170ULL * 1000000000ULL * 6ULL);
427 break;
428 case IIO_TEMP:
429 /* 1170mV / 0.81 mV/C / 2^23 */
430 scale_uv = 1444444444444444ULL;
431 break;
432 default:
433 return -EINVAL;
434 }
435
436 scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
437 *val = 0;
438 *val2 = scale_uv;
439 return IIO_VAL_INT_PLUS_NANO;
440 case IIO_CHAN_INFO_OFFSET:
441 if (!unipolar)
442 *val = -(1 << (chan->scan_type.realbits - 1));
443 else
444 *val = 0;
445
446 /* Kelvin to Celsius */
447 if (chan->type == IIO_TEMP) {
448 unsigned long long offset;
449 unsigned int shift;
450
451 shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
452 offset = 273ULL << shift;
453 do_div(offset, 1444);
454 *val -= offset;
455 }
456 return IIO_VAL_INT;
457 case IIO_CHAN_INFO_SAMP_FREQ:
458 *val = st->chip_info
459 ->sample_freq_avail[AD7793_MODE_RATE(st->mode)];
460 return IIO_VAL_INT;
461 }
462 return -EINVAL;
463 }
464
465 static int ad7793_write_raw(struct iio_dev *indio_dev,
466 struct iio_chan_spec const *chan,
467 int val,
468 int val2,
469 long mask)
470 {
471 struct ad7793_state *st = iio_priv(indio_dev);
472 int ret, i;
473 unsigned int tmp;
474
475 ret = iio_device_claim_direct_mode(indio_dev);
476 if (ret)
477 return ret;
478
479 switch (mask) {
480 case IIO_CHAN_INFO_SCALE:
481 ret = -EINVAL;
482 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
483 if (val2 == st->scale_avail[i][1]) {
484 ret = 0;
485 tmp = st->conf;
486 st->conf &= ~AD7793_CONF_GAIN(-1);
487 st->conf |= AD7793_CONF_GAIN(i);
488
489 if (tmp == st->conf)
490 break;
491
492 ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
493 sizeof(st->conf), st->conf);
494 ad7793_calibrate_all(st);
495 break;
496 }
497 break;
498 case IIO_CHAN_INFO_SAMP_FREQ:
499 if (!val) {
500 ret = -EINVAL;
501 break;
502 }
503
504 for (i = 0; i < 16; i++)
505 if (val == st->chip_info->sample_freq_avail[i])
506 break;
507
508 if (i == 16) {
509 ret = -EINVAL;
510 break;
511 }
512
513 st->mode &= ~AD7793_MODE_RATE(-1);
514 st->mode |= AD7793_MODE_RATE(i);
515 ad_sd_write_reg(&st->sd, AD7793_REG_MODE, sizeof(st->mode),
516 st->mode);
517 break;
518 default:
519 ret = -EINVAL;
520 }
521
522 iio_device_release_direct_mode(indio_dev);
523 return ret;
524 }
525
526 static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
527 struct iio_chan_spec const *chan,
528 long mask)
529 {
530 return IIO_VAL_INT_PLUS_NANO;
531 }
532
533 static const struct iio_info ad7793_info = {
534 .read_raw = &ad7793_read_raw,
535 .write_raw = &ad7793_write_raw,
536 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
537 .attrs = &ad7793_attribute_group,
538 .validate_trigger = ad_sd_validate_trigger,
539 };
540
541 static const struct iio_info ad7797_info = {
542 .read_raw = &ad7793_read_raw,
543 .write_raw = &ad7793_write_raw,
544 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
545 .attrs = &ad7793_attribute_group,
546 .validate_trigger = ad_sd_validate_trigger,
547 };
548
549 #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
550 const struct iio_chan_spec _name##_channels[] = { \
551 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \
552 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \
553 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \
554 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \
555 AD_SD_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \
556 AD_SD_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \
557 IIO_CHAN_SOFT_TIMESTAMP(6), \
558 }
559
560 #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \
561 const struct iio_chan_spec _name##_channels[] = { \
562 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
563 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
564 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
565 AD_SD_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \
566 AD_SD_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \
567 AD_SD_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \
568 AD_SD_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
569 AD_SD_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \
570 AD_SD_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
571 IIO_CHAN_SOFT_TIMESTAMP(9), \
572 }
573
574 #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \
575 const struct iio_chan_spec _name##_channels[] = { \
576 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
577 AD_SD_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
578 AD_SD_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \
579 AD_SD_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
580 IIO_CHAN_SOFT_TIMESTAMP(4), \
581 }
582
583 #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \
584 const struct iio_chan_spec _name##_channels[] = { \
585 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
586 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
587 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
588 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
589 AD_SD_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
590 IIO_CHAN_SOFT_TIMESTAMP(5), \
591 }
592
593 static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4);
594 static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0);
595 static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0);
596 static DECLARE_AD7795_CHANNELS(ad7794, 16, 32);
597 static DECLARE_AD7795_CHANNELS(ad7795, 24, 32);
598 static DECLARE_AD7797_CHANNELS(ad7796, 16, 16);
599 static DECLARE_AD7797_CHANNELS(ad7797, 24, 32);
600 static DECLARE_AD7799_CHANNELS(ad7798, 16, 16);
601 static DECLARE_AD7799_CHANNELS(ad7799, 24, 32);
602
603 static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
604 [ID_AD7785] = {
605 .id = AD7785_ID,
606 .channels = ad7785_channels,
607 .num_channels = ARRAY_SIZE(ad7785_channels),
608 .iio_info = &ad7793_info,
609 .sample_freq_avail = ad7793_sample_freq_avail,
610 .flags = AD7793_FLAG_HAS_CLKSEL |
611 AD7793_FLAG_HAS_REFSEL |
612 AD7793_FLAG_HAS_VBIAS |
613 AD7793_HAS_EXITATION_CURRENT |
614 AD7793_FLAG_HAS_GAIN |
615 AD7793_FLAG_HAS_BUFFER,
616 },
617 [ID_AD7792] = {
618 .id = AD7792_ID,
619 .channels = ad7792_channels,
620 .num_channels = ARRAY_SIZE(ad7792_channels),
621 .iio_info = &ad7793_info,
622 .sample_freq_avail = ad7793_sample_freq_avail,
623 .flags = AD7793_FLAG_HAS_CLKSEL |
624 AD7793_FLAG_HAS_REFSEL |
625 AD7793_FLAG_HAS_VBIAS |
626 AD7793_HAS_EXITATION_CURRENT |
627 AD7793_FLAG_HAS_GAIN |
628 AD7793_FLAG_HAS_BUFFER,
629 },
630 [ID_AD7793] = {
631 .id = AD7793_ID,
632 .channels = ad7793_channels,
633 .num_channels = ARRAY_SIZE(ad7793_channels),
634 .iio_info = &ad7793_info,
635 .sample_freq_avail = ad7793_sample_freq_avail,
636 .flags = AD7793_FLAG_HAS_CLKSEL |
637 AD7793_FLAG_HAS_REFSEL |
638 AD7793_FLAG_HAS_VBIAS |
639 AD7793_HAS_EXITATION_CURRENT |
640 AD7793_FLAG_HAS_GAIN |
641 AD7793_FLAG_HAS_BUFFER,
642 },
643 [ID_AD7794] = {
644 .id = AD7794_ID,
645 .channels = ad7794_channels,
646 .num_channels = ARRAY_SIZE(ad7794_channels),
647 .iio_info = &ad7793_info,
648 .sample_freq_avail = ad7793_sample_freq_avail,
649 .flags = AD7793_FLAG_HAS_CLKSEL |
650 AD7793_FLAG_HAS_REFSEL |
651 AD7793_FLAG_HAS_VBIAS |
652 AD7793_HAS_EXITATION_CURRENT |
653 AD7793_FLAG_HAS_GAIN |
654 AD7793_FLAG_HAS_BUFFER,
655 },
656 [ID_AD7795] = {
657 .id = AD7795_ID,
658 .channels = ad7795_channels,
659 .num_channels = ARRAY_SIZE(ad7795_channels),
660 .iio_info = &ad7793_info,
661 .sample_freq_avail = ad7793_sample_freq_avail,
662 .flags = AD7793_FLAG_HAS_CLKSEL |
663 AD7793_FLAG_HAS_REFSEL |
664 AD7793_FLAG_HAS_VBIAS |
665 AD7793_HAS_EXITATION_CURRENT |
666 AD7793_FLAG_HAS_GAIN |
667 AD7793_FLAG_HAS_BUFFER,
668 },
669 [ID_AD7796] = {
670 .id = AD7796_ID,
671 .channels = ad7796_channels,
672 .num_channels = ARRAY_SIZE(ad7796_channels),
673 .iio_info = &ad7797_info,
674 .sample_freq_avail = ad7797_sample_freq_avail,
675 .flags = AD7793_FLAG_HAS_CLKSEL,
676 },
677 [ID_AD7797] = {
678 .id = AD7797_ID,
679 .channels = ad7797_channels,
680 .num_channels = ARRAY_SIZE(ad7797_channels),
681 .iio_info = &ad7797_info,
682 .sample_freq_avail = ad7797_sample_freq_avail,
683 .flags = AD7793_FLAG_HAS_CLKSEL,
684 },
685 [ID_AD7798] = {
686 .id = AD7798_ID,
687 .channels = ad7798_channels,
688 .num_channels = ARRAY_SIZE(ad7798_channels),
689 .iio_info = &ad7793_info,
690 .sample_freq_avail = ad7793_sample_freq_avail,
691 .flags = AD7793_FLAG_HAS_GAIN |
692 AD7793_FLAG_HAS_BUFFER,
693 },
694 [ID_AD7799] = {
695 .id = AD7799_ID,
696 .channels = ad7799_channels,
697 .num_channels = ARRAY_SIZE(ad7799_channels),
698 .iio_info = &ad7793_info,
699 .sample_freq_avail = ad7793_sample_freq_avail,
700 .flags = AD7793_FLAG_HAS_GAIN |
701 AD7793_FLAG_HAS_BUFFER,
702 },
703 };
704
705 static int ad7793_probe(struct spi_device *spi)
706 {
707 const struct ad7793_platform_data *pdata = spi->dev.platform_data;
708 struct ad7793_state *st;
709 struct iio_dev *indio_dev;
710 int ret, vref_mv = 0;
711
712 if (!pdata) {
713 dev_err(&spi->dev, "no platform data?\n");
714 return -ENODEV;
715 }
716
717 if (!spi->irq) {
718 dev_err(&spi->dev, "no IRQ?\n");
719 return -ENODEV;
720 }
721
722 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
723 if (indio_dev == NULL)
724 return -ENOMEM;
725
726 st = iio_priv(indio_dev);
727
728 ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);
729
730 if (pdata->refsel != AD7793_REFSEL_INTERNAL) {
731 st->reg = devm_regulator_get(&spi->dev, "refin");
732 if (IS_ERR(st->reg))
733 return PTR_ERR(st->reg);
734
735 ret = regulator_enable(st->reg);
736 if (ret)
737 return ret;
738
739 vref_mv = regulator_get_voltage(st->reg);
740 if (vref_mv < 0) {
741 ret = vref_mv;
742 goto error_disable_reg;
743 }
744
745 vref_mv /= 1000;
746 } else {
747 vref_mv = 1170; /* Build-in ref */
748 }
749
750 st->chip_info =
751 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
752
753 spi_set_drvdata(spi, indio_dev);
754
755 indio_dev->dev.parent = &spi->dev;
756 indio_dev->dev.of_node = spi->dev.of_node;
757 indio_dev->name = spi_get_device_id(spi)->name;
758 indio_dev->modes = INDIO_DIRECT_MODE;
759 indio_dev->channels = st->chip_info->channels;
760 indio_dev->num_channels = st->chip_info->num_channels;
761 indio_dev->info = st->chip_info->iio_info;
762
763 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
764 if (ret)
765 goto error_disable_reg;
766
767 ret = ad7793_setup(indio_dev, pdata, vref_mv);
768 if (ret)
769 goto error_remove_trigger;
770
771 ret = iio_device_register(indio_dev);
772 if (ret)
773 goto error_remove_trigger;
774
775 return 0;
776
777 error_remove_trigger:
778 ad_sd_cleanup_buffer_and_trigger(indio_dev);
779 error_disable_reg:
780 if (pdata->refsel != AD7793_REFSEL_INTERNAL)
781 regulator_disable(st->reg);
782
783 return ret;
784 }
785
786 static int ad7793_remove(struct spi_device *spi)
787 {
788 const struct ad7793_platform_data *pdata = spi->dev.platform_data;
789 struct iio_dev *indio_dev = spi_get_drvdata(spi);
790 struct ad7793_state *st = iio_priv(indio_dev);
791
792 iio_device_unregister(indio_dev);
793 ad_sd_cleanup_buffer_and_trigger(indio_dev);
794
795 if (pdata->refsel != AD7793_REFSEL_INTERNAL)
796 regulator_disable(st->reg);
797
798 return 0;
799 }
800
801 static const struct spi_device_id ad7793_id[] = {
802 {"ad7785", ID_AD7785},
803 {"ad7792", ID_AD7792},
804 {"ad7793", ID_AD7793},
805 {"ad7794", ID_AD7794},
806 {"ad7795", ID_AD7795},
807 {"ad7796", ID_AD7796},
808 {"ad7797", ID_AD7797},
809 {"ad7798", ID_AD7798},
810 {"ad7799", ID_AD7799},
811 {}
812 };
813 MODULE_DEVICE_TABLE(spi, ad7793_id);
814
815 static struct spi_driver ad7793_driver = {
816 .driver = {
817 .name = "ad7793",
818 },
819 .probe = ad7793_probe,
820 .remove = ad7793_remove,
821 .id_table = ad7793_id,
822 };
823 module_spi_driver(ad7793_driver);
824
825 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
826 MODULE_DESCRIPTION("Analog Devices AD7793 and similar ADCs");
827 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support