drivers/iio/adc/ep93xx_adc.c

   1 /*
   2  * Driver for ADC module on the Cirrus Logic EP93xx series of SoCs
   3  *
   4  * Copyright (C) 2015 Alexander Sverdlin
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * The driver uses polling to get the conversion status. According to EP93xx
  11  * datasheets, reading ADCResult register starts the conversion, but user is also
  12  * responsible for ensuring that delay between adjacent conversion triggers is
  13  * long enough so that maximum allowed conversion rate is not exceeded. This
  14  * basically renders IRQ mode unusable.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <linux/err.h>
  21 #include <linux/iio/iio.h>
  22 #include <linux/io.h>
  23 #include <linux/irqflags.h>
  24 #include <linux/module.h>
  25 #include <linux/mutex.h>
  26 #include <linux/platform_device.h>
  27
  28 /*
  29  * This code could benefit from real HR Timers, but jiffy granularity would
  30  * lower ADC conversion rate down to CONFIG_HZ, so we fallback to busy wait
  31  * in such case.
  32  *
  33  * HR Timers-based version loads CPU only up to 10% during back to back ADC
  34  * conversion, while busy wait-based version consumes whole CPU power.
  35  */
  36 #ifdef CONFIG_HIGH_RES_TIMERS
  37 #define ep93xx_adc_delay(usmin, usmax) usleep_range(usmin, usmax)
  38 #else
  39 #define ep93xx_adc_delay(usmin, usmax) udelay(usmin)
  40 #endif
  41
  42 #define EP93XX_ADC_RESULT       0x08
  43 #define   EP93XX_ADC_SDR        BIT(31)
  44 #define EP93XX_ADC_SWITCH       0x18
  45 #define EP93XX_ADC_SW_LOCK      0x20
  46
  47 struct ep93xx_adc_priv {
  48         struct clk *clk;
  49         void __iomem *base;
  50         int lastch;
  51         struct mutex lock;
  52 };
  53
  54 #define EP93XX_ADC_CH(index, dname, swcfg) {                    \
  55         .type = IIO_VOLTAGE,                                    \
  56         .indexed = 1,                                           \
  57         .channel = index,                                       \
  58         .address = swcfg,                                       \
  59         .datasheet_name = dname,                                \
  60         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
  61         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) |   \
  62                                    BIT(IIO_CHAN_INFO_OFFSET),   \
  63 }
  64
  65 /*
  66  * Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets.
  67  * EP9307, EP9312 and EP9312 have 3 channels more (total 8), but the numbering is
  68  * not defined. So the last three are numbered randomly, let's say.
  69  */
  70 static const struct iio_chan_spec ep93xx_adc_channels[8] = {
  71         EP93XX_ADC_CH(0, "YM",  0x608),
  72         EP93XX_ADC_CH(1, "SXP", 0x680),
  73         EP93XX_ADC_CH(2, "SXM", 0x640),
  74         EP93XX_ADC_CH(3, "SYP", 0x620),
  75         EP93XX_ADC_CH(4, "SYM", 0x610),
  76         EP93XX_ADC_CH(5, "XP",  0x601),
  77         EP93XX_ADC_CH(6, "XM",  0x602),
  78         EP93XX_ADC_CH(7, "YP",  0x604),
  79 };
  80
  81 static int ep93xx_read_raw(struct iio_dev *iiodev,
  82                            struct iio_chan_spec const *channel, int *value,
  83                            int *shift, long mask)
  84 {
  85         struct ep93xx_adc_priv *priv = iio_priv(iiodev);
  86         unsigned long timeout;
  87         int ret;
  88
  89         switch (mask) {
  90         case IIO_CHAN_INFO_RAW:
  91                 mutex_lock(&priv->lock);
  92                 if (priv->lastch != channel->channel) {
  93                         priv->lastch = channel->channel;
  94                         /*
  95                          * Switch register is software-locked, unlocking must be
  96                          * immediately followed by write
  97                          */
  98                         local_irq_disable();
  99                         writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK);
 100                         writel_relaxed(channel->address,
 101                                        priv->base + EP93XX_ADC_SWITCH);
 102                         local_irq_enable();
 103                         /*
 104                          * Settling delay depends on module clock and could be
 105                          * 2ms or 500us
 106                          */
 107                         ep93xx_adc_delay(2000, 2000);
 108                 }
 109                 /* Start the conversion, eventually discarding old result */
 110                 readl_relaxed(priv->base + EP93XX_ADC_RESULT);
 111                 /* Ensure maximum conversion rate is not exceeded */
 112                 ep93xx_adc_delay(DIV_ROUND_UP(1000000, 925),
 113                                  DIV_ROUND_UP(1000000, 925));
 114                 /* At this point conversion must be completed, but anyway... */
 115                 ret = IIO_VAL_INT;
 116                 timeout = jiffies + msecs_to_jiffies(1) + 1;
 117                 while (1) {
 118                         u32 t;
 119
 120                         t = readl_relaxed(priv->base + EP93XX_ADC_RESULT);
 121                         if (t & EP93XX_ADC_SDR) {
 122                                 *value = sign_extend32(t, 15);
 123                                 break;
 124                         }
 125
 126                         if (time_after(jiffies, timeout)) {
 127                                 dev_err(&iiodev->dev, "Conversion timeout\n");
 128                                 ret = -ETIMEDOUT;
 129                                 break;
 130                         }
 131
 132                         cpu_relax();
 133                 }
 134                 mutex_unlock(&priv->lock);
 135                 return ret;
 136
 137         case IIO_CHAN_INFO_OFFSET:
 138                 /* According to datasheet, range is -25000..25000 */
 139                 *value = 25000;
 140                 return IIO_VAL_INT;
 141
 142         case IIO_CHAN_INFO_SCALE:
 143                 /* Typical supply voltage is 3.3v */
 144                 *value = (1ULL << 32) * 3300 / 50000;
 145                 *shift = 32;
 146                 return IIO_VAL_FRACTIONAL_LOG2;
 147         }
 148
 149         return -EINVAL;
 150 }
 151
 152 static const struct iio_info ep93xx_adc_info = {
 153         .read_raw = ep93xx_read_raw,
 154 };
 155
 156 static int ep93xx_adc_probe(struct platform_device *pdev)
 157 {
 158         int ret;
 159         struct iio_dev *iiodev;
 160         struct ep93xx_adc_priv *priv;
 161         struct clk *pclk;
 162         struct resource *res;
 163
 164         iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
 165         if (!iiodev)
 166                 return -ENOMEM;
 167         priv = iio_priv(iiodev);
 168
 169         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 170         priv->base = devm_ioremap_resource(&pdev->dev, res);
 171         if (IS_ERR(priv->base)) {
 172                 dev_err(&pdev->dev, "Cannot map memory resource\n");
 173                 return PTR_ERR(priv->base);
 174         }
 175
 176         iiodev->dev.parent = &pdev->dev;
 177         iiodev->name = dev_name(&pdev->dev);
 178         iiodev->modes = INDIO_DIRECT_MODE;
 179         iiodev->info = &ep93xx_adc_info;
 180         iiodev->num_channels = ARRAY_SIZE(ep93xx_adc_channels);
 181         iiodev->channels = ep93xx_adc_channels;
 182
 183         priv->lastch = -1;
 184         mutex_init(&priv->lock);
 185
 186         platform_set_drvdata(pdev, iiodev);
 187
 188         priv->clk = devm_clk_get(&pdev->dev, NULL);
 189         if (IS_ERR(priv->clk)) {
 190                 dev_err(&pdev->dev, "Cannot obtain clock\n");
 191                 return PTR_ERR(priv->clk);
 192         }
 193
 194         pclk = clk_get_parent(priv->clk);
 195         if (!pclk) {
 196                 dev_warn(&pdev->dev, "Cannot obtain parent clock\n");
 197         } else {
 198                 /*
 199                  * This is actually a place for improvement:
 200                  * EP93xx ADC supports two clock divisors -- 4 and 16,
 201                  * resulting in conversion rates 3750 and 925 samples per second
 202                  * with 500us or 2ms settling time respectively.
 203                  * One might find this interesting enough to be configurable.
 204                  */
 205                 ret = clk_set_rate(priv->clk, clk_get_rate(pclk) / 16);
 206                 if (ret)
 207                         dev_warn(&pdev->dev, "Cannot set clock rate\n");
 208                 /*
 209                  * We can tolerate rate setting failure because the module should
 210                  * work in any case.
 211                  */
 212         }
 213
 214         ret = clk_enable(priv->clk);
 215         if (ret) {
 216                 dev_err(&pdev->dev, "Cannot enable clock\n");
 217                 return ret;
 218         }
 219
 220         ret = iio_device_register(iiodev);
 221         if (ret)
 222                 clk_disable(priv->clk);
 223
 224         return ret;
 225 }
 226
 227 static int ep93xx_adc_remove(struct platform_device *pdev)
 228 {
 229         struct iio_dev *iiodev = platform_get_drvdata(pdev);
 230         struct ep93xx_adc_priv *priv = iio_priv(iiodev);
 231
 232         iio_device_unregister(iiodev);
 233         clk_disable(priv->clk);
 234
 235         return 0;
 236 }
 237
 238 static struct platform_driver ep93xx_adc_driver = {
 239         .driver = {
 240                 .name = "ep93xx-adc",
 241         },
 242         .probe = ep93xx_adc_probe,
 243         .remove = ep93xx_adc_remove,
 244 };
 245 module_platform_driver(ep93xx_adc_driver);
 246
 247 MODULE_AUTHOR("Alexander Sverdlin <alexander.sverdlin@gmail.com>");
 248 MODULE_DESCRIPTION("Cirrus Logic EP93XX ADC driver");
 249 MODULE_LICENSE("GPL");
 250 MODULE_ALIAS("platform:ep93xx-adc");