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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / iio / adc / mcp320x.c
bloba04856d8afdb89481870dfce6ce7da60302e6b41
1 /*
2 * Copyright (C) 2013 Oskar Andero <oskar.andero@gmail.com>
3 * Copyright (C) 2014 Rose Technology
4 * Allan Bendorff Jensen <abj@rosetechnology.dk>
5 * Soren Andersen <san@rosetechnology.dk>
6 *
7 * Driver for following ADC chips from Microchip Technology's:
8 * 10 Bit converter
9 * MCP3001
10 * MCP3002
11 * MCP3004
12 * MCP3008
13 * ------------
14 * 12 bit converter
15 * MCP3201
16 * MCP3202
17 * MCP3204
18 * MCP3208
19 * ------------
20 * 13 bit converter
21 * MCP3301
22 * ------------
23 * 22 bit converter
24 * MCP3550
25 * MCP3551
26 * MCP3553
27 *
28 * Datasheet can be found here:
29 * http://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001
30 * http://ww1.microchip.com/downloads/en/DeviceDoc/21294E.pdf mcp3002
31 * http://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf mcp3004/08
32 * http://ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf mcp3201
33 * http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202
34 * http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08
35 * http://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301
36 * http://ww1.microchip.com/downloads/en/DeviceDoc/21950D.pdf mcp3550/1/3
37 *
38 * This program is free software; you can redistribute it and/or modify
39 * it under the terms of the GNU General Public License version 2 as
40 * published by the Free Software Foundation.
41 */
42
43 #include <linux/err.h>
44 #include <linux/delay.h>
45 #include <linux/spi/spi.h>
46 #include <linux/module.h>
47 #include <linux/iio/iio.h>
48 #include <linux/regulator/consumer.h>
49
50 enum {
51 mcp3001,
52 mcp3002,
53 mcp3004,
54 mcp3008,
55 mcp3201,
56 mcp3202,
57 mcp3204,
58 mcp3208,
59 mcp3301,
60 mcp3550_50,
61 mcp3550_60,
62 mcp3551,
63 mcp3553,
64 };
65
66 struct mcp320x_chip_info {
67 const struct iio_chan_spec *channels;
68 unsigned int num_channels;
69 unsigned int resolution;
70 unsigned int conv_time; /* usec */
71 };
72
73 /**
74 * struct mcp320x - Microchip SPI ADC instance
75 * @spi: SPI slave (parent of the IIO device)
76 * @msg: SPI message to select a channel and receive a value from the ADC
77 * @transfer: SPI transfers used by @msg
78 * @start_conv_msg: SPI message to start a conversion by briefly asserting CS
79 * @start_conv_transfer: SPI transfer used by @start_conv_msg
80 * @reg: regulator generating Vref
81 * @lock: protects read sequences
82 * @chip_info: ADC properties
83 * @tx_buf: buffer for @transfer[0] (not used on single-channel converters)
84 * @rx_buf: buffer for @transfer[1]
85 */
86 struct mcp320x {
87 struct spi_device *spi;
88 struct spi_message msg;
89 struct spi_transfer transfer[2];
90 struct spi_message start_conv_msg;
91 struct spi_transfer start_conv_transfer;
92
93 struct regulator *reg;
94 struct mutex lock;
95 const struct mcp320x_chip_info *chip_info;
96
97 u8 tx_buf ____cacheline_aligned;
98 u8 rx_buf[4];
99 };
100
101 static int mcp320x_channel_to_tx_data(int device_index,
102 const unsigned int channel, bool differential)
103 {
104 int start_bit = 1;
105
106 switch (device_index) {
107 case mcp3002:
108 case mcp3202:
109 return ((start_bit << 4) | (!differential << 3) |
110 (channel << 2));
111 case mcp3004:
112 case mcp3204:
113 case mcp3008:
114 case mcp3208:
115 return ((start_bit << 6) | (!differential << 5) |
116 (channel << 2));
117 default:
118 return -EINVAL;
119 }
120 }
121
122 static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel,
123 bool differential, int device_index, int *val)
124 {
125 int ret;
126
127 if (adc->chip_info->conv_time) {
128 ret = spi_sync(adc->spi, &adc->start_conv_msg);
129 if (ret < 0)
130 return ret;
131
132 usleep_range(adc->chip_info->conv_time,
133 adc->chip_info->conv_time + 100);
134 }
135
136 memset(&adc->rx_buf, 0, sizeof(adc->rx_buf));
137 if (adc->chip_info->num_channels > 1)
138 adc->tx_buf = mcp320x_channel_to_tx_data(device_index, channel,
139 differential);
140
141 ret = spi_sync(adc->spi, &adc->msg);
142 if (ret < 0)
143 return ret;
144
145 switch (device_index) {
146 case mcp3001:
147 *val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3);
148 return 0;
149 case mcp3002:
150 case mcp3004:
151 case mcp3008:
152 *val = (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6);
153 return 0;
154 case mcp3201:
155 *val = (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1);
156 return 0;
157 case mcp3202:
158 case mcp3204:
159 case mcp3208:
160 *val = (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4);
161 return 0;
162 case mcp3301:
163 *val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8
164 | adc->rx_buf[1], 12);
165 return 0;
166 case mcp3550_50:
167 case mcp3550_60:
168 case mcp3551:
169 case mcp3553: {
170 u32 raw = be32_to_cpup((u32 *)adc->rx_buf);
171
172 if (!(adc->spi->mode & SPI_CPOL))
173 raw <<= 1; /* strip Data Ready bit in SPI mode 0,0 */
174
175 /*
176 * If the input is within -vref and vref, bit 21 is the sign.
177 * Up to 12% overrange or underrange are allowed, in which case
178 * bit 23 is the sign and bit 0 to 21 is the value.
179 */
180 raw >>= 8;
181 if (raw & BIT(22) && raw & BIT(23))
182 return -EIO; /* cannot have overrange AND underrange */
183 else if (raw & BIT(22))
184 raw &= ~BIT(22); /* overrange */
185 else if (raw & BIT(23) || raw & BIT(21))
186 raw |= GENMASK(31, 22); /* underrange or negative */
187
188 *val = (s32)raw;
189 return 0;
190 }
191 default:
192 return -EINVAL;
193 }
194 }
195
196 static int mcp320x_read_raw(struct iio_dev *indio_dev,
197 struct iio_chan_spec const *channel, int *val,
198 int *val2, long mask)
199 {
200 struct mcp320x *adc = iio_priv(indio_dev);
201 int ret = -EINVAL;
202 int device_index = 0;
203
204 mutex_lock(&adc->lock);
205
206 device_index = spi_get_device_id(adc->spi)->driver_data;
207
208 switch (mask) {
209 case IIO_CHAN_INFO_RAW:
210 ret = mcp320x_adc_conversion(adc, channel->address,
211 channel->differential, device_index, val);
212 if (ret < 0)
213 goto out;
214
215 ret = IIO_VAL_INT;
216 break;
217
218 case IIO_CHAN_INFO_SCALE:
219 ret = regulator_get_voltage(adc->reg);
220 if (ret < 0)
221 goto out;
222
223 /* convert regulator output voltage to mV */
224 *val = ret / 1000;
225 *val2 = adc->chip_info->resolution;
226 ret = IIO_VAL_FRACTIONAL_LOG2;
227 break;
228 }
229
230 out:
231 mutex_unlock(&adc->lock);
232
233 return ret;
234 }
235
236 #define MCP320X_VOLTAGE_CHANNEL(num) \
237 { \
238 .type = IIO_VOLTAGE, \
239 .indexed = 1, \
240 .channel = (num), \
241 .address = (num), \
242 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
243 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
244 }
245
246 #define MCP320X_VOLTAGE_CHANNEL_DIFF(chan1, chan2) \
247 { \
248 .type = IIO_VOLTAGE, \
249 .indexed = 1, \
250 .channel = (chan1), \
251 .channel2 = (chan2), \
252 .address = (chan1), \
253 .differential = 1, \
254 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
255 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
256 }
257
258 static const struct iio_chan_spec mcp3201_channels[] = {
259 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
260 };
261
262 static const struct iio_chan_spec mcp3202_channels[] = {
263 MCP320X_VOLTAGE_CHANNEL(0),
264 MCP320X_VOLTAGE_CHANNEL(1),
265 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
266 MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
267 };
268
269 static const struct iio_chan_spec mcp3204_channels[] = {
270 MCP320X_VOLTAGE_CHANNEL(0),
271 MCP320X_VOLTAGE_CHANNEL(1),
272 MCP320X_VOLTAGE_CHANNEL(2),
273 MCP320X_VOLTAGE_CHANNEL(3),
274 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
275 MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
276 MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
277 MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
278 };
279
280 static const struct iio_chan_spec mcp3208_channels[] = {
281 MCP320X_VOLTAGE_CHANNEL(0),
282 MCP320X_VOLTAGE_CHANNEL(1),
283 MCP320X_VOLTAGE_CHANNEL(2),
284 MCP320X_VOLTAGE_CHANNEL(3),
285 MCP320X_VOLTAGE_CHANNEL(4),
286 MCP320X_VOLTAGE_CHANNEL(5),
287 MCP320X_VOLTAGE_CHANNEL(6),
288 MCP320X_VOLTAGE_CHANNEL(7),
289 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
290 MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
291 MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
292 MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
293 MCP320X_VOLTAGE_CHANNEL_DIFF(4, 5),
294 MCP320X_VOLTAGE_CHANNEL_DIFF(5, 4),
295 MCP320X_VOLTAGE_CHANNEL_DIFF(6, 7),
296 MCP320X_VOLTAGE_CHANNEL_DIFF(7, 6),
297 };
298
299 static const struct iio_info mcp320x_info = {
300 .read_raw = mcp320x_read_raw,
301 };
302
303 static const struct mcp320x_chip_info mcp320x_chip_infos[] = {
304 [mcp3001] = {
305 .channels = mcp3201_channels,
306 .num_channels = ARRAY_SIZE(mcp3201_channels),
307 .resolution = 10
308 },
309 [mcp3002] = {
310 .channels = mcp3202_channels,
311 .num_channels = ARRAY_SIZE(mcp3202_channels),
312 .resolution = 10
313 },
314 [mcp3004] = {
315 .channels = mcp3204_channels,
316 .num_channels = ARRAY_SIZE(mcp3204_channels),
317 .resolution = 10
318 },
319 [mcp3008] = {
320 .channels = mcp3208_channels,
321 .num_channels = ARRAY_SIZE(mcp3208_channels),
322 .resolution = 10
323 },
324 [mcp3201] = {
325 .channels = mcp3201_channels,
326 .num_channels = ARRAY_SIZE(mcp3201_channels),
327 .resolution = 12
328 },
329 [mcp3202] = {
330 .channels = mcp3202_channels,
331 .num_channels = ARRAY_SIZE(mcp3202_channels),
332 .resolution = 12
333 },
334 [mcp3204] = {
335 .channels = mcp3204_channels,
336 .num_channels = ARRAY_SIZE(mcp3204_channels),
337 .resolution = 12
338 },
339 [mcp3208] = {
340 .channels = mcp3208_channels,
341 .num_channels = ARRAY_SIZE(mcp3208_channels),
342 .resolution = 12
343 },
344 [mcp3301] = {
345 .channels = mcp3201_channels,
346 .num_channels = ARRAY_SIZE(mcp3201_channels),
347 .resolution = 13
348 },
349 [mcp3550_50] = {
350 .channels = mcp3201_channels,
351 .num_channels = ARRAY_SIZE(mcp3201_channels),
352 .resolution = 21,
353 /* 2% max deviation + 144 clock periods to exit shutdown */
354 .conv_time = 80000 * 1.02 + 144000 / 102.4,
355 },
356 [mcp3550_60] = {
357 .channels = mcp3201_channels,
358 .num_channels = ARRAY_SIZE(mcp3201_channels),
359 .resolution = 21,
360 .conv_time = 66670 * 1.02 + 144000 / 122.88,
361 },
362 [mcp3551] = {
363 .channels = mcp3201_channels,
364 .num_channels = ARRAY_SIZE(mcp3201_channels),
365 .resolution = 21,
366 .conv_time = 73100 * 1.02 + 144000 / 112.64,
367 },
368 [mcp3553] = {
369 .channels = mcp3201_channels,
370 .num_channels = ARRAY_SIZE(mcp3201_channels),
371 .resolution = 21,
372 .conv_time = 16670 * 1.02 + 144000 / 122.88,
373 },
374 };
375
376 static int mcp320x_probe(struct spi_device *spi)
377 {
378 struct iio_dev *indio_dev;
379 struct mcp320x *adc;
380 const struct mcp320x_chip_info *chip_info;
381 int ret, device_index;
382
383 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
384 if (!indio_dev)
385 return -ENOMEM;
386
387 adc = iio_priv(indio_dev);
388 adc->spi = spi;
389
390 indio_dev->dev.parent = &spi->dev;
391 indio_dev->dev.of_node = spi->dev.of_node;
392 indio_dev->name = spi_get_device_id(spi)->name;
393 indio_dev->modes = INDIO_DIRECT_MODE;
394 indio_dev->info = &mcp320x_info;
395 spi_set_drvdata(spi, indio_dev);
396
397 device_index = spi_get_device_id(spi)->driver_data;
398 chip_info = &mcp320x_chip_infos[device_index];
399 indio_dev->channels = chip_info->channels;
400 indio_dev->num_channels = chip_info->num_channels;
401
402 adc->chip_info = chip_info;
403
404 adc->transfer[0].tx_buf = &adc->tx_buf;
405 adc->transfer[0].len = sizeof(adc->tx_buf);
406 adc->transfer[1].rx_buf = adc->rx_buf;
407 adc->transfer[1].len = DIV_ROUND_UP(chip_info->resolution, 8);
408
409 if (chip_info->num_channels == 1)
410 /* single-channel converters are rx only (no MOSI pin) */
411 spi_message_init_with_transfers(&adc->msg,
412 &adc->transfer[1], 1);
413 else
414 spi_message_init_with_transfers(&adc->msg, adc->transfer,
415 ARRAY_SIZE(adc->transfer));
416
417 switch (device_index) {
418 case mcp3550_50:
419 case mcp3550_60:
420 case mcp3551:
421 case mcp3553:
422 /* rx len increases from 24 to 25 bit in SPI mode 0,0 */
423 if (!(spi->mode & SPI_CPOL))
424 adc->transfer[1].len++;
425
426 /* conversions are started by asserting CS pin for 8 usec */
427 adc->start_conv_transfer.delay_usecs = 8;
428 spi_message_init_with_transfers(&adc->start_conv_msg,
429 &adc->start_conv_transfer, 1);
430
431 /*
432 * If CS was previously kept low (continuous conversion mode)
433 * and then changed to high, the chip is in shutdown.
434 * Sometimes it fails to wake from shutdown and clocks out
435 * only 0xffffff. The magic sequence of performing two
436 * conversions without delay between them resets the chip
437 * and ensures all subsequent conversions succeed.
438 */
439 mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
440 mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
441 }
442
443 adc->reg = devm_regulator_get(&spi->dev, "vref");
444 if (IS_ERR(adc->reg))
445 return PTR_ERR(adc->reg);
446
447 ret = regulator_enable(adc->reg);
448 if (ret < 0)
449 return ret;
450
451 mutex_init(&adc->lock);
452
453 ret = iio_device_register(indio_dev);
454 if (ret < 0)
455 goto reg_disable;
456
457 return 0;
458
459 reg_disable:
460 regulator_disable(adc->reg);
461
462 return ret;
463 }
464
465 static int mcp320x_remove(struct spi_device *spi)
466 {
467 struct iio_dev *indio_dev = spi_get_drvdata(spi);
468 struct mcp320x *adc = iio_priv(indio_dev);
469
470 iio_device_unregister(indio_dev);
471 regulator_disable(adc->reg);
472
473 return 0;
474 }
475
476 #if defined(CONFIG_OF)
477 static const struct of_device_id mcp320x_dt_ids[] = {
478 /* NOTE: The use of compatibles with no vendor prefix is deprecated. */
479 { .compatible = "mcp3001" },
480 { .compatible = "mcp3002" },
481 { .compatible = "mcp3004" },
482 { .compatible = "mcp3008" },
483 { .compatible = "mcp3201" },
484 { .compatible = "mcp3202" },
485 { .compatible = "mcp3204" },
486 { .compatible = "mcp3208" },
487 { .compatible = "mcp3301" },
488 { .compatible = "microchip,mcp3001" },
489 { .compatible = "microchip,mcp3002" },
490 { .compatible = "microchip,mcp3004" },
491 { .compatible = "microchip,mcp3008" },
492 { .compatible = "microchip,mcp3201" },
493 { .compatible = "microchip,mcp3202" },
494 { .compatible = "microchip,mcp3204" },
495 { .compatible = "microchip,mcp3208" },
496 { .compatible = "microchip,mcp3301" },
497 { .compatible = "microchip,mcp3550-50" },
498 { .compatible = "microchip,mcp3550-60" },
499 { .compatible = "microchip,mcp3551" },
500 { .compatible = "microchip,mcp3553" },
501 { }
502 };
503 MODULE_DEVICE_TABLE(of, mcp320x_dt_ids);
504 #endif
505
506 static const struct spi_device_id mcp320x_id[] = {
507 { "mcp3001", mcp3001 },
508 { "mcp3002", mcp3002 },
509 { "mcp3004", mcp3004 },
510 { "mcp3008", mcp3008 },
511 { "mcp3201", mcp3201 },
512 { "mcp3202", mcp3202 },
513 { "mcp3204", mcp3204 },
514 { "mcp3208", mcp3208 },
515 { "mcp3301", mcp3301 },
516 { "mcp3550-50", mcp3550_50 },
517 { "mcp3550-60", mcp3550_60 },
518 { "mcp3551", mcp3551 },
519 { "mcp3553", mcp3553 },
520 { }
521 };
522 MODULE_DEVICE_TABLE(spi, mcp320x_id);
523
524 static struct spi_driver mcp320x_driver = {
525 .driver = {
526 .name = "mcp320x",
527 .of_match_table = of_match_ptr(mcp320x_dt_ids),
528 },
529 .probe = mcp320x_probe,
530 .remove = mcp320x_remove,
531 .id_table = mcp320x_id,
532 };
533 module_spi_driver(mcp320x_driver);
534
535 MODULE_AUTHOR("Oskar Andero <oskar.andero@gmail.com>");
536 MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3");
537 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support