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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / iio / adc / stm32-dfsdm-adc.c
blobfcd4a1c00ca0574d02326602f68da118a499fca4
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is the ADC part of the STM32 DFSDM driver
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
7 */
8
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
12 #include <linux/iio/buffer.h>
13 #include <linux/iio/hw-consumer.h>
14 #include <linux/iio/sysfs.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21
22 #include "stm32-dfsdm.h"
23
24 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
25
26 /* Conversion timeout */
27 #define DFSDM_TIMEOUT_US 100000
28 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
29
30 /* Oversampling attribute default */
31 #define DFSDM_DEFAULT_OVERSAMPLING 100
32
33 /* Oversampling max values */
34 #define DFSDM_MAX_INT_OVERSAMPLING 256
35 #define DFSDM_MAX_FL_OVERSAMPLING 1024
36
37 /* Max sample resolutions */
38 #define DFSDM_MAX_RES BIT(31)
39 #define DFSDM_DATA_RES BIT(23)
40
41 enum sd_converter_type {
42 DFSDM_AUDIO,
43 DFSDM_IIO,
44 };
45
46 struct stm32_dfsdm_dev_data {
47 int type;
48 int (*init)(struct iio_dev *indio_dev);
49 unsigned int num_channels;
50 const struct regmap_config *regmap_cfg;
51 };
52
53 struct stm32_dfsdm_adc {
54 struct stm32_dfsdm *dfsdm;
55 const struct stm32_dfsdm_dev_data *dev_data;
56 unsigned int fl_id;
57
58 /* ADC specific */
59 unsigned int oversamp;
60 struct iio_hw_consumer *hwc;
61 struct completion completion;
62 u32 *buffer;
63
64 /* Audio specific */
65 unsigned int spi_freq; /* SPI bus clock frequency */
66 unsigned int sample_freq; /* Sample frequency after filter decimation */
67 int (*cb)(const void *data, size_t size, void *cb_priv);
68 void *cb_priv;
69
70 /* DMA */
71 u8 *rx_buf;
72 unsigned int bufi; /* Buffer current position */
73 unsigned int buf_sz; /* Buffer size */
74 struct dma_chan *dma_chan;
75 dma_addr_t dma_buf;
76 };
77
78 struct stm32_dfsdm_str2field {
79 const char *name;
80 unsigned int val;
81 };
82
83 /* DFSDM channel serial interface type */
84 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
85 { "SPI_R", 0 }, /* SPI with data on rising edge */
86 { "SPI_F", 1 }, /* SPI with data on falling edge */
87 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
88 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
89 {},
90 };
91
92 /* DFSDM channel clock source */
93 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
94 /* External SPI clock (CLKIN x) */
95 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
96 /* Internal SPI clock (CLKOUT) */
97 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
98 /* Internal SPI clock divided by 2 (falling edge) */
99 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
100 /* Internal SPI clock divided by 2 (falling edge) */
101 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
102 {},
103 };
104
105 static int stm32_dfsdm_str2val(const char *str,
106 const struct stm32_dfsdm_str2field *list)
107 {
108 const struct stm32_dfsdm_str2field *p = list;
109
110 for (p = list; p && p->name; p++)
111 if (!strcmp(p->name, str))
112 return p->val;
113
114 return -EINVAL;
115 }
116
117 static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl,
118 unsigned int fast, unsigned int oversamp)
119 {
120 unsigned int i, d, fosr, iosr;
121 u64 res;
122 s64 delta;
123 unsigned int m = 1; /* multiplication factor */
124 unsigned int p = fl->ford; /* filter order (ford) */
125
126 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
127 /*
128 * This function tries to compute filter oversampling and integrator
129 * oversampling, base on oversampling ratio requested by user.
130 *
131 * Decimation d depends on the filter order and the oversampling ratios.
132 * ford: filter order
133 * fosr: filter over sampling ratio
134 * iosr: integrator over sampling ratio
135 */
136 if (fl->ford == DFSDM_FASTSINC_ORDER) {
137 m = 2;
138 p = 2;
139 }
140
141 /*
142 * Look for filter and integrator oversampling ratios which allows
143 * to reach 24 bits data output resolution.
144 * Leave as soon as if exact resolution if reached.
145 * Otherwise the higher resolution below 32 bits is kept.
146 */
147 fl->res = 0;
148 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
149 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
150 if (fast)
151 d = fosr * iosr;
152 else if (fl->ford == DFSDM_FASTSINC_ORDER)
153 d = fosr * (iosr + 3) + 2;
154 else
155 d = fosr * (iosr - 1 + p) + p;
156
157 if (d > oversamp)
158 break;
159 else if (d != oversamp)
160 continue;
161 /*
162 * Check resolution (limited to signed 32 bits)
163 * res <= 2^31
164 * Sincx filters:
165 * res = m * fosr^p x iosr (with m=1, p=ford)
166 * FastSinc filter
167 * res = m * fosr^p x iosr (with m=2, p=2)
168 */
169 res = fosr;
170 for (i = p - 1; i > 0; i--) {
171 res = res * (u64)fosr;
172 if (res > DFSDM_MAX_RES)
173 break;
174 }
175 if (res > DFSDM_MAX_RES)
176 continue;
177 res = res * (u64)m * (u64)iosr;
178 if (res > DFSDM_MAX_RES)
179 continue;
180
181 delta = res - DFSDM_DATA_RES;
182
183 if (res >= fl->res) {
184 fl->res = res;
185 fl->fosr = fosr;
186 fl->iosr = iosr;
187 fl->fast = fast;
188 pr_debug("%s: fosr = %d, iosr = %d\n",
189 __func__, fl->fosr, fl->iosr);
190 }
191
192 if (!delta)
193 return 0;
194 }
195 }
196
197 if (!fl->res)
198 return -EINVAL;
199
200 return 0;
201 }
202
203 static int stm32_dfsdm_start_channel(struct stm32_dfsdm *dfsdm,
204 unsigned int ch_id)
205 {
206 return regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
207 DFSDM_CHCFGR1_CHEN_MASK,
208 DFSDM_CHCFGR1_CHEN(1));
209 }
210
211 static void stm32_dfsdm_stop_channel(struct stm32_dfsdm *dfsdm,
212 unsigned int ch_id)
213 {
214 regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
215 DFSDM_CHCFGR1_CHEN_MASK, DFSDM_CHCFGR1_CHEN(0));
216 }
217
218 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
219 struct stm32_dfsdm_channel *ch)
220 {
221 unsigned int id = ch->id;
222 struct regmap *regmap = dfsdm->regmap;
223 int ret;
224
225 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
226 DFSDM_CHCFGR1_SITP_MASK,
227 DFSDM_CHCFGR1_SITP(ch->type));
228 if (ret < 0)
229 return ret;
230 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
231 DFSDM_CHCFGR1_SPICKSEL_MASK,
232 DFSDM_CHCFGR1_SPICKSEL(ch->src));
233 if (ret < 0)
234 return ret;
235 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
236 DFSDM_CHCFGR1_CHINSEL_MASK,
237 DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
238 }
239
240 static int stm32_dfsdm_start_filter(struct stm32_dfsdm *dfsdm,
241 unsigned int fl_id)
242 {
243 int ret;
244
245 /* Enable filter */
246 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
247 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
248 if (ret < 0)
249 return ret;
250
251 /* Start conversion */
252 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
253 DFSDM_CR1_RSWSTART_MASK,
254 DFSDM_CR1_RSWSTART(1));
255 }
256
257 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
258 unsigned int fl_id)
259 {
260 /* Disable conversion */
261 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
262 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
263 }
264
265 static int stm32_dfsdm_filter_configure(struct stm32_dfsdm *dfsdm,
266 unsigned int fl_id, unsigned int ch_id)
267 {
268 struct regmap *regmap = dfsdm->regmap;
269 struct stm32_dfsdm_filter *fl = &dfsdm->fl_list[fl_id];
270 int ret;
271
272 /* Average integrator oversampling */
273 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
274 DFSDM_FCR_IOSR(fl->iosr - 1));
275 if (ret)
276 return ret;
277
278 /* Filter order and Oversampling */
279 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
280 DFSDM_FCR_FOSR(fl->fosr - 1));
281 if (ret)
282 return ret;
283
284 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
285 DFSDM_FCR_FORD(fl->ford));
286 if (ret)
287 return ret;
288
289 /* No scan mode supported for the moment */
290 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_RCH_MASK,
291 DFSDM_CR1_RCH(ch_id));
292 if (ret)
293 return ret;
294
295 return regmap_update_bits(regmap, DFSDM_CR1(fl_id),
296 DFSDM_CR1_RSYNC_MASK,
297 DFSDM_CR1_RSYNC(fl->sync_mode));
298 }
299
300 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
301 struct iio_dev *indio_dev,
302 struct iio_chan_spec *ch)
303 {
304 struct stm32_dfsdm_channel *df_ch;
305 const char *of_str;
306 int chan_idx = ch->scan_index;
307 int ret, val;
308
309 ret = of_property_read_u32_index(indio_dev->dev.of_node,
310 "st,adc-channels", chan_idx,
311 &ch->channel);
312 if (ret < 0) {
313 dev_err(&indio_dev->dev,
314 " Error parsing 'st,adc-channels' for idx %d\n",
315 chan_idx);
316 return ret;
317 }
318 if (ch->channel >= dfsdm->num_chs) {
319 dev_err(&indio_dev->dev,
320 " Error bad channel number %d (max = %d)\n",
321 ch->channel, dfsdm->num_chs);
322 return -EINVAL;
323 }
324
325 ret = of_property_read_string_index(indio_dev->dev.of_node,
326 "st,adc-channel-names", chan_idx,
327 &ch->datasheet_name);
328 if (ret < 0) {
329 dev_err(&indio_dev->dev,
330 " Error parsing 'st,adc-channel-names' for idx %d\n",
331 chan_idx);
332 return ret;
333 }
334
335 df_ch = &dfsdm->ch_list[ch->channel];
336 df_ch->id = ch->channel;
337
338 ret = of_property_read_string_index(indio_dev->dev.of_node,
339 "st,adc-channel-types", chan_idx,
340 &of_str);
341 if (!ret) {
342 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
343 if (val < 0)
344 return val;
345 } else {
346 val = 0;
347 }
348 df_ch->type = val;
349
350 ret = of_property_read_string_index(indio_dev->dev.of_node,
351 "st,adc-channel-clk-src", chan_idx,
352 &of_str);
353 if (!ret) {
354 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
355 if (val < 0)
356 return val;
357 } else {
358 val = 0;
359 }
360 df_ch->src = val;
361
362 ret = of_property_read_u32_index(indio_dev->dev.of_node,
363 "st,adc-alt-channel", chan_idx,
364 &df_ch->alt_si);
365 if (ret < 0)
366 df_ch->alt_si = 0;
367
368 return 0;
369 }
370
371 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
372 uintptr_t priv,
373 const struct iio_chan_spec *chan,
374 char *buf)
375 {
376 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
377
378 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
379 }
380
381 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
382 uintptr_t priv,
383 const struct iio_chan_spec *chan,
384 const char *buf, size_t len)
385 {
386 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
387 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
388 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
389 unsigned int sample_freq = adc->sample_freq;
390 unsigned int spi_freq;
391 int ret;
392
393 dev_err(&indio_dev->dev, "enter %s\n", __func__);
394 /* If DFSDM is master on SPI, SPI freq can not be updated */
395 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
396 return -EPERM;
397
398 ret = kstrtoint(buf, 0, &spi_freq);
399 if (ret)
400 return ret;
401
402 if (!spi_freq)
403 return -EINVAL;
404
405 if (sample_freq) {
406 if (spi_freq % sample_freq)
407 dev_warn(&indio_dev->dev,
408 "Sampling rate not accurate (%d)\n",
409 spi_freq / (spi_freq / sample_freq));
410
411 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / sample_freq));
412 if (ret < 0) {
413 dev_err(&indio_dev->dev,
414 "No filter parameters that match!\n");
415 return ret;
416 }
417 }
418 adc->spi_freq = spi_freq;
419
420 return len;
421 }
422
423 static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
424 const struct iio_chan_spec *chan,
425 bool dma)
426 {
427 struct regmap *regmap = adc->dfsdm->regmap;
428 int ret;
429 unsigned int dma_en = 0, cont_en = 0;
430
431 ret = stm32_dfsdm_start_channel(adc->dfsdm, chan->channel);
432 if (ret < 0)
433 return ret;
434
435 ret = stm32_dfsdm_filter_configure(adc->dfsdm, adc->fl_id,
436 chan->channel);
437 if (ret < 0)
438 goto stop_channels;
439
440 if (dma) {
441 /* Enable DMA transfer*/
442 dma_en = DFSDM_CR1_RDMAEN(1);
443 /* Enable conversion triggered by SPI clock*/
444 cont_en = DFSDM_CR1_RCONT(1);
445 }
446 /* Enable DMA transfer*/
447 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
448 DFSDM_CR1_RDMAEN_MASK, dma_en);
449 if (ret < 0)
450 goto stop_channels;
451
452 /* Enable conversion triggered by SPI clock*/
453 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
454 DFSDM_CR1_RCONT_MASK, cont_en);
455 if (ret < 0)
456 goto stop_channels;
457
458 ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id);
459 if (ret < 0)
460 goto stop_channels;
461
462 return 0;
463
464 stop_channels:
465 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
466 DFSDM_CR1_RDMAEN_MASK, 0);
467
468 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
469 DFSDM_CR1_RCONT_MASK, 0);
470 stm32_dfsdm_stop_channel(adc->dfsdm, chan->channel);
471
472 return ret;
473 }
474
475 static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc,
476 const struct iio_chan_spec *chan)
477 {
478 struct regmap *regmap = adc->dfsdm->regmap;
479
480 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
481
482 /* Clean conversion options */
483 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
484 DFSDM_CR1_RDMAEN_MASK, 0);
485
486 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
487 DFSDM_CR1_RCONT_MASK, 0);
488
489 stm32_dfsdm_stop_channel(adc->dfsdm, chan->channel);
490 }
491
492 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
493 unsigned int val)
494 {
495 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
496 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
497
498 /*
499 * DMA cyclic transfers are used, buffer is split into two periods.
500 * There should be :
501 * - always one buffer (period) DMA is working on
502 * - one buffer (period) driver pushed to ASoC side.
503 */
504 watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
505 adc->buf_sz = watermark * 2;
506
507 return 0;
508 }
509
510 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
511 {
512 struct dma_tx_state state;
513 enum dma_status status;
514
515 status = dmaengine_tx_status(adc->dma_chan,
516 adc->dma_chan->cookie,
517 &state);
518 if (status == DMA_IN_PROGRESS) {
519 /* Residue is size in bytes from end of buffer */
520 unsigned int i = adc->buf_sz - state.residue;
521 unsigned int size;
522
523 /* Return available bytes */
524 if (i >= adc->bufi)
525 size = i - adc->bufi;
526 else
527 size = adc->buf_sz + i - adc->bufi;
528
529 return size;
530 }
531
532 return 0;
533 }
534
535 static void stm32_dfsdm_audio_dma_buffer_done(void *data)
536 {
537 struct iio_dev *indio_dev = data;
538 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
539 int available = stm32_dfsdm_adc_dma_residue(adc);
540 size_t old_pos;
541
542 /*
543 * FIXME: In Kernel interface does not support cyclic DMA buffer,and
544 * offers only an interface to push data samples per samples.
545 * For this reason IIO buffer interface is not used and interface is
546 * bypassed using a private callback registered by ASoC.
547 * This should be a temporary solution waiting a cyclic DMA engine
548 * support in IIO.
549 */
550
551 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
552 adc->bufi, available);
553 old_pos = adc->bufi;
554
555 while (available >= indio_dev->scan_bytes) {
556 u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi];
557
558 /* Mask 8 LSB that contains the channel ID */
559 *buffer = (*buffer & 0xFFFFFF00) << 8;
560 available -= indio_dev->scan_bytes;
561 adc->bufi += indio_dev->scan_bytes;
562 if (adc->bufi >= adc->buf_sz) {
563 if (adc->cb)
564 adc->cb(&adc->rx_buf[old_pos],
565 adc->buf_sz - old_pos, adc->cb_priv);
566 adc->bufi = 0;
567 old_pos = 0;
568 }
569 }
570 if (adc->cb)
571 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
572 adc->cb_priv);
573 }
574
575 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
576 {
577 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
578 struct dma_async_tx_descriptor *desc;
579 dma_cookie_t cookie;
580 int ret;
581
582 if (!adc->dma_chan)
583 return -EINVAL;
584
585 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
586 adc->buf_sz, adc->buf_sz / 2);
587
588 /* Prepare a DMA cyclic transaction */
589 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
590 adc->dma_buf,
591 adc->buf_sz, adc->buf_sz / 2,
592 DMA_DEV_TO_MEM,
593 DMA_PREP_INTERRUPT);
594 if (!desc)
595 return -EBUSY;
596
597 desc->callback = stm32_dfsdm_audio_dma_buffer_done;
598 desc->callback_param = indio_dev;
599
600 cookie = dmaengine_submit(desc);
601 ret = dma_submit_error(cookie);
602 if (ret) {
603 dmaengine_terminate_all(adc->dma_chan);
604 return ret;
605 }
606
607 /* Issue pending DMA requests */
608 dma_async_issue_pending(adc->dma_chan);
609
610 return 0;
611 }
612
613 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
614 {
615 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
616 const struct iio_chan_spec *chan = &indio_dev->channels[0];
617 int ret;
618
619 /* Reset adc buffer index */
620 adc->bufi = 0;
621
622 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
623 if (ret < 0)
624 return ret;
625
626 ret = stm32_dfsdm_start_conv(adc, chan, true);
627 if (ret) {
628 dev_err(&indio_dev->dev, "Can't start conversion\n");
629 goto stop_dfsdm;
630 }
631
632 if (adc->dma_chan) {
633 ret = stm32_dfsdm_adc_dma_start(indio_dev);
634 if (ret) {
635 dev_err(&indio_dev->dev, "Can't start DMA\n");
636 goto err_stop_conv;
637 }
638 }
639
640 return 0;
641
642 err_stop_conv:
643 stm32_dfsdm_stop_conv(adc, chan);
644 stop_dfsdm:
645 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
646
647 return ret;
648 }
649
650 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
651 {
652 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
653 const struct iio_chan_spec *chan = &indio_dev->channels[0];
654
655 if (adc->dma_chan)
656 dmaengine_terminate_all(adc->dma_chan);
657
658 stm32_dfsdm_stop_conv(adc, chan);
659
660 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
661
662 return 0;
663 }
664
665 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
666 .postenable = &stm32_dfsdm_postenable,
667 .predisable = &stm32_dfsdm_predisable,
668 };
669
670 /**
671 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
672 * DMA transfer period is achieved.
673 *
674 * @iio_dev: Handle to IIO device.
675 * @cb: Pointer to callback function:
676 * - data: pointer to data buffer
677 * - size: size in byte of the data buffer
678 * - private: pointer to consumer private structure.
679 * @private: Pointer to consumer private structure.
680 */
681 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
682 int (*cb)(const void *data, size_t size,
683 void *private),
684 void *private)
685 {
686 struct stm32_dfsdm_adc *adc;
687
688 if (!iio_dev)
689 return -EINVAL;
690 adc = iio_priv(iio_dev);
691
692 adc->cb = cb;
693 adc->cb_priv = private;
694
695 return 0;
696 }
697 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
698
699 /**
700 * stm32_dfsdm_release_buff_cb - unregister buffer callback
701 *
702 * @iio_dev: Handle to IIO device.
703 */
704 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
705 {
706 struct stm32_dfsdm_adc *adc;
707
708 if (!iio_dev)
709 return -EINVAL;
710 adc = iio_priv(iio_dev);
711
712 adc->cb = NULL;
713 adc->cb_priv = NULL;
714
715 return 0;
716 }
717 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
718
719 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
720 const struct iio_chan_spec *chan, int *res)
721 {
722 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
723 long timeout;
724 int ret;
725
726 reinit_completion(&adc->completion);
727
728 adc->buffer = res;
729
730 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
731 if (ret < 0)
732 return ret;
733
734 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
735 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
736 if (ret < 0)
737 goto stop_dfsdm;
738
739 ret = stm32_dfsdm_start_conv(adc, chan, false);
740 if (ret < 0) {
741 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
742 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
743 goto stop_dfsdm;
744 }
745
746 timeout = wait_for_completion_interruptible_timeout(&adc->completion,
747 DFSDM_TIMEOUT);
748
749 /* Mask IRQ for regular conversion achievement*/
750 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
751 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
752
753 if (timeout == 0)
754 ret = -ETIMEDOUT;
755 else if (timeout < 0)
756 ret = timeout;
757 else
758 ret = IIO_VAL_INT;
759
760 stm32_dfsdm_stop_conv(adc, chan);
761
762 stop_dfsdm:
763 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
764
765 return ret;
766 }
767
768 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
769 struct iio_chan_spec const *chan,
770 int val, int val2, long mask)
771 {
772 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
773 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
774 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
775 unsigned int spi_freq;
776 int ret = -EINVAL;
777
778 switch (mask) {
779 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
780 ret = stm32_dfsdm_set_osrs(fl, 0, val);
781 if (!ret)
782 adc->oversamp = val;
783
784 return ret;
785
786 case IIO_CHAN_INFO_SAMP_FREQ:
787 if (!val)
788 return -EINVAL;
789
790 switch (ch->src) {
791 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
792 spi_freq = adc->dfsdm->spi_master_freq;
793 break;
794 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
795 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
796 spi_freq = adc->dfsdm->spi_master_freq / 2;
797 break;
798 default:
799 spi_freq = adc->spi_freq;
800 }
801
802 if (spi_freq % val)
803 dev_warn(&indio_dev->dev,
804 "Sampling rate not accurate (%d)\n",
805 spi_freq / (spi_freq / val));
806
807 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / val));
808 if (ret < 0) {
809 dev_err(&indio_dev->dev,
810 "Not able to find parameter that match!\n");
811 return ret;
812 }
813 adc->sample_freq = val;
814
815 return 0;
816 }
817
818 return -EINVAL;
819 }
820
821 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
822 struct iio_chan_spec const *chan, int *val,
823 int *val2, long mask)
824 {
825 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
826 int ret;
827
828 switch (mask) {
829 case IIO_CHAN_INFO_RAW:
830 ret = iio_hw_consumer_enable(adc->hwc);
831 if (ret < 0) {
832 dev_err(&indio_dev->dev,
833 "%s: IIO enable failed (channel %d)\n",
834 __func__, chan->channel);
835 return ret;
836 }
837 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
838 iio_hw_consumer_disable(adc->hwc);
839 if (ret < 0) {
840 dev_err(&indio_dev->dev,
841 "%s: Conversion failed (channel %d)\n",
842 __func__, chan->channel);
843 return ret;
844 }
845 return IIO_VAL_INT;
846
847 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
848 *val = adc->oversamp;
849
850 return IIO_VAL_INT;
851
852 case IIO_CHAN_INFO_SAMP_FREQ:
853 *val = adc->sample_freq;
854
855 return IIO_VAL_INT;
856 }
857
858 return -EINVAL;
859 }
860
861 static const struct iio_info stm32_dfsdm_info_audio = {
862 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
863 .read_raw = stm32_dfsdm_read_raw,
864 .write_raw = stm32_dfsdm_write_raw,
865 };
866
867 static const struct iio_info stm32_dfsdm_info_adc = {
868 .read_raw = stm32_dfsdm_read_raw,
869 .write_raw = stm32_dfsdm_write_raw,
870 };
871
872 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
873 {
874 struct stm32_dfsdm_adc *adc = arg;
875 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
876 struct regmap *regmap = adc->dfsdm->regmap;
877 unsigned int status, int_en;
878
879 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
880 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
881
882 if (status & DFSDM_ISR_REOCF_MASK) {
883 /* Read the data register clean the IRQ status */
884 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
885 complete(&adc->completion);
886 }
887
888 if (status & DFSDM_ISR_ROVRF_MASK) {
889 if (int_en & DFSDM_CR2_ROVRIE_MASK)
890 dev_warn(&indio_dev->dev, "Overrun detected\n");
891 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
892 DFSDM_ICR_CLRROVRF_MASK,
893 DFSDM_ICR_CLRROVRF_MASK);
894 }
895
896 return IRQ_HANDLED;
897 }
898
899 /*
900 * Define external info for SPI Frequency and audio sampling rate that can be
901 * configured by ASoC driver through consumer.h API
902 */
903 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
904 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
905 {
906 .name = "spi_clk_freq",
907 .shared = IIO_SHARED_BY_TYPE,
908 .read = dfsdm_adc_audio_get_spiclk,
909 .write = dfsdm_adc_audio_set_spiclk,
910 },
911 {},
912 };
913
914 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
915 {
916 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
917
918 if (adc->dma_chan) {
919 dma_free_coherent(adc->dma_chan->device->dev,
920 DFSDM_DMA_BUFFER_SIZE,
921 adc->rx_buf, adc->dma_buf);
922 dma_release_channel(adc->dma_chan);
923 }
924 }
925
926 static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev)
927 {
928 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
929 struct dma_slave_config config = {
930 .src_addr = (dma_addr_t)adc->dfsdm->phys_base +
931 DFSDM_RDATAR(adc->fl_id),
932 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
933 };
934 int ret;
935
936 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
937 if (!adc->dma_chan)
938 return -EINVAL;
939
940 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
941 DFSDM_DMA_BUFFER_SIZE,
942 &adc->dma_buf, GFP_KERNEL);
943 if (!adc->rx_buf) {
944 ret = -ENOMEM;
945 goto err_release;
946 }
947
948 ret = dmaengine_slave_config(adc->dma_chan, &config);
949 if (ret)
950 goto err_free;
951
952 return 0;
953
954 err_free:
955 dma_free_coherent(adc->dma_chan->device->dev, DFSDM_DMA_BUFFER_SIZE,
956 adc->rx_buf, adc->dma_buf);
957 err_release:
958 dma_release_channel(adc->dma_chan);
959
960 return ret;
961 }
962
963 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
964 struct iio_chan_spec *ch)
965 {
966 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
967 int ret;
968
969 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
970 if (ret < 0)
971 return ret;
972
973 ch->type = IIO_VOLTAGE;
974 ch->indexed = 1;
975
976 /*
977 * IIO_CHAN_INFO_RAW: used to compute regular conversion
978 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
979 */
980 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
981 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
982
983 if (adc->dev_data->type == DFSDM_AUDIO) {
984 ch->scan_type.sign = 's';
985 ch->ext_info = dfsdm_adc_audio_ext_info;
986 } else {
987 ch->scan_type.sign = 'u';
988 }
989 ch->scan_type.realbits = 24;
990 ch->scan_type.storagebits = 32;
991
992 return stm32_dfsdm_chan_configure(adc->dfsdm,
993 &adc->dfsdm->ch_list[ch->channel]);
994 }
995
996 static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev)
997 {
998 struct iio_chan_spec *ch;
999 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1000 struct stm32_dfsdm_channel *d_ch;
1001 int ret;
1002
1003 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1004 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1005
1006 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1007 if (!ch)
1008 return -ENOMEM;
1009
1010 ch->scan_index = 0;
1011
1012 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1013 if (ret < 0) {
1014 dev_err(&indio_dev->dev, "Channels init failed\n");
1015 return ret;
1016 }
1017 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1018
1019 d_ch = &adc->dfsdm->ch_list[ch->channel];
1020 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1021 adc->spi_freq = adc->dfsdm->spi_master_freq;
1022
1023 indio_dev->num_channels = 1;
1024 indio_dev->channels = ch;
1025
1026 return stm32_dfsdm_dma_request(indio_dev);
1027 }
1028
1029 static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
1030 {
1031 struct iio_chan_spec *ch;
1032 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1033 int num_ch;
1034 int ret, chan_idx;
1035
1036 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1037 ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0,
1038 adc->oversamp);
1039 if (ret < 0)
1040 return ret;
1041
1042 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1043 "st,adc-channels");
1044 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1045 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1046 return num_ch < 0 ? num_ch : -EINVAL;
1047 }
1048
1049 /* Bind to SD modulator IIO device */
1050 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1051 if (IS_ERR(adc->hwc))
1052 return -EPROBE_DEFER;
1053
1054 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1055 GFP_KERNEL);
1056 if (!ch)
1057 return -ENOMEM;
1058
1059 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1060 ch[chan_idx].scan_index = chan_idx;
1061 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1062 if (ret < 0) {
1063 dev_err(&indio_dev->dev, "Channels init failed\n");
1064 return ret;
1065 }
1066 }
1067
1068 indio_dev->num_channels = num_ch;
1069 indio_dev->channels = ch;
1070
1071 init_completion(&adc->completion);
1072
1073 return 0;
1074 }
1075
1076 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1077 .type = DFSDM_IIO,
1078 .init = stm32_dfsdm_adc_init,
1079 };
1080
1081 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1082 .type = DFSDM_AUDIO,
1083 .init = stm32_dfsdm_audio_init,
1084 };
1085
1086 static const struct of_device_id stm32_dfsdm_adc_match[] = {
1087 {
1088 .compatible = "st,stm32-dfsdm-adc",
1089 .data = &stm32h7_dfsdm_adc_data,
1090 },
1091 {
1092 .compatible = "st,stm32-dfsdm-dmic",
1093 .data = &stm32h7_dfsdm_audio_data,
1094 },
1095 {}
1096 };
1097
1098 static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1099 {
1100 struct device *dev = &pdev->dev;
1101 struct stm32_dfsdm_adc *adc;
1102 struct device_node *np = dev->of_node;
1103 const struct stm32_dfsdm_dev_data *dev_data;
1104 struct iio_dev *iio;
1105 char *name;
1106 int ret, irq, val;
1107
1108 dev_data = of_device_get_match_data(dev);
1109 iio = devm_iio_device_alloc(dev, sizeof(*adc));
1110 if (!iio) {
1111 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1112 return -ENOMEM;
1113 }
1114
1115 adc = iio_priv(iio);
1116 adc->dfsdm = dev_get_drvdata(dev->parent);
1117
1118 iio->dev.parent = dev;
1119 iio->dev.of_node = np;
1120 iio->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1121
1122 platform_set_drvdata(pdev, adc);
1123
1124 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1125 if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1126 dev_err(dev, "Missing or bad reg property\n");
1127 return -EINVAL;
1128 }
1129
1130 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1131 if (!name)
1132 return -ENOMEM;
1133 if (dev_data->type == DFSDM_AUDIO) {
1134 iio->info = &stm32_dfsdm_info_audio;
1135 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1136 } else {
1137 iio->info = &stm32_dfsdm_info_adc;
1138 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1139 }
1140 iio->name = name;
1141
1142 /*
1143 * In a first step IRQs generated for channels are not treated.
1144 * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1145 */
1146 irq = platform_get_irq(pdev, 0);
1147 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1148 0, pdev->name, adc);
1149 if (ret < 0) {
1150 dev_err(dev, "Failed to request IRQ\n");
1151 return ret;
1152 }
1153
1154 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1155 if (ret < 0) {
1156 dev_err(dev, "Failed to set filter order\n");
1157 return ret;
1158 }
1159
1160 adc->dfsdm->fl_list[adc->fl_id].ford = val;
1161
1162 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1163 if (!ret)
1164 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1165
1166 adc->dev_data = dev_data;
1167 ret = dev_data->init(iio);
1168 if (ret < 0)
1169 return ret;
1170
1171 ret = iio_device_register(iio);
1172 if (ret < 0)
1173 goto err_cleanup;
1174
1175 if (dev_data->type == DFSDM_AUDIO) {
1176 ret = of_platform_populate(np, NULL, NULL, dev);
1177 if (ret < 0) {
1178 dev_err(dev, "Failed to find an audio DAI\n");
1179 goto err_unregister;
1180 }
1181 }
1182
1183 return 0;
1184
1185 err_unregister:
1186 iio_device_unregister(iio);
1187 err_cleanup:
1188 stm32_dfsdm_dma_release(iio);
1189
1190 return ret;
1191 }
1192
1193 static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1194 {
1195 struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
1196 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1197
1198 if (adc->dev_data->type == DFSDM_AUDIO)
1199 of_platform_depopulate(&pdev->dev);
1200 iio_device_unregister(indio_dev);
1201 stm32_dfsdm_dma_release(indio_dev);
1202
1203 return 0;
1204 }
1205
1206 static struct platform_driver stm32_dfsdm_adc_driver = {
1207 .driver = {
1208 .name = "stm32-dfsdm-adc",
1209 .of_match_table = stm32_dfsdm_adc_match,
1210 },
1211 .probe = stm32_dfsdm_adc_probe,
1212 .remove = stm32_dfsdm_adc_remove,
1213 };
1214 module_platform_driver(stm32_dfsdm_adc_driver);
1215
1216 MODULE_DESCRIPTION("STM32 sigma delta ADC");
1217 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1218 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support