1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part the core part STM32 DFSDM driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
10 #include <linux/iio/iio.h>
11 #include <linux/iio/sysfs.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
18 #include "stm32-dfsdm.h"
20 struct stm32_dfsdm_dev_data
{
21 unsigned int num_filters
;
22 unsigned int num_channels
;
23 const struct regmap_config
*regmap_cfg
;
26 #define STM32H7_DFSDM_NUM_FILTERS 4
27 #define STM32H7_DFSDM_NUM_CHANNELS 8
28 #define STM32MP1_DFSDM_NUM_FILTERS 6
29 #define STM32MP1_DFSDM_NUM_CHANNELS 8
31 static bool stm32_dfsdm_volatile_reg(struct device
*dev
, unsigned int reg
)
33 if (reg
< DFSDM_FILTER_BASE_ADR
)
37 * Mask is done on register to avoid to list registers of all
40 switch (reg
& DFSDM_FILTER_REG_MASK
) {
41 case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK
:
42 case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK
:
43 case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK
:
44 case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK
:
51 static const struct regmap_config stm32h7_dfsdm_regmap_cfg
= {
54 .reg_stride
= sizeof(u32
),
55 .max_register
= 0x2B8,
56 .volatile_reg
= stm32_dfsdm_volatile_reg
,
60 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data
= {
61 .num_filters
= STM32H7_DFSDM_NUM_FILTERS
,
62 .num_channels
= STM32H7_DFSDM_NUM_CHANNELS
,
63 .regmap_cfg
= &stm32h7_dfsdm_regmap_cfg
,
66 static const struct regmap_config stm32mp1_dfsdm_regmap_cfg
= {
69 .reg_stride
= sizeof(u32
),
70 .max_register
= 0x7fc,
71 .volatile_reg
= stm32_dfsdm_volatile_reg
,
75 static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data
= {
76 .num_filters
= STM32MP1_DFSDM_NUM_FILTERS
,
77 .num_channels
= STM32MP1_DFSDM_NUM_CHANNELS
,
78 .regmap_cfg
= &stm32mp1_dfsdm_regmap_cfg
,
82 struct platform_device
*pdev
; /* platform device */
84 struct stm32_dfsdm dfsdm
; /* common data exported for all instances */
86 unsigned int spi_clk_out_div
; /* SPI clkout divider value */
87 atomic_t n_active_ch
; /* number of current active channels */
89 struct clk
*clk
; /* DFSDM clock */
90 struct clk
*aclk
; /* audio clock */
94 * stm32_dfsdm_start_dfsdm - start global dfsdm interface.
96 * Enable interface if n_active_ch is not null.
97 * @dfsdm: Handle used to retrieve dfsdm context.
99 int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm
*dfsdm
)
101 struct dfsdm_priv
*priv
= container_of(dfsdm
, struct dfsdm_priv
, dfsdm
);
102 struct device
*dev
= &priv
->pdev
->dev
;
103 unsigned int clk_div
= priv
->spi_clk_out_div
, clk_src
;
106 if (atomic_inc_return(&priv
->n_active_ch
) == 1) {
107 ret
= clk_prepare_enable(priv
->clk
);
109 dev_err(dev
, "Failed to start clock\n");
113 ret
= clk_prepare_enable(priv
->aclk
);
115 dev_err(dev
, "Failed to start audio clock\n");
120 /* select clock source, e.g. 0 for "dfsdm" or 1 for "audio" */
121 clk_src
= priv
->aclk
? 1 : 0;
122 ret
= regmap_update_bits(dfsdm
->regmap
, DFSDM_CHCFGR1(0),
123 DFSDM_CHCFGR1_CKOUTSRC_MASK
,
124 DFSDM_CHCFGR1_CKOUTSRC(clk_src
));
128 /* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
129 ret
= regmap_update_bits(dfsdm
->regmap
, DFSDM_CHCFGR1(0),
130 DFSDM_CHCFGR1_CKOUTDIV_MASK
,
131 DFSDM_CHCFGR1_CKOUTDIV(clk_div
));
135 /* Global enable of DFSDM interface */
136 ret
= regmap_update_bits(dfsdm
->regmap
, DFSDM_CHCFGR1(0),
137 DFSDM_CHCFGR1_DFSDMEN_MASK
,
138 DFSDM_CHCFGR1_DFSDMEN(1));
143 dev_dbg(dev
, "%s: n_active_ch %d\n", __func__
,
144 atomic_read(&priv
->n_active_ch
));
149 clk_disable_unprepare(priv
->aclk
);
151 clk_disable_unprepare(priv
->clk
);
154 atomic_dec(&priv
->n_active_ch
);
158 EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm
);
161 * stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
163 * Disable interface if n_active_ch is null
164 * @dfsdm: Handle used to retrieve dfsdm context.
166 int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm
*dfsdm
)
168 struct dfsdm_priv
*priv
= container_of(dfsdm
, struct dfsdm_priv
, dfsdm
);
171 if (atomic_dec_and_test(&priv
->n_active_ch
)) {
172 /* Global disable of DFSDM interface */
173 ret
= regmap_update_bits(dfsdm
->regmap
, DFSDM_CHCFGR1(0),
174 DFSDM_CHCFGR1_DFSDMEN_MASK
,
175 DFSDM_CHCFGR1_DFSDMEN(0));
179 /* Stop SPI CLKOUT */
180 ret
= regmap_update_bits(dfsdm
->regmap
, DFSDM_CHCFGR1(0),
181 DFSDM_CHCFGR1_CKOUTDIV_MASK
,
182 DFSDM_CHCFGR1_CKOUTDIV(0));
186 clk_disable_unprepare(priv
->clk
);
188 clk_disable_unprepare(priv
->aclk
);
190 dev_dbg(&priv
->pdev
->dev
, "%s: n_active_ch %d\n", __func__
,
191 atomic_read(&priv
->n_active_ch
));
195 EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm
);
197 static int stm32_dfsdm_parse_of(struct platform_device
*pdev
,
198 struct dfsdm_priv
*priv
)
200 struct device_node
*node
= pdev
->dev
.of_node
;
201 struct resource
*res
;
202 unsigned long clk_freq
;
203 unsigned int spi_freq
, rem
;
209 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
211 dev_err(&pdev
->dev
, "Failed to get memory resource\n");
214 priv
->dfsdm
.phys_base
= res
->start
;
215 priv
->dfsdm
.base
= devm_ioremap_resource(&pdev
->dev
, res
);
218 * "dfsdm" clock is mandatory for DFSDM peripheral clocking.
219 * "dfsdm" or "audio" clocks can be used as source clock for
220 * the SPI clock out signal and internal processing, depending
223 priv
->clk
= devm_clk_get(&pdev
->dev
, "dfsdm");
224 if (IS_ERR(priv
->clk
)) {
225 dev_err(&pdev
->dev
, "No stm32_dfsdm_clk clock found\n");
229 priv
->aclk
= devm_clk_get(&pdev
->dev
, "audio");
230 if (IS_ERR(priv
->aclk
))
234 clk_freq
= clk_get_rate(priv
->aclk
);
236 clk_freq
= clk_get_rate(priv
->clk
);
238 /* SPI clock out frequency */
239 ret
= of_property_read_u32(pdev
->dev
.of_node
, "spi-max-frequency",
242 /* No SPI master mode */
246 priv
->spi_clk_out_div
= div_u64_rem(clk_freq
, spi_freq
, &rem
) - 1;
247 if (!priv
->spi_clk_out_div
) {
248 /* spi_clk_out_div == 0 means ckout is OFF */
249 dev_err(&pdev
->dev
, "spi-max-frequency not achievable\n");
252 priv
->dfsdm
.spi_master_freq
= spi_freq
;
255 dev_warn(&pdev
->dev
, "SPI clock not accurate\n");
256 dev_warn(&pdev
->dev
, "%ld = %d * %d + %d\n",
257 clk_freq
, spi_freq
, priv
->spi_clk_out_div
+ 1, rem
);
263 static const struct of_device_id stm32_dfsdm_of_match
[] = {
265 .compatible
= "st,stm32h7-dfsdm",
266 .data
= &stm32h7_dfsdm_data
,
269 .compatible
= "st,stm32mp1-dfsdm",
270 .data
= &stm32mp1_dfsdm_data
,
274 MODULE_DEVICE_TABLE(of
, stm32_dfsdm_of_match
);
276 static int stm32_dfsdm_probe(struct platform_device
*pdev
)
278 struct dfsdm_priv
*priv
;
279 const struct stm32_dfsdm_dev_data
*dev_data
;
280 struct stm32_dfsdm
*dfsdm
;
283 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
289 dev_data
= of_device_get_match_data(&pdev
->dev
);
291 dfsdm
= &priv
->dfsdm
;
292 dfsdm
->fl_list
= devm_kcalloc(&pdev
->dev
, dev_data
->num_filters
,
293 sizeof(*dfsdm
->fl_list
), GFP_KERNEL
);
297 dfsdm
->num_fls
= dev_data
->num_filters
;
298 dfsdm
->ch_list
= devm_kcalloc(&pdev
->dev
, dev_data
->num_channels
,
299 sizeof(*dfsdm
->ch_list
),
303 dfsdm
->num_chs
= dev_data
->num_channels
;
305 ret
= stm32_dfsdm_parse_of(pdev
, priv
);
309 dfsdm
->regmap
= devm_regmap_init_mmio_clk(&pdev
->dev
, "dfsdm",
311 dev_data
->regmap_cfg
);
312 if (IS_ERR(dfsdm
->regmap
)) {
313 ret
= PTR_ERR(dfsdm
->regmap
);
314 dev_err(&pdev
->dev
, "%s: Failed to allocate regmap: %d\n",
319 platform_set_drvdata(pdev
, dfsdm
);
321 return devm_of_platform_populate(&pdev
->dev
);
324 static struct platform_driver stm32_dfsdm_driver
= {
325 .probe
= stm32_dfsdm_probe
,
327 .name
= "stm32-dfsdm",
328 .of_match_table
= stm32_dfsdm_of_match
,
332 module_platform_driver(stm32_dfsdm_driver
);
334 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
335 MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
336 MODULE_LICENSE("GPL v2");