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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / iommu / amd_iommu.c
blob4e04fff23977348877cce7a00d4ae394fadf91ef
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
46 #include <asm/apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
51 #include <asm/gart.h>
52 #include <asm/dma.h>
53
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
57
58 #define AMD_IOMMU_MAPPING_ERROR 0
59
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61
62 #define LOOP_TIMEOUT 100000
63
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
67
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
73
74 /*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
80 * 512GB Pages are not supported due to a hardware bug
81 */
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
85 static DEFINE_SPINLOCK(pd_bitmap_lock);
86
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list);
89
90 LIST_HEAD(ioapic_map);
91 LIST_HEAD(hpet_map);
92 LIST_HEAD(acpihid_map);
93
94 /*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
98 const struct iommu_ops amd_iommu_ops;
99
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
102
103 static const struct dma_map_ops amd_iommu_dma_ops;
104
105 /*
106 * general struct to manage commands send to an IOMMU
107 */
108 struct iommu_cmd {
109 u32 data[4];
110 };
111
112 struct kmem_cache *amd_iommu_irq_cache;
113
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
118
119 /*
120 * Data container for a dma_ops specific protection domain
121 */
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
128 };
129
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
132
133 /****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
141 {
142 const char *hid, *uid;
143
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
146
147 if (!hid || !(*hid))
148 return -ENODEV;
149
150 if (!uid || !(*uid))
151 return strcmp(hid, entry->hid);
152
153 if (!(*entry->uid))
154 return strcmp(hid, entry->hid);
155
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
157 }
158
159 static inline u16 get_pci_device_id(struct device *dev)
160 {
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164 }
165
166 static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
168 {
169 struct acpihid_map_entry *p;
170
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
173 if (entry)
174 *entry = p;
175 return p->devid;
176 }
177 }
178 return -EINVAL;
179 }
180
181 static inline int get_device_id(struct device *dev)
182 {
183 int devid;
184
185 if (dev_is_pci(dev))
186 devid = get_pci_device_id(dev);
187 else
188 devid = get_acpihid_device_id(dev, NULL);
189
190 return devid;
191 }
192
193 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194 {
195 return container_of(dom, struct protection_domain, domain);
196 }
197
198 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199 {
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
202 }
203
204 static struct iommu_dev_data *alloc_dev_data(u16 devid)
205 {
206 struct iommu_dev_data *dev_data;
207
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
209 if (!dev_data)
210 return NULL;
211
212 dev_data->devid = devid;
213 ratelimit_default_init(&dev_data->rs);
214
215 llist_add(&dev_data->dev_data_list, &dev_data_list);
216 return dev_data;
217 }
218
219 static struct iommu_dev_data *search_dev_data(u16 devid)
220 {
221 struct iommu_dev_data *dev_data;
222 struct llist_node *node;
223
224 if (llist_empty(&dev_data_list))
225 return NULL;
226
227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
229 if (dev_data->devid == devid)
230 return dev_data;
231 }
232
233 return NULL;
234 }
235
236 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
237 {
238 *(u16 *)data = alias;
239 return 0;
240 }
241
242 static u16 get_alias(struct device *dev)
243 {
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
246
247 /* The callers make sure that get_device_id() does not fail here */
248 devid = get_device_id(dev);
249 ivrs_alias = amd_iommu_alias_table[devid];
250 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
251
252 if (ivrs_alias == pci_alias)
253 return ivrs_alias;
254
255 /*
256 * DMA alias showdown
257 *
258 * The IVRS is fairly reliable in telling us about aliases, but it
259 * can't know about every screwy device. If we don't have an IVRS
260 * reported alias, use the PCI reported alias. In that case we may
261 * still need to initialize the rlookup and dev_table entries if the
262 * alias is to a non-existent device.
263 */
264 if (ivrs_alias == devid) {
265 if (!amd_iommu_rlookup_table[pci_alias]) {
266 amd_iommu_rlookup_table[pci_alias] =
267 amd_iommu_rlookup_table[devid];
268 memcpy(amd_iommu_dev_table[pci_alias].data,
269 amd_iommu_dev_table[devid].data,
270 sizeof(amd_iommu_dev_table[pci_alias].data));
271 }
272
273 return pci_alias;
274 }
275
276 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
277 "for device %s[%04x:%04x], kernel reported alias "
278 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
279 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
280 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
281 PCI_FUNC(pci_alias));
282
283 /*
284 * If we don't have a PCI DMA alias and the IVRS alias is on the same
285 * bus, then the IVRS table may know about a quirk that we don't.
286 */
287 if (pci_alias == devid &&
288 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
289 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
290 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
291 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
292 dev_name(dev));
293 }
294
295 return ivrs_alias;
296 }
297
298 static struct iommu_dev_data *find_dev_data(u16 devid)
299 {
300 struct iommu_dev_data *dev_data;
301 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
302
303 dev_data = search_dev_data(devid);
304
305 if (dev_data == NULL) {
306 dev_data = alloc_dev_data(devid);
307 if (!dev_data)
308 return NULL;
309
310 if (translation_pre_enabled(iommu))
311 dev_data->defer_attach = true;
312 }
313
314 return dev_data;
315 }
316
317 struct iommu_dev_data *get_dev_data(struct device *dev)
318 {
319 return dev->archdata.iommu;
320 }
321 EXPORT_SYMBOL(get_dev_data);
322
323 /*
324 * Find or create an IOMMU group for a acpihid device.
325 */
326 static struct iommu_group *acpihid_device_group(struct device *dev)
327 {
328 struct acpihid_map_entry *p, *entry = NULL;
329 int devid;
330
331 devid = get_acpihid_device_id(dev, &entry);
332 if (devid < 0)
333 return ERR_PTR(devid);
334
335 list_for_each_entry(p, &acpihid_map, list) {
336 if ((devid == p->devid) && p->group)
337 entry->group = p->group;
338 }
339
340 if (!entry->group)
341 entry->group = generic_device_group(dev);
342 else
343 iommu_group_ref_get(entry->group);
344
345 return entry->group;
346 }
347
348 static bool pci_iommuv2_capable(struct pci_dev *pdev)
349 {
350 static const int caps[] = {
351 PCI_EXT_CAP_ID_ATS,
352 PCI_EXT_CAP_ID_PRI,
353 PCI_EXT_CAP_ID_PASID,
354 };
355 int i, pos;
356
357 if (pci_ats_disabled())
358 return false;
359
360 for (i = 0; i < 3; ++i) {
361 pos = pci_find_ext_capability(pdev, caps[i]);
362 if (pos == 0)
363 return false;
364 }
365
366 return true;
367 }
368
369 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
370 {
371 struct iommu_dev_data *dev_data;
372
373 dev_data = get_dev_data(&pdev->dev);
374
375 return dev_data->errata & (1 << erratum) ? true : false;
376 }
377
378 /*
379 * This function checks if the driver got a valid device from the caller to
380 * avoid dereferencing invalid pointers.
381 */
382 static bool check_device(struct device *dev)
383 {
384 int devid;
385
386 if (!dev || !dev->dma_mask)
387 return false;
388
389 devid = get_device_id(dev);
390 if (devid < 0)
391 return false;
392
393 /* Out of our scope? */
394 if (devid > amd_iommu_last_bdf)
395 return false;
396
397 if (amd_iommu_rlookup_table[devid] == NULL)
398 return false;
399
400 return true;
401 }
402
403 static void init_iommu_group(struct device *dev)
404 {
405 struct iommu_group *group;
406
407 group = iommu_group_get_for_dev(dev);
408 if (IS_ERR(group))
409 return;
410
411 iommu_group_put(group);
412 }
413
414 static int iommu_init_device(struct device *dev)
415 {
416 struct iommu_dev_data *dev_data;
417 struct amd_iommu *iommu;
418 int devid;
419
420 if (dev->archdata.iommu)
421 return 0;
422
423 devid = get_device_id(dev);
424 if (devid < 0)
425 return devid;
426
427 iommu = amd_iommu_rlookup_table[devid];
428
429 dev_data = find_dev_data(devid);
430 if (!dev_data)
431 return -ENOMEM;
432
433 dev_data->alias = get_alias(dev);
434
435 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
436 struct amd_iommu *iommu;
437
438 iommu = amd_iommu_rlookup_table[dev_data->devid];
439 dev_data->iommu_v2 = iommu->is_iommu_v2;
440 }
441
442 dev->archdata.iommu = dev_data;
443
444 iommu_device_link(&iommu->iommu, dev);
445
446 return 0;
447 }
448
449 static void iommu_ignore_device(struct device *dev)
450 {
451 u16 alias;
452 int devid;
453
454 devid = get_device_id(dev);
455 if (devid < 0)
456 return;
457
458 alias = get_alias(dev);
459
460 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
461 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
462
463 amd_iommu_rlookup_table[devid] = NULL;
464 amd_iommu_rlookup_table[alias] = NULL;
465 }
466
467 static void iommu_uninit_device(struct device *dev)
468 {
469 struct iommu_dev_data *dev_data;
470 struct amd_iommu *iommu;
471 int devid;
472
473 devid = get_device_id(dev);
474 if (devid < 0)
475 return;
476
477 iommu = amd_iommu_rlookup_table[devid];
478
479 dev_data = search_dev_data(devid);
480 if (!dev_data)
481 return;
482
483 if (dev_data->domain)
484 detach_device(dev);
485
486 iommu_device_unlink(&iommu->iommu, dev);
487
488 iommu_group_remove_device(dev);
489
490 /* Remove dma-ops */
491 dev->dma_ops = NULL;
492
493 /*
494 * We keep dev_data around for unplugged devices and reuse it when the
495 * device is re-plugged - not doing so would introduce a ton of races.
496 */
497 }
498
499 /****************************************************************************
500 *
501 * Interrupt handling functions
502 *
503 ****************************************************************************/
504
505 static void dump_dte_entry(u16 devid)
506 {
507 int i;
508
509 for (i = 0; i < 4; ++i)
510 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
511 amd_iommu_dev_table[devid].data[i]);
512 }
513
514 static void dump_command(unsigned long phys_addr)
515 {
516 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
517 int i;
518
519 for (i = 0; i < 4; ++i)
520 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
521 }
522
523 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
524 u64 address, int flags)
525 {
526 struct iommu_dev_data *dev_data = NULL;
527 struct pci_dev *pdev;
528
529 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
530 devid & 0xff);
531 if (pdev)
532 dev_data = get_dev_data(&pdev->dev);
533
534 if (dev_data && __ratelimit(&dev_data->rs)) {
535 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
536 domain_id, address, flags);
537 } else if (printk_ratelimit()) {
538 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
539 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
540 domain_id, address, flags);
541 }
542
543 if (pdev)
544 pci_dev_put(pdev);
545 }
546
547 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
548 {
549 struct device *dev = iommu->iommu.dev;
550 int type, devid, pasid, flags, tag;
551 volatile u32 *event = __evt;
552 int count = 0;
553 u64 address;
554
555 retry:
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 pasid = PPR_PASID(*(u64 *)&event[0]);
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
561
562 if (type == 0) {
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
566 return;
567 }
568 udelay(1);
569 goto retry;
570 }
571
572 if (type == EVENT_TYPE_IO_FAULT) {
573 amd_iommu_report_page_fault(devid, pasid, address, flags);
574 return;
575 } else {
576 dev_err(dev, "AMD-Vi: Event logged [");
577 }
578
579 switch (type) {
580 case EVENT_TYPE_ILL_DEV:
581 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
582 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
583 pasid, address, flags);
584 dump_dte_entry(devid);
585 break;
586 case EVENT_TYPE_DEV_TAB_ERR:
587 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
588 "address=0x%016llx flags=0x%04x]\n",
589 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
590 address, flags);
591 break;
592 case EVENT_TYPE_PAGE_TAB_ERR:
593 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
594 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
595 pasid, address, flags);
596 break;
597 case EVENT_TYPE_ILL_CMD:
598 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
599 dump_command(address);
600 break;
601 case EVENT_TYPE_CMD_HARD_ERR:
602 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
603 address, flags);
604 break;
605 case EVENT_TYPE_IOTLB_INV_TO:
606 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
607 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
608 address);
609 break;
610 case EVENT_TYPE_INV_DEV_REQ:
611 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
612 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
613 pasid, address, flags);
614 break;
615 case EVENT_TYPE_INV_PPR_REQ:
616 pasid = ((event[0] >> 16) & 0xFFFF)
617 | ((event[1] << 6) & 0xF0000);
618 tag = event[1] & 0x03FF;
619 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 pasid, address, flags);
622 break;
623 default:
624 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
625 event[0], event[1], event[2], event[3]);
626 }
627
628 memset(__evt, 0, 4 * sizeof(u32));
629 }
630
631 static void iommu_poll_events(struct amd_iommu *iommu)
632 {
633 u32 head, tail;
634
635 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
636 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
637
638 while (head != tail) {
639 iommu_print_event(iommu, iommu->evt_buf + head);
640 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
641 }
642
643 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
644 }
645
646 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
647 {
648 struct amd_iommu_fault fault;
649
650 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
651 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
652 return;
653 }
654
655 fault.address = raw[1];
656 fault.pasid = PPR_PASID(raw[0]);
657 fault.device_id = PPR_DEVID(raw[0]);
658 fault.tag = PPR_TAG(raw[0]);
659 fault.flags = PPR_FLAGS(raw[0]);
660
661 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
662 }
663
664 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
665 {
666 u32 head, tail;
667
668 if (iommu->ppr_log == NULL)
669 return;
670
671 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
672 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
673
674 while (head != tail) {
675 volatile u64 *raw;
676 u64 entry[2];
677 int i;
678
679 raw = (u64 *)(iommu->ppr_log + head);
680
681 /*
682 * Hardware bug: Interrupt may arrive before the entry is
683 * written to memory. If this happens we need to wait for the
684 * entry to arrive.
685 */
686 for (i = 0; i < LOOP_TIMEOUT; ++i) {
687 if (PPR_REQ_TYPE(raw[0]) != 0)
688 break;
689 udelay(1);
690 }
691
692 /* Avoid memcpy function-call overhead */
693 entry[0] = raw[0];
694 entry[1] = raw[1];
695
696 /*
697 * To detect the hardware bug we need to clear the entry
698 * back to zero.
699 */
700 raw[0] = raw[1] = 0UL;
701
702 /* Update head pointer of hardware ring-buffer */
703 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
704 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
705
706 /* Handle PPR entry */
707 iommu_handle_ppr_entry(iommu, entry);
708
709 /* Refresh ring-buffer information */
710 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
711 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
712 }
713 }
714
715 #ifdef CONFIG_IRQ_REMAP
716 static int (*iommu_ga_log_notifier)(u32);
717
718 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
719 {
720 iommu_ga_log_notifier = notifier;
721
722 return 0;
723 }
724 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
725
726 static void iommu_poll_ga_log(struct amd_iommu *iommu)
727 {
728 u32 head, tail, cnt = 0;
729
730 if (iommu->ga_log == NULL)
731 return;
732
733 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
734 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
735
736 while (head != tail) {
737 volatile u64 *raw;
738 u64 log_entry;
739
740 raw = (u64 *)(iommu->ga_log + head);
741 cnt++;
742
743 /* Avoid memcpy function-call overhead */
744 log_entry = *raw;
745
746 /* Update head pointer of hardware ring-buffer */
747 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
748 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
749
750 /* Handle GA entry */
751 switch (GA_REQ_TYPE(log_entry)) {
752 case GA_GUEST_NR:
753 if (!iommu_ga_log_notifier)
754 break;
755
756 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
757 __func__, GA_DEVID(log_entry),
758 GA_TAG(log_entry));
759
760 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
761 pr_err("AMD-Vi: GA log notifier failed.\n");
762 break;
763 default:
764 break;
765 }
766 }
767 }
768 #endif /* CONFIG_IRQ_REMAP */
769
770 #define AMD_IOMMU_INT_MASK \
771 (MMIO_STATUS_EVT_INT_MASK | \
772 MMIO_STATUS_PPR_INT_MASK | \
773 MMIO_STATUS_GALOG_INT_MASK)
774
775 irqreturn_t amd_iommu_int_thread(int irq, void *data)
776 {
777 struct amd_iommu *iommu = (struct amd_iommu *) data;
778 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
779
780 while (status & AMD_IOMMU_INT_MASK) {
781 /* Enable EVT and PPR and GA interrupts again */
782 writel(AMD_IOMMU_INT_MASK,
783 iommu->mmio_base + MMIO_STATUS_OFFSET);
784
785 if (status & MMIO_STATUS_EVT_INT_MASK) {
786 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
787 iommu_poll_events(iommu);
788 }
789
790 if (status & MMIO_STATUS_PPR_INT_MASK) {
791 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
792 iommu_poll_ppr_log(iommu);
793 }
794
795 #ifdef CONFIG_IRQ_REMAP
796 if (status & MMIO_STATUS_GALOG_INT_MASK) {
797 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
798 iommu_poll_ga_log(iommu);
799 }
800 #endif
801
802 /*
803 * Hardware bug: ERBT1312
804 * When re-enabling interrupt (by writing 1
805 * to clear the bit), the hardware might also try to set
806 * the interrupt bit in the event status register.
807 * In this scenario, the bit will be set, and disable
808 * subsequent interrupts.
809 *
810 * Workaround: The IOMMU driver should read back the
811 * status register and check if the interrupt bits are cleared.
812 * If not, driver will need to go through the interrupt handler
813 * again and re-clear the bits
814 */
815 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
816 }
817 return IRQ_HANDLED;
818 }
819
820 irqreturn_t amd_iommu_int_handler(int irq, void *data)
821 {
822 return IRQ_WAKE_THREAD;
823 }
824
825 /****************************************************************************
826 *
827 * IOMMU command queuing functions
828 *
829 ****************************************************************************/
830
831 static int wait_on_sem(volatile u64 *sem)
832 {
833 int i = 0;
834
835 while (*sem == 0 && i < LOOP_TIMEOUT) {
836 udelay(1);
837 i += 1;
838 }
839
840 if (i == LOOP_TIMEOUT) {
841 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
842 return -EIO;
843 }
844
845 return 0;
846 }
847
848 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
849 struct iommu_cmd *cmd)
850 {
851 u8 *target;
852
853 target = iommu->cmd_buf + iommu->cmd_buf_tail;
854
855 iommu->cmd_buf_tail += sizeof(*cmd);
856 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
857
858 /* Copy command to buffer */
859 memcpy(target, cmd, sizeof(*cmd));
860
861 /* Tell the IOMMU about it */
862 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
863 }
864
865 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
866 {
867 u64 paddr = iommu_virt_to_phys((void *)address);
868
869 WARN_ON(address & 0x7ULL);
870
871 memset(cmd, 0, sizeof(*cmd));
872 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
873 cmd->data[1] = upper_32_bits(paddr);
874 cmd->data[2] = 1;
875 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
876 }
877
878 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
879 {
880 memset(cmd, 0, sizeof(*cmd));
881 cmd->data[0] = devid;
882 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
883 }
884
885 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
886 size_t size, u16 domid, int pde)
887 {
888 u64 pages;
889 bool s;
890
891 pages = iommu_num_pages(address, size, PAGE_SIZE);
892 s = false;
893
894 if (pages > 1) {
895 /*
896 * If we have to flush more than one page, flush all
897 * TLB entries for this domain
898 */
899 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
900 s = true;
901 }
902
903 address &= PAGE_MASK;
904
905 memset(cmd, 0, sizeof(*cmd));
906 cmd->data[1] |= domid;
907 cmd->data[2] = lower_32_bits(address);
908 cmd->data[3] = upper_32_bits(address);
909 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
910 if (s) /* size bit - we flush more than one 4kb page */
911 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
912 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
913 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
914 }
915
916 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
917 u64 address, size_t size)
918 {
919 u64 pages;
920 bool s;
921
922 pages = iommu_num_pages(address, size, PAGE_SIZE);
923 s = false;
924
925 if (pages > 1) {
926 /*
927 * If we have to flush more than one page, flush all
928 * TLB entries for this domain
929 */
930 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
931 s = true;
932 }
933
934 address &= PAGE_MASK;
935
936 memset(cmd, 0, sizeof(*cmd));
937 cmd->data[0] = devid;
938 cmd->data[0] |= (qdep & 0xff) << 24;
939 cmd->data[1] = devid;
940 cmd->data[2] = lower_32_bits(address);
941 cmd->data[3] = upper_32_bits(address);
942 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
943 if (s)
944 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
945 }
946
947 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
948 u64 address, bool size)
949 {
950 memset(cmd, 0, sizeof(*cmd));
951
952 address &= ~(0xfffULL);
953
954 cmd->data[0] = pasid;
955 cmd->data[1] = domid;
956 cmd->data[2] = lower_32_bits(address);
957 cmd->data[3] = upper_32_bits(address);
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
960 if (size)
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
962 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
963 }
964
965 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
966 int qdep, u64 address, bool size)
967 {
968 memset(cmd, 0, sizeof(*cmd));
969
970 address &= ~(0xfffULL);
971
972 cmd->data[0] = devid;
973 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
974 cmd->data[0] |= (qdep & 0xff) << 24;
975 cmd->data[1] = devid;
976 cmd->data[1] |= (pasid & 0xff) << 16;
977 cmd->data[2] = lower_32_bits(address);
978 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
979 cmd->data[3] = upper_32_bits(address);
980 if (size)
981 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
982 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
983 }
984
985 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
986 int status, int tag, bool gn)
987 {
988 memset(cmd, 0, sizeof(*cmd));
989
990 cmd->data[0] = devid;
991 if (gn) {
992 cmd->data[1] = pasid;
993 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
994 }
995 cmd->data[3] = tag & 0x1ff;
996 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
997
998 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
999 }
1000
1001 static void build_inv_all(struct iommu_cmd *cmd)
1002 {
1003 memset(cmd, 0, sizeof(*cmd));
1004 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1005 }
1006
1007 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1008 {
1009 memset(cmd, 0, sizeof(*cmd));
1010 cmd->data[0] = devid;
1011 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1012 }
1013
1014 /*
1015 * Writes the command to the IOMMUs command buffer and informs the
1016 * hardware about the new command.
1017 */
1018 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1019 struct iommu_cmd *cmd,
1020 bool sync)
1021 {
1022 unsigned int count = 0;
1023 u32 left, next_tail;
1024
1025 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1026 again:
1027 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1028
1029 if (left <= 0x20) {
1030 /* Skip udelay() the first time around */
1031 if (count++) {
1032 if (count == LOOP_TIMEOUT) {
1033 pr_err("AMD-Vi: Command buffer timeout\n");
1034 return -EIO;
1035 }
1036
1037 udelay(1);
1038 }
1039
1040 /* Update head and recheck remaining space */
1041 iommu->cmd_buf_head = readl(iommu->mmio_base +
1042 MMIO_CMD_HEAD_OFFSET);
1043
1044 goto again;
1045 }
1046
1047 copy_cmd_to_buffer(iommu, cmd);
1048
1049 /* Do we need to make sure all commands are processed? */
1050 iommu->need_sync = sync;
1051
1052 return 0;
1053 }
1054
1055 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1056 struct iommu_cmd *cmd,
1057 bool sync)
1058 {
1059 unsigned long flags;
1060 int ret;
1061
1062 raw_spin_lock_irqsave(&iommu->lock, flags);
1063 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1064 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1065
1066 return ret;
1067 }
1068
1069 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1070 {
1071 return iommu_queue_command_sync(iommu, cmd, true);
1072 }
1073
1074 /*
1075 * This function queues a completion wait command into the command
1076 * buffer of an IOMMU
1077 */
1078 static int iommu_completion_wait(struct amd_iommu *iommu)
1079 {
1080 struct iommu_cmd cmd;
1081 unsigned long flags;
1082 int ret;
1083
1084 if (!iommu->need_sync)
1085 return 0;
1086
1087
1088 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1089
1090 raw_spin_lock_irqsave(&iommu->lock, flags);
1091
1092 iommu->cmd_sem = 0;
1093
1094 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1095 if (ret)
1096 goto out_unlock;
1097
1098 ret = wait_on_sem(&iommu->cmd_sem);
1099
1100 out_unlock:
1101 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1102
1103 return ret;
1104 }
1105
1106 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1107 {
1108 struct iommu_cmd cmd;
1109
1110 build_inv_dte(&cmd, devid);
1111
1112 return iommu_queue_command(iommu, &cmd);
1113 }
1114
1115 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1116 {
1117 u32 devid;
1118
1119 for (devid = 0; devid <= 0xffff; ++devid)
1120 iommu_flush_dte(iommu, devid);
1121
1122 iommu_completion_wait(iommu);
1123 }
1124
1125 /*
1126 * This function uses heavy locking and may disable irqs for some time. But
1127 * this is no issue because it is only called during resume.
1128 */
1129 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1130 {
1131 u32 dom_id;
1132
1133 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1134 struct iommu_cmd cmd;
1135 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1136 dom_id, 1);
1137 iommu_queue_command(iommu, &cmd);
1138 }
1139
1140 iommu_completion_wait(iommu);
1141 }
1142
1143 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1144 {
1145 struct iommu_cmd cmd;
1146
1147 build_inv_all(&cmd);
1148
1149 iommu_queue_command(iommu, &cmd);
1150 iommu_completion_wait(iommu);
1151 }
1152
1153 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1154 {
1155 struct iommu_cmd cmd;
1156
1157 build_inv_irt(&cmd, devid);
1158
1159 iommu_queue_command(iommu, &cmd);
1160 }
1161
1162 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1163 {
1164 u32 devid;
1165
1166 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1167 iommu_flush_irt(iommu, devid);
1168
1169 iommu_completion_wait(iommu);
1170 }
1171
1172 void iommu_flush_all_caches(struct amd_iommu *iommu)
1173 {
1174 if (iommu_feature(iommu, FEATURE_IA)) {
1175 amd_iommu_flush_all(iommu);
1176 } else {
1177 amd_iommu_flush_dte_all(iommu);
1178 amd_iommu_flush_irt_all(iommu);
1179 amd_iommu_flush_tlb_all(iommu);
1180 }
1181 }
1182
1183 /*
1184 * Command send function for flushing on-device TLB
1185 */
1186 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1187 u64 address, size_t size)
1188 {
1189 struct amd_iommu *iommu;
1190 struct iommu_cmd cmd;
1191 int qdep;
1192
1193 qdep = dev_data->ats.qdep;
1194 iommu = amd_iommu_rlookup_table[dev_data->devid];
1195
1196 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1197
1198 return iommu_queue_command(iommu, &cmd);
1199 }
1200
1201 /*
1202 * Command send function for invalidating a device table entry
1203 */
1204 static int device_flush_dte(struct iommu_dev_data *dev_data)
1205 {
1206 struct amd_iommu *iommu;
1207 u16 alias;
1208 int ret;
1209
1210 iommu = amd_iommu_rlookup_table[dev_data->devid];
1211 alias = dev_data->alias;
1212
1213 ret = iommu_flush_dte(iommu, dev_data->devid);
1214 if (!ret && alias != dev_data->devid)
1215 ret = iommu_flush_dte(iommu, alias);
1216 if (ret)
1217 return ret;
1218
1219 if (dev_data->ats.enabled)
1220 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1221
1222 return ret;
1223 }
1224
1225 /*
1226 * TLB invalidation function which is called from the mapping functions.
1227 * It invalidates a single PTE if the range to flush is within a single
1228 * page. Otherwise it flushes the whole TLB of the IOMMU.
1229 */
1230 static void __domain_flush_pages(struct protection_domain *domain,
1231 u64 address, size_t size, int pde)
1232 {
1233 struct iommu_dev_data *dev_data;
1234 struct iommu_cmd cmd;
1235 int ret = 0, i;
1236
1237 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1238
1239 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1240 if (!domain->dev_iommu[i])
1241 continue;
1242
1243 /*
1244 * Devices of this domain are behind this IOMMU
1245 * We need a TLB flush
1246 */
1247 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1248 }
1249
1250 list_for_each_entry(dev_data, &domain->dev_list, list) {
1251
1252 if (!dev_data->ats.enabled)
1253 continue;
1254
1255 ret |= device_flush_iotlb(dev_data, address, size);
1256 }
1257
1258 WARN_ON(ret);
1259 }
1260
1261 static void domain_flush_pages(struct protection_domain *domain,
1262 u64 address, size_t size)
1263 {
1264 __domain_flush_pages(domain, address, size, 0);
1265 }
1266
1267 /* Flush the whole IO/TLB for a given protection domain */
1268 static void domain_flush_tlb(struct protection_domain *domain)
1269 {
1270 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1271 }
1272
1273 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1274 static void domain_flush_tlb_pde(struct protection_domain *domain)
1275 {
1276 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1277 }
1278
1279 static void domain_flush_complete(struct protection_domain *domain)
1280 {
1281 int i;
1282
1283 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1284 if (domain && !domain->dev_iommu[i])
1285 continue;
1286
1287 /*
1288 * Devices of this domain are behind this IOMMU
1289 * We need to wait for completion of all commands.
1290 */
1291 iommu_completion_wait(amd_iommus[i]);
1292 }
1293 }
1294
1295
1296 /*
1297 * This function flushes the DTEs for all devices in domain
1298 */
1299 static void domain_flush_devices(struct protection_domain *domain)
1300 {
1301 struct iommu_dev_data *dev_data;
1302
1303 list_for_each_entry(dev_data, &domain->dev_list, list)
1304 device_flush_dte(dev_data);
1305 }
1306
1307 /****************************************************************************
1308 *
1309 * The functions below are used the create the page table mappings for
1310 * unity mapped regions.
1311 *
1312 ****************************************************************************/
1313
1314 /*
1315 * This function is used to add another level to an IO page table. Adding
1316 * another level increases the size of the address space by 9 bits to a size up
1317 * to 64 bits.
1318 */
1319 static bool increase_address_space(struct protection_domain *domain,
1320 gfp_t gfp)
1321 {
1322 u64 *pte;
1323
1324 if (domain->mode == PAGE_MODE_6_LEVEL)
1325 /* address space already 64 bit large */
1326 return false;
1327
1328 pte = (void *)get_zeroed_page(gfp);
1329 if (!pte)
1330 return false;
1331
1332 *pte = PM_LEVEL_PDE(domain->mode,
1333 iommu_virt_to_phys(domain->pt_root));
1334 domain->pt_root = pte;
1335 domain->mode += 1;
1336 domain->updated = true;
1337
1338 return true;
1339 }
1340
1341 static u64 *alloc_pte(struct protection_domain *domain,
1342 unsigned long address,
1343 unsigned long page_size,
1344 u64 **pte_page,
1345 gfp_t gfp)
1346 {
1347 int level, end_lvl;
1348 u64 *pte, *page;
1349
1350 BUG_ON(!is_power_of_2(page_size));
1351
1352 while (address > PM_LEVEL_SIZE(domain->mode))
1353 increase_address_space(domain, gfp);
1354
1355 level = domain->mode - 1;
1356 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1357 address = PAGE_SIZE_ALIGN(address, page_size);
1358 end_lvl = PAGE_SIZE_LEVEL(page_size);
1359
1360 while (level > end_lvl) {
1361 u64 __pte, __npte;
1362
1363 __pte = *pte;
1364
1365 if (!IOMMU_PTE_PRESENT(__pte)) {
1366 page = (u64 *)get_zeroed_page(gfp);
1367 if (!page)
1368 return NULL;
1369
1370 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1371
1372 /* pte could have been changed somewhere. */
1373 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1374 free_page((unsigned long)page);
1375 continue;
1376 }
1377 }
1378
1379 /* No level skipping support yet */
1380 if (PM_PTE_LEVEL(*pte) != level)
1381 return NULL;
1382
1383 level -= 1;
1384
1385 pte = IOMMU_PTE_PAGE(*pte);
1386
1387 if (pte_page && level == end_lvl)
1388 *pte_page = pte;
1389
1390 pte = &pte[PM_LEVEL_INDEX(level, address)];
1391 }
1392
1393 return pte;
1394 }
1395
1396 /*
1397 * This function checks if there is a PTE for a given dma address. If
1398 * there is one, it returns the pointer to it.
1399 */
1400 static u64 *fetch_pte(struct protection_domain *domain,
1401 unsigned long address,
1402 unsigned long *page_size)
1403 {
1404 int level;
1405 u64 *pte;
1406
1407 *page_size = 0;
1408
1409 if (address > PM_LEVEL_SIZE(domain->mode))
1410 return NULL;
1411
1412 level = domain->mode - 1;
1413 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1414 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1415
1416 while (level > 0) {
1417
1418 /* Not Present */
1419 if (!IOMMU_PTE_PRESENT(*pte))
1420 return NULL;
1421
1422 /* Large PTE */
1423 if (PM_PTE_LEVEL(*pte) == 7 ||
1424 PM_PTE_LEVEL(*pte) == 0)
1425 break;
1426
1427 /* No level skipping support yet */
1428 if (PM_PTE_LEVEL(*pte) != level)
1429 return NULL;
1430
1431 level -= 1;
1432
1433 /* Walk to the next level */
1434 pte = IOMMU_PTE_PAGE(*pte);
1435 pte = &pte[PM_LEVEL_INDEX(level, address)];
1436 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1437 }
1438
1439 if (PM_PTE_LEVEL(*pte) == 0x07) {
1440 unsigned long pte_mask;
1441
1442 /*
1443 * If we have a series of large PTEs, make
1444 * sure to return a pointer to the first one.
1445 */
1446 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1447 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1448 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1449 }
1450
1451 return pte;
1452 }
1453
1454 /*
1455 * Generic mapping functions. It maps a physical address into a DMA
1456 * address space. It allocates the page table pages if necessary.
1457 * In the future it can be extended to a generic mapping function
1458 * supporting all features of AMD IOMMU page tables like level skipping
1459 * and full 64 bit address spaces.
1460 */
1461 static int iommu_map_page(struct protection_domain *dom,
1462 unsigned long bus_addr,
1463 unsigned long phys_addr,
1464 unsigned long page_size,
1465 int prot,
1466 gfp_t gfp)
1467 {
1468 u64 __pte, *pte;
1469 int i, count;
1470
1471 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1472 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1473
1474 if (!(prot & IOMMU_PROT_MASK))
1475 return -EINVAL;
1476
1477 count = PAGE_SIZE_PTE_COUNT(page_size);
1478 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1479
1480 if (!pte)
1481 return -ENOMEM;
1482
1483 for (i = 0; i < count; ++i)
1484 if (IOMMU_PTE_PRESENT(pte[i]))
1485 return -EBUSY;
1486
1487 if (count > 1) {
1488 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1489 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1490 } else
1491 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1492
1493 if (prot & IOMMU_PROT_IR)
1494 __pte |= IOMMU_PTE_IR;
1495 if (prot & IOMMU_PROT_IW)
1496 __pte |= IOMMU_PTE_IW;
1497
1498 for (i = 0; i < count; ++i)
1499 pte[i] = __pte;
1500
1501 update_domain(dom);
1502
1503 return 0;
1504 }
1505
1506 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1507 unsigned long bus_addr,
1508 unsigned long page_size)
1509 {
1510 unsigned long long unmapped;
1511 unsigned long unmap_size;
1512 u64 *pte;
1513
1514 BUG_ON(!is_power_of_2(page_size));
1515
1516 unmapped = 0;
1517
1518 while (unmapped < page_size) {
1519
1520 pte = fetch_pte(dom, bus_addr, &unmap_size);
1521
1522 if (pte) {
1523 int i, count;
1524
1525 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1526 for (i = 0; i < count; i++)
1527 pte[i] = 0ULL;
1528 }
1529
1530 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1531 unmapped += unmap_size;
1532 }
1533
1534 BUG_ON(unmapped && !is_power_of_2(unmapped));
1535
1536 return unmapped;
1537 }
1538
1539 /****************************************************************************
1540 *
1541 * The next functions belong to the address allocator for the dma_ops
1542 * interface functions.
1543 *
1544 ****************************************************************************/
1545
1546
1547 static unsigned long dma_ops_alloc_iova(struct device *dev,
1548 struct dma_ops_domain *dma_dom,
1549 unsigned int pages, u64 dma_mask)
1550 {
1551 unsigned long pfn = 0;
1552
1553 pages = __roundup_pow_of_two(pages);
1554
1555 if (dma_mask > DMA_BIT_MASK(32))
1556 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1557 IOVA_PFN(DMA_BIT_MASK(32)), false);
1558
1559 if (!pfn)
1560 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1561 IOVA_PFN(dma_mask), true);
1562
1563 return (pfn << PAGE_SHIFT);
1564 }
1565
1566 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1567 unsigned long address,
1568 unsigned int pages)
1569 {
1570 pages = __roundup_pow_of_two(pages);
1571 address >>= PAGE_SHIFT;
1572
1573 free_iova_fast(&dma_dom->iovad, address, pages);
1574 }
1575
1576 /****************************************************************************
1577 *
1578 * The next functions belong to the domain allocation. A domain is
1579 * allocated for every IOMMU as the default domain. If device isolation
1580 * is enabled, every device get its own domain. The most important thing
1581 * about domains is the page table mapping the DMA address space they
1582 * contain.
1583 *
1584 ****************************************************************************/
1585
1586 /*
1587 * This function adds a protection domain to the global protection domain list
1588 */
1589 static void add_domain_to_list(struct protection_domain *domain)
1590 {
1591 unsigned long flags;
1592
1593 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1594 list_add(&domain->list, &amd_iommu_pd_list);
1595 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1596 }
1597
1598 /*
1599 * This function removes a protection domain to the global
1600 * protection domain list
1601 */
1602 static void del_domain_from_list(struct protection_domain *domain)
1603 {
1604 unsigned long flags;
1605
1606 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1607 list_del(&domain->list);
1608 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1609 }
1610
1611 static u16 domain_id_alloc(void)
1612 {
1613 int id;
1614
1615 spin_lock(&pd_bitmap_lock);
1616 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1617 BUG_ON(id == 0);
1618 if (id > 0 && id < MAX_DOMAIN_ID)
1619 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1620 else
1621 id = 0;
1622 spin_unlock(&pd_bitmap_lock);
1623
1624 return id;
1625 }
1626
1627 static void domain_id_free(int id)
1628 {
1629 spin_lock(&pd_bitmap_lock);
1630 if (id > 0 && id < MAX_DOMAIN_ID)
1631 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1632 spin_unlock(&pd_bitmap_lock);
1633 }
1634
1635 #define DEFINE_FREE_PT_FN(LVL, FN) \
1636 static void free_pt_##LVL (unsigned long __pt) \
1637 { \
1638 unsigned long p; \
1639 u64 *pt; \
1640 int i; \
1641 \
1642 pt = (u64 *)__pt; \
1643 \
1644 for (i = 0; i < 512; ++i) { \
1645 /* PTE present? */ \
1646 if (!IOMMU_PTE_PRESENT(pt[i])) \
1647 continue; \
1648 \
1649 /* Large PTE? */ \
1650 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1651 PM_PTE_LEVEL(pt[i]) == 7) \
1652 continue; \
1653 \
1654 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1655 FN(p); \
1656 } \
1657 free_page((unsigned long)pt); \
1658 }
1659
1660 DEFINE_FREE_PT_FN(l2, free_page)
1661 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1662 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1663 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1664 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1665
1666 static void free_pagetable(struct protection_domain *domain)
1667 {
1668 unsigned long root = (unsigned long)domain->pt_root;
1669
1670 switch (domain->mode) {
1671 case PAGE_MODE_NONE:
1672 break;
1673 case PAGE_MODE_1_LEVEL:
1674 free_page(root);
1675 break;
1676 case PAGE_MODE_2_LEVEL:
1677 free_pt_l2(root);
1678 break;
1679 case PAGE_MODE_3_LEVEL:
1680 free_pt_l3(root);
1681 break;
1682 case PAGE_MODE_4_LEVEL:
1683 free_pt_l4(root);
1684 break;
1685 case PAGE_MODE_5_LEVEL:
1686 free_pt_l5(root);
1687 break;
1688 case PAGE_MODE_6_LEVEL:
1689 free_pt_l6(root);
1690 break;
1691 default:
1692 BUG();
1693 }
1694 }
1695
1696 static void free_gcr3_tbl_level1(u64 *tbl)
1697 {
1698 u64 *ptr;
1699 int i;
1700
1701 for (i = 0; i < 512; ++i) {
1702 if (!(tbl[i] & GCR3_VALID))
1703 continue;
1704
1705 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1706
1707 free_page((unsigned long)ptr);
1708 }
1709 }
1710
1711 static void free_gcr3_tbl_level2(u64 *tbl)
1712 {
1713 u64 *ptr;
1714 int i;
1715
1716 for (i = 0; i < 512; ++i) {
1717 if (!(tbl[i] & GCR3_VALID))
1718 continue;
1719
1720 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1721
1722 free_gcr3_tbl_level1(ptr);
1723 }
1724 }
1725
1726 static void free_gcr3_table(struct protection_domain *domain)
1727 {
1728 if (domain->glx == 2)
1729 free_gcr3_tbl_level2(domain->gcr3_tbl);
1730 else if (domain->glx == 1)
1731 free_gcr3_tbl_level1(domain->gcr3_tbl);
1732 else
1733 BUG_ON(domain->glx != 0);
1734
1735 free_page((unsigned long)domain->gcr3_tbl);
1736 }
1737
1738 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1739 {
1740 domain_flush_tlb(&dom->domain);
1741 domain_flush_complete(&dom->domain);
1742 }
1743
1744 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1745 {
1746 struct dma_ops_domain *dom;
1747
1748 dom = container_of(iovad, struct dma_ops_domain, iovad);
1749
1750 dma_ops_domain_flush_tlb(dom);
1751 }
1752
1753 /*
1754 * Free a domain, only used if something went wrong in the
1755 * allocation path and we need to free an already allocated page table
1756 */
1757 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1758 {
1759 if (!dom)
1760 return;
1761
1762 del_domain_from_list(&dom->domain);
1763
1764 put_iova_domain(&dom->iovad);
1765
1766 free_pagetable(&dom->domain);
1767
1768 if (dom->domain.id)
1769 domain_id_free(dom->domain.id);
1770
1771 kfree(dom);
1772 }
1773
1774 /*
1775 * Allocates a new protection domain usable for the dma_ops functions.
1776 * It also initializes the page table and the address allocator data
1777 * structures required for the dma_ops interface
1778 */
1779 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1780 {
1781 struct dma_ops_domain *dma_dom;
1782
1783 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1784 if (!dma_dom)
1785 return NULL;
1786
1787 if (protection_domain_init(&dma_dom->domain))
1788 goto free_dma_dom;
1789
1790 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1791 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1792 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1793 if (!dma_dom->domain.pt_root)
1794 goto free_dma_dom;
1795
1796 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1797
1798 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1799 goto free_dma_dom;
1800
1801 /* Initialize reserved ranges */
1802 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1803
1804 add_domain_to_list(&dma_dom->domain);
1805
1806 return dma_dom;
1807
1808 free_dma_dom:
1809 dma_ops_domain_free(dma_dom);
1810
1811 return NULL;
1812 }
1813
1814 /*
1815 * little helper function to check whether a given protection domain is a
1816 * dma_ops domain
1817 */
1818 static bool dma_ops_domain(struct protection_domain *domain)
1819 {
1820 return domain->flags & PD_DMA_OPS_MASK;
1821 }
1822
1823 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1824 bool ats, bool ppr)
1825 {
1826 u64 pte_root = 0;
1827 u64 flags = 0;
1828
1829 if (domain->mode != PAGE_MODE_NONE)
1830 pte_root = iommu_virt_to_phys(domain->pt_root);
1831
1832 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1833 << DEV_ENTRY_MODE_SHIFT;
1834 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1835
1836 flags = amd_iommu_dev_table[devid].data[1];
1837
1838 if (ats)
1839 flags |= DTE_FLAG_IOTLB;
1840
1841 if (ppr) {
1842 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1843
1844 if (iommu_feature(iommu, FEATURE_EPHSUP))
1845 pte_root |= 1ULL << DEV_ENTRY_PPR;
1846 }
1847
1848 if (domain->flags & PD_IOMMUV2_MASK) {
1849 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1850 u64 glx = domain->glx;
1851 u64 tmp;
1852
1853 pte_root |= DTE_FLAG_GV;
1854 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1855
1856 /* First mask out possible old values for GCR3 table */
1857 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1858 flags &= ~tmp;
1859
1860 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1861 flags &= ~tmp;
1862
1863 /* Encode GCR3 table into DTE */
1864 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1865 pte_root |= tmp;
1866
1867 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1868 flags |= tmp;
1869
1870 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1871 flags |= tmp;
1872 }
1873
1874 flags &= ~DEV_DOMID_MASK;
1875 flags |= domain->id;
1876
1877 amd_iommu_dev_table[devid].data[1] = flags;
1878 amd_iommu_dev_table[devid].data[0] = pte_root;
1879 }
1880
1881 static void clear_dte_entry(u16 devid)
1882 {
1883 /* remove entry from the device table seen by the hardware */
1884 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1885 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1886
1887 amd_iommu_apply_erratum_63(devid);
1888 }
1889
1890 static void do_attach(struct iommu_dev_data *dev_data,
1891 struct protection_domain *domain)
1892 {
1893 struct amd_iommu *iommu;
1894 u16 alias;
1895 bool ats;
1896
1897 iommu = amd_iommu_rlookup_table[dev_data->devid];
1898 alias = dev_data->alias;
1899 ats = dev_data->ats.enabled;
1900
1901 /* Update data structures */
1902 dev_data->domain = domain;
1903 list_add(&dev_data->list, &domain->dev_list);
1904
1905 /* Do reference counting */
1906 domain->dev_iommu[iommu->index] += 1;
1907 domain->dev_cnt += 1;
1908
1909 /* Update device table */
1910 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1911 if (alias != dev_data->devid)
1912 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1913
1914 device_flush_dte(dev_data);
1915 }
1916
1917 static void do_detach(struct iommu_dev_data *dev_data)
1918 {
1919 struct amd_iommu *iommu;
1920 u16 alias;
1921
1922 iommu = amd_iommu_rlookup_table[dev_data->devid];
1923 alias = dev_data->alias;
1924
1925 /* decrease reference counters */
1926 dev_data->domain->dev_iommu[iommu->index] -= 1;
1927 dev_data->domain->dev_cnt -= 1;
1928
1929 /* Update data structures */
1930 dev_data->domain = NULL;
1931 list_del(&dev_data->list);
1932 clear_dte_entry(dev_data->devid);
1933 if (alias != dev_data->devid)
1934 clear_dte_entry(alias);
1935
1936 /* Flush the DTE entry */
1937 device_flush_dte(dev_data);
1938 }
1939
1940 /*
1941 * If a device is not yet associated with a domain, this function makes the
1942 * device visible in the domain
1943 */
1944 static int __attach_device(struct iommu_dev_data *dev_data,
1945 struct protection_domain *domain)
1946 {
1947 int ret;
1948
1949 /* lock domain */
1950 spin_lock(&domain->lock);
1951
1952 ret = -EBUSY;
1953 if (dev_data->domain != NULL)
1954 goto out_unlock;
1955
1956 /* Attach alias group root */
1957 do_attach(dev_data, domain);
1958
1959 ret = 0;
1960
1961 out_unlock:
1962
1963 /* ready */
1964 spin_unlock(&domain->lock);
1965
1966 return ret;
1967 }
1968
1969
1970 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1971 {
1972 pci_disable_ats(pdev);
1973 pci_disable_pri(pdev);
1974 pci_disable_pasid(pdev);
1975 }
1976
1977 /* FIXME: Change generic reset-function to do the same */
1978 static int pri_reset_while_enabled(struct pci_dev *pdev)
1979 {
1980 u16 control;
1981 int pos;
1982
1983 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1984 if (!pos)
1985 return -EINVAL;
1986
1987 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1988 control |= PCI_PRI_CTRL_RESET;
1989 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1990
1991 return 0;
1992 }
1993
1994 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1995 {
1996 bool reset_enable;
1997 int reqs, ret;
1998
1999 /* FIXME: Hardcode number of outstanding requests for now */
2000 reqs = 32;
2001 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2002 reqs = 1;
2003 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2004
2005 /* Only allow access to user-accessible pages */
2006 ret = pci_enable_pasid(pdev, 0);
2007 if (ret)
2008 goto out_err;
2009
2010 /* First reset the PRI state of the device */
2011 ret = pci_reset_pri(pdev);
2012 if (ret)
2013 goto out_err;
2014
2015 /* Enable PRI */
2016 ret = pci_enable_pri(pdev, reqs);
2017 if (ret)
2018 goto out_err;
2019
2020 if (reset_enable) {
2021 ret = pri_reset_while_enabled(pdev);
2022 if (ret)
2023 goto out_err;
2024 }
2025
2026 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2027 if (ret)
2028 goto out_err;
2029
2030 return 0;
2031
2032 out_err:
2033 pci_disable_pri(pdev);
2034 pci_disable_pasid(pdev);
2035
2036 return ret;
2037 }
2038
2039 /* FIXME: Move this to PCI code */
2040 #define PCI_PRI_TLP_OFF (1 << 15)
2041
2042 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2043 {
2044 u16 status;
2045 int pos;
2046
2047 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2048 if (!pos)
2049 return false;
2050
2051 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2052
2053 return (status & PCI_PRI_TLP_OFF) ? true : false;
2054 }
2055
2056 /*
2057 * If a device is not yet associated with a domain, this function makes the
2058 * device visible in the domain
2059 */
2060 static int attach_device(struct device *dev,
2061 struct protection_domain *domain)
2062 {
2063 struct pci_dev *pdev;
2064 struct iommu_dev_data *dev_data;
2065 unsigned long flags;
2066 int ret;
2067
2068 dev_data = get_dev_data(dev);
2069
2070 if (!dev_is_pci(dev))
2071 goto skip_ats_check;
2072
2073 pdev = to_pci_dev(dev);
2074 if (domain->flags & PD_IOMMUV2_MASK) {
2075 if (!dev_data->passthrough)
2076 return -EINVAL;
2077
2078 if (dev_data->iommu_v2) {
2079 if (pdev_iommuv2_enable(pdev) != 0)
2080 return -EINVAL;
2081
2082 dev_data->ats.enabled = true;
2083 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2084 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2085 }
2086 } else if (amd_iommu_iotlb_sup &&
2087 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2088 dev_data->ats.enabled = true;
2089 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2090 }
2091
2092 skip_ats_check:
2093 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2094 ret = __attach_device(dev_data, domain);
2095 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2096
2097 /*
2098 * We might boot into a crash-kernel here. The crashed kernel
2099 * left the caches in the IOMMU dirty. So we have to flush
2100 * here to evict all dirty stuff.
2101 */
2102 domain_flush_tlb_pde(domain);
2103
2104 return ret;
2105 }
2106
2107 /*
2108 * Removes a device from a protection domain (unlocked)
2109 */
2110 static void __detach_device(struct iommu_dev_data *dev_data)
2111 {
2112 struct protection_domain *domain;
2113
2114 domain = dev_data->domain;
2115
2116 spin_lock(&domain->lock);
2117
2118 do_detach(dev_data);
2119
2120 spin_unlock(&domain->lock);
2121 }
2122
2123 /*
2124 * Removes a device from a protection domain (with devtable_lock held)
2125 */
2126 static void detach_device(struct device *dev)
2127 {
2128 struct protection_domain *domain;
2129 struct iommu_dev_data *dev_data;
2130 unsigned long flags;
2131
2132 dev_data = get_dev_data(dev);
2133 domain = dev_data->domain;
2134
2135 /*
2136 * First check if the device is still attached. It might already
2137 * be detached from its domain because the generic
2138 * iommu_detach_group code detached it and we try again here in
2139 * our alias handling.
2140 */
2141 if (WARN_ON(!dev_data->domain))
2142 return;
2143
2144 /* lock device table */
2145 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2146 __detach_device(dev_data);
2147 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2148
2149 if (!dev_is_pci(dev))
2150 return;
2151
2152 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2153 pdev_iommuv2_disable(to_pci_dev(dev));
2154 else if (dev_data->ats.enabled)
2155 pci_disable_ats(to_pci_dev(dev));
2156
2157 dev_data->ats.enabled = false;
2158 }
2159
2160 static int amd_iommu_add_device(struct device *dev)
2161 {
2162 struct iommu_dev_data *dev_data;
2163 struct iommu_domain *domain;
2164 struct amd_iommu *iommu;
2165 int ret, devid;
2166
2167 if (!check_device(dev) || get_dev_data(dev))
2168 return 0;
2169
2170 devid = get_device_id(dev);
2171 if (devid < 0)
2172 return devid;
2173
2174 iommu = amd_iommu_rlookup_table[devid];
2175
2176 ret = iommu_init_device(dev);
2177 if (ret) {
2178 if (ret != -ENOTSUPP)
2179 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2180 dev_name(dev));
2181
2182 iommu_ignore_device(dev);
2183 dev->dma_ops = &dma_direct_ops;
2184 goto out;
2185 }
2186 init_iommu_group(dev);
2187
2188 dev_data = get_dev_data(dev);
2189
2190 BUG_ON(!dev_data);
2191
2192 if (iommu_pass_through || dev_data->iommu_v2)
2193 iommu_request_dm_for_dev(dev);
2194
2195 /* Domains are initialized for this device - have a look what we ended up with */
2196 domain = iommu_get_domain_for_dev(dev);
2197 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2198 dev_data->passthrough = true;
2199 else
2200 dev->dma_ops = &amd_iommu_dma_ops;
2201
2202 out:
2203 iommu_completion_wait(iommu);
2204
2205 return 0;
2206 }
2207
2208 static void amd_iommu_remove_device(struct device *dev)
2209 {
2210 struct amd_iommu *iommu;
2211 int devid;
2212
2213 if (!check_device(dev))
2214 return;
2215
2216 devid = get_device_id(dev);
2217 if (devid < 0)
2218 return;
2219
2220 iommu = amd_iommu_rlookup_table[devid];
2221
2222 iommu_uninit_device(dev);
2223 iommu_completion_wait(iommu);
2224 }
2225
2226 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2227 {
2228 if (dev_is_pci(dev))
2229 return pci_device_group(dev);
2230
2231 return acpihid_device_group(dev);
2232 }
2233
2234 /*****************************************************************************
2235 *
2236 * The next functions belong to the dma_ops mapping/unmapping code.
2237 *
2238 *****************************************************************************/
2239
2240 /*
2241 * In the dma_ops path we only have the struct device. This function
2242 * finds the corresponding IOMMU, the protection domain and the
2243 * requestor id for a given device.
2244 * If the device is not yet associated with a domain this is also done
2245 * in this function.
2246 */
2247 static struct protection_domain *get_domain(struct device *dev)
2248 {
2249 struct protection_domain *domain;
2250 struct iommu_domain *io_domain;
2251
2252 if (!check_device(dev))
2253 return ERR_PTR(-EINVAL);
2254
2255 domain = get_dev_data(dev)->domain;
2256 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2257 get_dev_data(dev)->defer_attach = false;
2258 io_domain = iommu_get_domain_for_dev(dev);
2259 domain = to_pdomain(io_domain);
2260 attach_device(dev, domain);
2261 }
2262 if (domain == NULL)
2263 return ERR_PTR(-EBUSY);
2264
2265 if (!dma_ops_domain(domain))
2266 return ERR_PTR(-EBUSY);
2267
2268 return domain;
2269 }
2270
2271 static void update_device_table(struct protection_domain *domain)
2272 {
2273 struct iommu_dev_data *dev_data;
2274
2275 list_for_each_entry(dev_data, &domain->dev_list, list) {
2276 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2277 dev_data->iommu_v2);
2278
2279 if (dev_data->devid == dev_data->alias)
2280 continue;
2281
2282 /* There is an alias, update device table entry for it */
2283 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2284 dev_data->iommu_v2);
2285 }
2286 }
2287
2288 static void update_domain(struct protection_domain *domain)
2289 {
2290 if (!domain->updated)
2291 return;
2292
2293 update_device_table(domain);
2294
2295 domain_flush_devices(domain);
2296 domain_flush_tlb_pde(domain);
2297
2298 domain->updated = false;
2299 }
2300
2301 static int dir2prot(enum dma_data_direction direction)
2302 {
2303 if (direction == DMA_TO_DEVICE)
2304 return IOMMU_PROT_IR;
2305 else if (direction == DMA_FROM_DEVICE)
2306 return IOMMU_PROT_IW;
2307 else if (direction == DMA_BIDIRECTIONAL)
2308 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2309 else
2310 return 0;
2311 }
2312
2313 /*
2314 * This function contains common code for mapping of a physically
2315 * contiguous memory region into DMA address space. It is used by all
2316 * mapping functions provided with this IOMMU driver.
2317 * Must be called with the domain lock held.
2318 */
2319 static dma_addr_t __map_single(struct device *dev,
2320 struct dma_ops_domain *dma_dom,
2321 phys_addr_t paddr,
2322 size_t size,
2323 enum dma_data_direction direction,
2324 u64 dma_mask)
2325 {
2326 dma_addr_t offset = paddr & ~PAGE_MASK;
2327 dma_addr_t address, start, ret;
2328 unsigned int pages;
2329 int prot = 0;
2330 int i;
2331
2332 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2333 paddr &= PAGE_MASK;
2334
2335 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2336 if (address == AMD_IOMMU_MAPPING_ERROR)
2337 goto out;
2338
2339 prot = dir2prot(direction);
2340
2341 start = address;
2342 for (i = 0; i < pages; ++i) {
2343 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2344 PAGE_SIZE, prot, GFP_ATOMIC);
2345 if (ret)
2346 goto out_unmap;
2347
2348 paddr += PAGE_SIZE;
2349 start += PAGE_SIZE;
2350 }
2351 address += offset;
2352
2353 if (unlikely(amd_iommu_np_cache)) {
2354 domain_flush_pages(&dma_dom->domain, address, size);
2355 domain_flush_complete(&dma_dom->domain);
2356 }
2357
2358 out:
2359 return address;
2360
2361 out_unmap:
2362
2363 for (--i; i >= 0; --i) {
2364 start -= PAGE_SIZE;
2365 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2366 }
2367
2368 domain_flush_tlb(&dma_dom->domain);
2369 domain_flush_complete(&dma_dom->domain);
2370
2371 dma_ops_free_iova(dma_dom, address, pages);
2372
2373 return AMD_IOMMU_MAPPING_ERROR;
2374 }
2375
2376 /*
2377 * Does the reverse of the __map_single function. Must be called with
2378 * the domain lock held too
2379 */
2380 static void __unmap_single(struct dma_ops_domain *dma_dom,
2381 dma_addr_t dma_addr,
2382 size_t size,
2383 int dir)
2384 {
2385 dma_addr_t i, start;
2386 unsigned int pages;
2387
2388 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2389 dma_addr &= PAGE_MASK;
2390 start = dma_addr;
2391
2392 for (i = 0; i < pages; ++i) {
2393 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2394 start += PAGE_SIZE;
2395 }
2396
2397 if (amd_iommu_unmap_flush) {
2398 domain_flush_tlb(&dma_dom->domain);
2399 domain_flush_complete(&dma_dom->domain);
2400 dma_ops_free_iova(dma_dom, dma_addr, pages);
2401 } else {
2402 pages = __roundup_pow_of_two(pages);
2403 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2404 }
2405 }
2406
2407 /*
2408 * The exported map_single function for dma_ops.
2409 */
2410 static dma_addr_t map_page(struct device *dev, struct page *page,
2411 unsigned long offset, size_t size,
2412 enum dma_data_direction dir,
2413 unsigned long attrs)
2414 {
2415 phys_addr_t paddr = page_to_phys(page) + offset;
2416 struct protection_domain *domain;
2417 struct dma_ops_domain *dma_dom;
2418 u64 dma_mask;
2419
2420 domain = get_domain(dev);
2421 if (PTR_ERR(domain) == -EINVAL)
2422 return (dma_addr_t)paddr;
2423 else if (IS_ERR(domain))
2424 return AMD_IOMMU_MAPPING_ERROR;
2425
2426 dma_mask = *dev->dma_mask;
2427 dma_dom = to_dma_ops_domain(domain);
2428
2429 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2430 }
2431
2432 /*
2433 * The exported unmap_single function for dma_ops.
2434 */
2435 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2436 enum dma_data_direction dir, unsigned long attrs)
2437 {
2438 struct protection_domain *domain;
2439 struct dma_ops_domain *dma_dom;
2440
2441 domain = get_domain(dev);
2442 if (IS_ERR(domain))
2443 return;
2444
2445 dma_dom = to_dma_ops_domain(domain);
2446
2447 __unmap_single(dma_dom, dma_addr, size, dir);
2448 }
2449
2450 static int sg_num_pages(struct device *dev,
2451 struct scatterlist *sglist,
2452 int nelems)
2453 {
2454 unsigned long mask, boundary_size;
2455 struct scatterlist *s;
2456 int i, npages = 0;
2457
2458 mask = dma_get_seg_boundary(dev);
2459 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2460 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2461
2462 for_each_sg(sglist, s, nelems, i) {
2463 int p, n;
2464
2465 s->dma_address = npages << PAGE_SHIFT;
2466 p = npages % boundary_size;
2467 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2468 if (p + n > boundary_size)
2469 npages += boundary_size - p;
2470 npages += n;
2471 }
2472
2473 return npages;
2474 }
2475
2476 /*
2477 * The exported map_sg function for dma_ops (handles scatter-gather
2478 * lists).
2479 */
2480 static int map_sg(struct device *dev, struct scatterlist *sglist,
2481 int nelems, enum dma_data_direction direction,
2482 unsigned long attrs)
2483 {
2484 int mapped_pages = 0, npages = 0, prot = 0, i;
2485 struct protection_domain *domain;
2486 struct dma_ops_domain *dma_dom;
2487 struct scatterlist *s;
2488 unsigned long address;
2489 u64 dma_mask;
2490
2491 domain = get_domain(dev);
2492 if (IS_ERR(domain))
2493 return 0;
2494
2495 dma_dom = to_dma_ops_domain(domain);
2496 dma_mask = *dev->dma_mask;
2497
2498 npages = sg_num_pages(dev, sglist, nelems);
2499
2500 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2501 if (address == AMD_IOMMU_MAPPING_ERROR)
2502 goto out_err;
2503
2504 prot = dir2prot(direction);
2505
2506 /* Map all sg entries */
2507 for_each_sg(sglist, s, nelems, i) {
2508 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2509
2510 for (j = 0; j < pages; ++j) {
2511 unsigned long bus_addr, phys_addr;
2512 int ret;
2513
2514 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2515 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2516 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2517 if (ret)
2518 goto out_unmap;
2519
2520 mapped_pages += 1;
2521 }
2522 }
2523
2524 /* Everything is mapped - write the right values into s->dma_address */
2525 for_each_sg(sglist, s, nelems, i) {
2526 s->dma_address += address + s->offset;
2527 s->dma_length = s->length;
2528 }
2529
2530 return nelems;
2531
2532 out_unmap:
2533 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2534 dev_name(dev), npages);
2535
2536 for_each_sg(sglist, s, nelems, i) {
2537 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2538
2539 for (j = 0; j < pages; ++j) {
2540 unsigned long bus_addr;
2541
2542 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2543 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2544
2545 if (--mapped_pages)
2546 goto out_free_iova;
2547 }
2548 }
2549
2550 out_free_iova:
2551 free_iova_fast(&dma_dom->iovad, address, npages);
2552
2553 out_err:
2554 return 0;
2555 }
2556
2557 /*
2558 * The exported map_sg function for dma_ops (handles scatter-gather
2559 * lists).
2560 */
2561 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2562 int nelems, enum dma_data_direction dir,
2563 unsigned long attrs)
2564 {
2565 struct protection_domain *domain;
2566 struct dma_ops_domain *dma_dom;
2567 unsigned long startaddr;
2568 int npages = 2;
2569
2570 domain = get_domain(dev);
2571 if (IS_ERR(domain))
2572 return;
2573
2574 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2575 dma_dom = to_dma_ops_domain(domain);
2576 npages = sg_num_pages(dev, sglist, nelems);
2577
2578 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2579 }
2580
2581 /*
2582 * The exported alloc_coherent function for dma_ops.
2583 */
2584 static void *alloc_coherent(struct device *dev, size_t size,
2585 dma_addr_t *dma_addr, gfp_t flag,
2586 unsigned long attrs)
2587 {
2588 u64 dma_mask = dev->coherent_dma_mask;
2589 struct protection_domain *domain;
2590 struct dma_ops_domain *dma_dom;
2591 struct page *page;
2592
2593 domain = get_domain(dev);
2594 if (PTR_ERR(domain) == -EINVAL) {
2595 page = alloc_pages(flag, get_order(size));
2596 *dma_addr = page_to_phys(page);
2597 return page_address(page);
2598 } else if (IS_ERR(domain))
2599 return NULL;
2600
2601 dma_dom = to_dma_ops_domain(domain);
2602 size = PAGE_ALIGN(size);
2603 dma_mask = dev->coherent_dma_mask;
2604 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2605 flag |= __GFP_ZERO;
2606
2607 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2608 if (!page) {
2609 if (!gfpflags_allow_blocking(flag))
2610 return NULL;
2611
2612 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2613 get_order(size), flag & __GFP_NOWARN);
2614 if (!page)
2615 return NULL;
2616 }
2617
2618 if (!dma_mask)
2619 dma_mask = *dev->dma_mask;
2620
2621 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2622 size, DMA_BIDIRECTIONAL, dma_mask);
2623
2624 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2625 goto out_free;
2626
2627 return page_address(page);
2628
2629 out_free:
2630
2631 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2632 __free_pages(page, get_order(size));
2633
2634 return NULL;
2635 }
2636
2637 /*
2638 * The exported free_coherent function for dma_ops.
2639 */
2640 static void free_coherent(struct device *dev, size_t size,
2641 void *virt_addr, dma_addr_t dma_addr,
2642 unsigned long attrs)
2643 {
2644 struct protection_domain *domain;
2645 struct dma_ops_domain *dma_dom;
2646 struct page *page;
2647
2648 page = virt_to_page(virt_addr);
2649 size = PAGE_ALIGN(size);
2650
2651 domain = get_domain(dev);
2652 if (IS_ERR(domain))
2653 goto free_mem;
2654
2655 dma_dom = to_dma_ops_domain(domain);
2656
2657 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2658
2659 free_mem:
2660 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2661 __free_pages(page, get_order(size));
2662 }
2663
2664 /*
2665 * This function is called by the DMA layer to find out if we can handle a
2666 * particular device. It is part of the dma_ops.
2667 */
2668 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2669 {
2670 if (!dma_direct_supported(dev, mask))
2671 return 0;
2672 return check_device(dev);
2673 }
2674
2675 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2676 {
2677 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2678 }
2679
2680 static const struct dma_map_ops amd_iommu_dma_ops = {
2681 .alloc = alloc_coherent,
2682 .free = free_coherent,
2683 .map_page = map_page,
2684 .unmap_page = unmap_page,
2685 .map_sg = map_sg,
2686 .unmap_sg = unmap_sg,
2687 .dma_supported = amd_iommu_dma_supported,
2688 .mapping_error = amd_iommu_mapping_error,
2689 };
2690
2691 static int init_reserved_iova_ranges(void)
2692 {
2693 struct pci_dev *pdev = NULL;
2694 struct iova *val;
2695
2696 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2697
2698 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2699 &reserved_rbtree_key);
2700
2701 /* MSI memory range */
2702 val = reserve_iova(&reserved_iova_ranges,
2703 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2704 if (!val) {
2705 pr_err("Reserving MSI range failed\n");
2706 return -ENOMEM;
2707 }
2708
2709 /* HT memory range */
2710 val = reserve_iova(&reserved_iova_ranges,
2711 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2712 if (!val) {
2713 pr_err("Reserving HT range failed\n");
2714 return -ENOMEM;
2715 }
2716
2717 /*
2718 * Memory used for PCI resources
2719 * FIXME: Check whether we can reserve the PCI-hole completly
2720 */
2721 for_each_pci_dev(pdev) {
2722 int i;
2723
2724 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2725 struct resource *r = &pdev->resource[i];
2726
2727 if (!(r->flags & IORESOURCE_MEM))
2728 continue;
2729
2730 val = reserve_iova(&reserved_iova_ranges,
2731 IOVA_PFN(r->start),
2732 IOVA_PFN(r->end));
2733 if (!val) {
2734 pr_err("Reserve pci-resource range failed\n");
2735 return -ENOMEM;
2736 }
2737 }
2738 }
2739
2740 return 0;
2741 }
2742
2743 int __init amd_iommu_init_api(void)
2744 {
2745 int ret, err = 0;
2746
2747 ret = iova_cache_get();
2748 if (ret)
2749 return ret;
2750
2751 ret = init_reserved_iova_ranges();
2752 if (ret)
2753 return ret;
2754
2755 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2756 if (err)
2757 return err;
2758 #ifdef CONFIG_ARM_AMBA
2759 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2760 if (err)
2761 return err;
2762 #endif
2763 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2764 if (err)
2765 return err;
2766
2767 return 0;
2768 }
2769
2770 int __init amd_iommu_init_dma_ops(void)
2771 {
2772 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2773 iommu_detected = 1;
2774
2775 /*
2776 * In case we don't initialize SWIOTLB (actually the common case
2777 * when AMD IOMMU is enabled and SME is not active), make sure there
2778 * are global dma_ops set as a fall-back for devices not handled by
2779 * this driver (for example non-PCI devices). When SME is active,
2780 * make sure that swiotlb variable remains set so the global dma_ops
2781 * continue to be SWIOTLB.
2782 */
2783 if (!swiotlb)
2784 dma_ops = &dma_direct_ops;
2785
2786 if (amd_iommu_unmap_flush)
2787 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2788 else
2789 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2790
2791 return 0;
2792
2793 }
2794
2795 /*****************************************************************************
2796 *
2797 * The following functions belong to the exported interface of AMD IOMMU
2798 *
2799 * This interface allows access to lower level functions of the IOMMU
2800 * like protection domain handling and assignement of devices to domains
2801 * which is not possible with the dma_ops interface.
2802 *
2803 *****************************************************************************/
2804
2805 static void cleanup_domain(struct protection_domain *domain)
2806 {
2807 struct iommu_dev_data *entry;
2808 unsigned long flags;
2809
2810 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2811
2812 while (!list_empty(&domain->dev_list)) {
2813 entry = list_first_entry(&domain->dev_list,
2814 struct iommu_dev_data, list);
2815 BUG_ON(!entry->domain);
2816 __detach_device(entry);
2817 }
2818
2819 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2820 }
2821
2822 static void protection_domain_free(struct protection_domain *domain)
2823 {
2824 if (!domain)
2825 return;
2826
2827 del_domain_from_list(domain);
2828
2829 if (domain->id)
2830 domain_id_free(domain->id);
2831
2832 kfree(domain);
2833 }
2834
2835 static int protection_domain_init(struct protection_domain *domain)
2836 {
2837 spin_lock_init(&domain->lock);
2838 mutex_init(&domain->api_lock);
2839 domain->id = domain_id_alloc();
2840 if (!domain->id)
2841 return -ENOMEM;
2842 INIT_LIST_HEAD(&domain->dev_list);
2843
2844 return 0;
2845 }
2846
2847 static struct protection_domain *protection_domain_alloc(void)
2848 {
2849 struct protection_domain *domain;
2850
2851 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2852 if (!domain)
2853 return NULL;
2854
2855 if (protection_domain_init(domain))
2856 goto out_err;
2857
2858 add_domain_to_list(domain);
2859
2860 return domain;
2861
2862 out_err:
2863 kfree(domain);
2864
2865 return NULL;
2866 }
2867
2868 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2869 {
2870 struct protection_domain *pdomain;
2871 struct dma_ops_domain *dma_domain;
2872
2873 switch (type) {
2874 case IOMMU_DOMAIN_UNMANAGED:
2875 pdomain = protection_domain_alloc();
2876 if (!pdomain)
2877 return NULL;
2878
2879 pdomain->mode = PAGE_MODE_3_LEVEL;
2880 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2881 if (!pdomain->pt_root) {
2882 protection_domain_free(pdomain);
2883 return NULL;
2884 }
2885
2886 pdomain->domain.geometry.aperture_start = 0;
2887 pdomain->domain.geometry.aperture_end = ~0ULL;
2888 pdomain->domain.geometry.force_aperture = true;
2889
2890 break;
2891 case IOMMU_DOMAIN_DMA:
2892 dma_domain = dma_ops_domain_alloc();
2893 if (!dma_domain) {
2894 pr_err("AMD-Vi: Failed to allocate\n");
2895 return NULL;
2896 }
2897 pdomain = &dma_domain->domain;
2898 break;
2899 case IOMMU_DOMAIN_IDENTITY:
2900 pdomain = protection_domain_alloc();
2901 if (!pdomain)
2902 return NULL;
2903
2904 pdomain->mode = PAGE_MODE_NONE;
2905 break;
2906 default:
2907 return NULL;
2908 }
2909
2910 return &pdomain->domain;
2911 }
2912
2913 static void amd_iommu_domain_free(struct iommu_domain *dom)
2914 {
2915 struct protection_domain *domain;
2916 struct dma_ops_domain *dma_dom;
2917
2918 domain = to_pdomain(dom);
2919
2920 if (domain->dev_cnt > 0)
2921 cleanup_domain(domain);
2922
2923 BUG_ON(domain->dev_cnt != 0);
2924
2925 if (!dom)
2926 return;
2927
2928 switch (dom->type) {
2929 case IOMMU_DOMAIN_DMA:
2930 /* Now release the domain */
2931 dma_dom = to_dma_ops_domain(domain);
2932 dma_ops_domain_free(dma_dom);
2933 break;
2934 default:
2935 if (domain->mode != PAGE_MODE_NONE)
2936 free_pagetable(domain);
2937
2938 if (domain->flags & PD_IOMMUV2_MASK)
2939 free_gcr3_table(domain);
2940
2941 protection_domain_free(domain);
2942 break;
2943 }
2944 }
2945
2946 static void amd_iommu_detach_device(struct iommu_domain *dom,
2947 struct device *dev)
2948 {
2949 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2950 struct amd_iommu *iommu;
2951 int devid;
2952
2953 if (!check_device(dev))
2954 return;
2955
2956 devid = get_device_id(dev);
2957 if (devid < 0)
2958 return;
2959
2960 if (dev_data->domain != NULL)
2961 detach_device(dev);
2962
2963 iommu = amd_iommu_rlookup_table[devid];
2964 if (!iommu)
2965 return;
2966
2967 #ifdef CONFIG_IRQ_REMAP
2968 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2969 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2970 dev_data->use_vapic = 0;
2971 #endif
2972
2973 iommu_completion_wait(iommu);
2974 }
2975
2976 static int amd_iommu_attach_device(struct iommu_domain *dom,
2977 struct device *dev)
2978 {
2979 struct protection_domain *domain = to_pdomain(dom);
2980 struct iommu_dev_data *dev_data;
2981 struct amd_iommu *iommu;
2982 int ret;
2983
2984 if (!check_device(dev))
2985 return -EINVAL;
2986
2987 dev_data = dev->archdata.iommu;
2988
2989 iommu = amd_iommu_rlookup_table[dev_data->devid];
2990 if (!iommu)
2991 return -EINVAL;
2992
2993 if (dev_data->domain)
2994 detach_device(dev);
2995
2996 ret = attach_device(dev, domain);
2997
2998 #ifdef CONFIG_IRQ_REMAP
2999 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3000 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3001 dev_data->use_vapic = 1;
3002 else
3003 dev_data->use_vapic = 0;
3004 }
3005 #endif
3006
3007 iommu_completion_wait(iommu);
3008
3009 return ret;
3010 }
3011
3012 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3013 phys_addr_t paddr, size_t page_size, int iommu_prot)
3014 {
3015 struct protection_domain *domain = to_pdomain(dom);
3016 int prot = 0;
3017 int ret;
3018
3019 if (domain->mode == PAGE_MODE_NONE)
3020 return -EINVAL;
3021
3022 if (iommu_prot & IOMMU_READ)
3023 prot |= IOMMU_PROT_IR;
3024 if (iommu_prot & IOMMU_WRITE)
3025 prot |= IOMMU_PROT_IW;
3026
3027 mutex_lock(&domain->api_lock);
3028 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3029 mutex_unlock(&domain->api_lock);
3030
3031 return ret;
3032 }
3033
3034 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3035 size_t page_size)
3036 {
3037 struct protection_domain *domain = to_pdomain(dom);
3038 size_t unmap_size;
3039
3040 if (domain->mode == PAGE_MODE_NONE)
3041 return 0;
3042
3043 mutex_lock(&domain->api_lock);
3044 unmap_size = iommu_unmap_page(domain, iova, page_size);
3045 mutex_unlock(&domain->api_lock);
3046
3047 return unmap_size;
3048 }
3049
3050 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3051 dma_addr_t iova)
3052 {
3053 struct protection_domain *domain = to_pdomain(dom);
3054 unsigned long offset_mask, pte_pgsize;
3055 u64 *pte, __pte;
3056
3057 if (domain->mode == PAGE_MODE_NONE)
3058 return iova;
3059
3060 pte = fetch_pte(domain, iova, &pte_pgsize);
3061
3062 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3063 return 0;
3064
3065 offset_mask = pte_pgsize - 1;
3066 __pte = *pte & PM_ADDR_MASK;
3067
3068 return (__pte & ~offset_mask) | (iova & offset_mask);
3069 }
3070
3071 static bool amd_iommu_capable(enum iommu_cap cap)
3072 {
3073 switch (cap) {
3074 case IOMMU_CAP_CACHE_COHERENCY:
3075 return true;
3076 case IOMMU_CAP_INTR_REMAP:
3077 return (irq_remapping_enabled == 1);
3078 case IOMMU_CAP_NOEXEC:
3079 return false;
3080 }
3081
3082 return false;
3083 }
3084
3085 static void amd_iommu_get_resv_regions(struct device *dev,
3086 struct list_head *head)
3087 {
3088 struct iommu_resv_region *region;
3089 struct unity_map_entry *entry;
3090 int devid;
3091
3092 devid = get_device_id(dev);
3093 if (devid < 0)
3094 return;
3095
3096 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3097 size_t length;
3098 int prot = 0;
3099
3100 if (devid < entry->devid_start || devid > entry->devid_end)
3101 continue;
3102
3103 length = entry->address_end - entry->address_start;
3104 if (entry->prot & IOMMU_PROT_IR)
3105 prot |= IOMMU_READ;
3106 if (entry->prot & IOMMU_PROT_IW)
3107 prot |= IOMMU_WRITE;
3108
3109 region = iommu_alloc_resv_region(entry->address_start,
3110 length, prot,
3111 IOMMU_RESV_DIRECT);
3112 if (!region) {
3113 pr_err("Out of memory allocating dm-regions for %s\n",
3114 dev_name(dev));
3115 return;
3116 }
3117 list_add_tail(&region->list, head);
3118 }
3119
3120 region = iommu_alloc_resv_region(MSI_RANGE_START,
3121 MSI_RANGE_END - MSI_RANGE_START + 1,
3122 0, IOMMU_RESV_MSI);
3123 if (!region)
3124 return;
3125 list_add_tail(&region->list, head);
3126
3127 region = iommu_alloc_resv_region(HT_RANGE_START,
3128 HT_RANGE_END - HT_RANGE_START + 1,
3129 0, IOMMU_RESV_RESERVED);
3130 if (!region)
3131 return;
3132 list_add_tail(&region->list, head);
3133 }
3134
3135 static void amd_iommu_put_resv_regions(struct device *dev,
3136 struct list_head *head)
3137 {
3138 struct iommu_resv_region *entry, *next;
3139
3140 list_for_each_entry_safe(entry, next, head, list)
3141 kfree(entry);
3142 }
3143
3144 static void amd_iommu_apply_resv_region(struct device *dev,
3145 struct iommu_domain *domain,
3146 struct iommu_resv_region *region)
3147 {
3148 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3149 unsigned long start, end;
3150
3151 start = IOVA_PFN(region->start);
3152 end = IOVA_PFN(region->start + region->length - 1);
3153
3154 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3155 }
3156
3157 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3158 struct device *dev)
3159 {
3160 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3161 return dev_data->defer_attach;
3162 }
3163
3164 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3165 {
3166 struct protection_domain *dom = to_pdomain(domain);
3167
3168 domain_flush_tlb_pde(dom);
3169 domain_flush_complete(dom);
3170 }
3171
3172 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3173 unsigned long iova, size_t size)
3174 {
3175 }
3176
3177 const struct iommu_ops amd_iommu_ops = {
3178 .capable = amd_iommu_capable,
3179 .domain_alloc = amd_iommu_domain_alloc,
3180 .domain_free = amd_iommu_domain_free,
3181 .attach_dev = amd_iommu_attach_device,
3182 .detach_dev = amd_iommu_detach_device,
3183 .map = amd_iommu_map,
3184 .unmap = amd_iommu_unmap,
3185 .iova_to_phys = amd_iommu_iova_to_phys,
3186 .add_device = amd_iommu_add_device,
3187 .remove_device = amd_iommu_remove_device,
3188 .device_group = amd_iommu_device_group,
3189 .get_resv_regions = amd_iommu_get_resv_regions,
3190 .put_resv_regions = amd_iommu_put_resv_regions,
3191 .apply_resv_region = amd_iommu_apply_resv_region,
3192 .is_attach_deferred = amd_iommu_is_attach_deferred,
3193 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3194 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3195 .iotlb_range_add = amd_iommu_iotlb_range_add,
3196 .iotlb_sync = amd_iommu_flush_iotlb_all,
3197 };
3198
3199 /*****************************************************************************
3200 *
3201 * The next functions do a basic initialization of IOMMU for pass through
3202 * mode
3203 *
3204 * In passthrough mode the IOMMU is initialized and enabled but not used for
3205 * DMA-API translation.
3206 *
3207 *****************************************************************************/
3208
3209 /* IOMMUv2 specific functions */
3210 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3211 {
3212 return atomic_notifier_chain_register(&ppr_notifier, nb);
3213 }
3214 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3215
3216 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3217 {
3218 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3219 }
3220 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3221
3222 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3223 {
3224 struct protection_domain *domain = to_pdomain(dom);
3225 unsigned long flags;
3226
3227 spin_lock_irqsave(&domain->lock, flags);
3228
3229 /* Update data structure */
3230 domain->mode = PAGE_MODE_NONE;
3231 domain->updated = true;
3232
3233 /* Make changes visible to IOMMUs */
3234 update_domain(domain);
3235
3236 /* Page-table is not visible to IOMMU anymore, so free it */
3237 free_pagetable(domain);
3238
3239 spin_unlock_irqrestore(&domain->lock, flags);
3240 }
3241 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3242
3243 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3244 {
3245 struct protection_domain *domain = to_pdomain(dom);
3246 unsigned long flags;
3247 int levels, ret;
3248
3249 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3250 return -EINVAL;
3251
3252 /* Number of GCR3 table levels required */
3253 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3254 levels += 1;
3255
3256 if (levels > amd_iommu_max_glx_val)
3257 return -EINVAL;
3258
3259 spin_lock_irqsave(&domain->lock, flags);
3260
3261 /*
3262 * Save us all sanity checks whether devices already in the
3263 * domain support IOMMUv2. Just force that the domain has no
3264 * devices attached when it is switched into IOMMUv2 mode.
3265 */
3266 ret = -EBUSY;
3267 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3268 goto out;
3269
3270 ret = -ENOMEM;
3271 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3272 if (domain->gcr3_tbl == NULL)
3273 goto out;
3274
3275 domain->glx = levels;
3276 domain->flags |= PD_IOMMUV2_MASK;
3277 domain->updated = true;
3278
3279 update_domain(domain);
3280
3281 ret = 0;
3282
3283 out:
3284 spin_unlock_irqrestore(&domain->lock, flags);
3285
3286 return ret;
3287 }
3288 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3289
3290 static int __flush_pasid(struct protection_domain *domain, int pasid,
3291 u64 address, bool size)
3292 {
3293 struct iommu_dev_data *dev_data;
3294 struct iommu_cmd cmd;
3295 int i, ret;
3296
3297 if (!(domain->flags & PD_IOMMUV2_MASK))
3298 return -EINVAL;
3299
3300 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3301
3302 /*
3303 * IOMMU TLB needs to be flushed before Device TLB to
3304 * prevent device TLB refill from IOMMU TLB
3305 */
3306 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3307 if (domain->dev_iommu[i] == 0)
3308 continue;
3309
3310 ret = iommu_queue_command(amd_iommus[i], &cmd);
3311 if (ret != 0)
3312 goto out;
3313 }
3314
3315 /* Wait until IOMMU TLB flushes are complete */
3316 domain_flush_complete(domain);
3317
3318 /* Now flush device TLBs */
3319 list_for_each_entry(dev_data, &domain->dev_list, list) {
3320 struct amd_iommu *iommu;
3321 int qdep;
3322
3323 /*
3324 There might be non-IOMMUv2 capable devices in an IOMMUv2
3325 * domain.
3326 */
3327 if (!dev_data->ats.enabled)
3328 continue;
3329
3330 qdep = dev_data->ats.qdep;
3331 iommu = amd_iommu_rlookup_table[dev_data->devid];
3332
3333 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3334 qdep, address, size);
3335
3336 ret = iommu_queue_command(iommu, &cmd);
3337 if (ret != 0)
3338 goto out;
3339 }
3340
3341 /* Wait until all device TLBs are flushed */
3342 domain_flush_complete(domain);
3343
3344 ret = 0;
3345
3346 out:
3347
3348 return ret;
3349 }
3350
3351 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3352 u64 address)
3353 {
3354 return __flush_pasid(domain, pasid, address, false);
3355 }
3356
3357 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3358 u64 address)
3359 {
3360 struct protection_domain *domain = to_pdomain(dom);
3361 unsigned long flags;
3362 int ret;
3363
3364 spin_lock_irqsave(&domain->lock, flags);
3365 ret = __amd_iommu_flush_page(domain, pasid, address);
3366 spin_unlock_irqrestore(&domain->lock, flags);
3367
3368 return ret;
3369 }
3370 EXPORT_SYMBOL(amd_iommu_flush_page);
3371
3372 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3373 {
3374 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3375 true);
3376 }
3377
3378 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3379 {
3380 struct protection_domain *domain = to_pdomain(dom);
3381 unsigned long flags;
3382 int ret;
3383
3384 spin_lock_irqsave(&domain->lock, flags);
3385 ret = __amd_iommu_flush_tlb(domain, pasid);
3386 spin_unlock_irqrestore(&domain->lock, flags);
3387
3388 return ret;
3389 }
3390 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3391
3392 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3393 {
3394 int index;
3395 u64 *pte;
3396
3397 while (true) {
3398
3399 index = (pasid >> (9 * level)) & 0x1ff;
3400 pte = &root[index];
3401
3402 if (level == 0)
3403 break;
3404
3405 if (!(*pte & GCR3_VALID)) {
3406 if (!alloc)
3407 return NULL;
3408
3409 root = (void *)get_zeroed_page(GFP_ATOMIC);
3410 if (root == NULL)
3411 return NULL;
3412
3413 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3414 }
3415
3416 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3417
3418 level -= 1;
3419 }
3420
3421 return pte;
3422 }
3423
3424 static int __set_gcr3(struct protection_domain *domain, int pasid,
3425 unsigned long cr3)
3426 {
3427 u64 *pte;
3428
3429 if (domain->mode != PAGE_MODE_NONE)
3430 return -EINVAL;
3431
3432 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3433 if (pte == NULL)
3434 return -ENOMEM;
3435
3436 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3437
3438 return __amd_iommu_flush_tlb(domain, pasid);
3439 }
3440
3441 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3442 {
3443 u64 *pte;
3444
3445 if (domain->mode != PAGE_MODE_NONE)
3446 return -EINVAL;
3447
3448 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3449 if (pte == NULL)
3450 return 0;
3451
3452 *pte = 0;
3453
3454 return __amd_iommu_flush_tlb(domain, pasid);
3455 }
3456
3457 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3458 unsigned long cr3)
3459 {
3460 struct protection_domain *domain = to_pdomain(dom);
3461 unsigned long flags;
3462 int ret;
3463
3464 spin_lock_irqsave(&domain->lock, flags);
3465 ret = __set_gcr3(domain, pasid, cr3);
3466 spin_unlock_irqrestore(&domain->lock, flags);
3467
3468 return ret;
3469 }
3470 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3471
3472 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3473 {
3474 struct protection_domain *domain = to_pdomain(dom);
3475 unsigned long flags;
3476 int ret;
3477
3478 spin_lock_irqsave(&domain->lock, flags);
3479 ret = __clear_gcr3(domain, pasid);
3480 spin_unlock_irqrestore(&domain->lock, flags);
3481
3482 return ret;
3483 }
3484 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3485
3486 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3487 int status, int tag)
3488 {
3489 struct iommu_dev_data *dev_data;
3490 struct amd_iommu *iommu;
3491 struct iommu_cmd cmd;
3492
3493 dev_data = get_dev_data(&pdev->dev);
3494 iommu = amd_iommu_rlookup_table[dev_data->devid];
3495
3496 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3497 tag, dev_data->pri_tlp);
3498
3499 return iommu_queue_command(iommu, &cmd);
3500 }
3501 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3502
3503 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3504 {
3505 struct protection_domain *pdomain;
3506
3507 pdomain = get_domain(&pdev->dev);
3508 if (IS_ERR(pdomain))
3509 return NULL;
3510
3511 /* Only return IOMMUv2 domains */
3512 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3513 return NULL;
3514
3515 return &pdomain->domain;
3516 }
3517 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3518
3519 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3520 {
3521 struct iommu_dev_data *dev_data;
3522
3523 if (!amd_iommu_v2_supported())
3524 return;
3525
3526 dev_data = get_dev_data(&pdev->dev);
3527 dev_data->errata |= (1 << erratum);
3528 }
3529 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3530
3531 int amd_iommu_device_info(struct pci_dev *pdev,
3532 struct amd_iommu_device_info *info)
3533 {
3534 int max_pasids;
3535 int pos;
3536
3537 if (pdev == NULL || info == NULL)
3538 return -EINVAL;
3539
3540 if (!amd_iommu_v2_supported())
3541 return -EINVAL;
3542
3543 memset(info, 0, sizeof(*info));
3544
3545 if (!pci_ats_disabled()) {
3546 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3547 if (pos)
3548 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3549 }
3550
3551 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3552 if (pos)
3553 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3554
3555 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3556 if (pos) {
3557 int features;
3558
3559 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3560 max_pasids = min(max_pasids, (1 << 20));
3561
3562 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3563 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3564
3565 features = pci_pasid_features(pdev);
3566 if (features & PCI_PASID_CAP_EXEC)
3567 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3568 if (features & PCI_PASID_CAP_PRIV)
3569 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3570 }
3571
3572 return 0;
3573 }
3574 EXPORT_SYMBOL(amd_iommu_device_info);
3575
3576 #ifdef CONFIG_IRQ_REMAP
3577
3578 /*****************************************************************************
3579 *
3580 * Interrupt Remapping Implementation
3581 *
3582 *****************************************************************************/
3583
3584 static struct irq_chip amd_ir_chip;
3585 static DEFINE_SPINLOCK(iommu_table_lock);
3586
3587 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3588 {
3589 u64 dte;
3590
3591 dte = amd_iommu_dev_table[devid].data[2];
3592 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3593 dte |= iommu_virt_to_phys(table->table);
3594 dte |= DTE_IRQ_REMAP_INTCTL;
3595 dte |= DTE_IRQ_TABLE_LEN;
3596 dte |= DTE_IRQ_REMAP_ENABLE;
3597
3598 amd_iommu_dev_table[devid].data[2] = dte;
3599 }
3600
3601 static struct irq_remap_table *get_irq_table(u16 devid)
3602 {
3603 struct irq_remap_table *table;
3604
3605 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3606 "%s: no iommu for devid %x\n", __func__, devid))
3607 return NULL;
3608
3609 table = irq_lookup_table[devid];
3610 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3611 return NULL;
3612
3613 return table;
3614 }
3615
3616 static struct irq_remap_table *__alloc_irq_table(void)
3617 {
3618 struct irq_remap_table *table;
3619
3620 table = kzalloc(sizeof(*table), GFP_KERNEL);
3621 if (!table)
3622 return NULL;
3623
3624 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3625 if (!table->table) {
3626 kfree(table);
3627 return NULL;
3628 }
3629 raw_spin_lock_init(&table->lock);
3630
3631 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3632 memset(table->table, 0,
3633 MAX_IRQS_PER_TABLE * sizeof(u32));
3634 else
3635 memset(table->table, 0,
3636 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3637 return table;
3638 }
3639
3640 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3641 struct irq_remap_table *table)
3642 {
3643 irq_lookup_table[devid] = table;
3644 set_dte_irq_entry(devid, table);
3645 iommu_flush_dte(iommu, devid);
3646 }
3647
3648 static struct irq_remap_table *alloc_irq_table(u16 devid)
3649 {
3650 struct irq_remap_table *table = NULL;
3651 struct irq_remap_table *new_table = NULL;
3652 struct amd_iommu *iommu;
3653 unsigned long flags;
3654 u16 alias;
3655
3656 spin_lock_irqsave(&iommu_table_lock, flags);
3657
3658 iommu = amd_iommu_rlookup_table[devid];
3659 if (!iommu)
3660 goto out_unlock;
3661
3662 table = irq_lookup_table[devid];
3663 if (table)
3664 goto out_unlock;
3665
3666 alias = amd_iommu_alias_table[devid];
3667 table = irq_lookup_table[alias];
3668 if (table) {
3669 set_remap_table_entry(iommu, devid, table);
3670 goto out_wait;
3671 }
3672 spin_unlock_irqrestore(&iommu_table_lock, flags);
3673
3674 /* Nothing there yet, allocate new irq remapping table */
3675 new_table = __alloc_irq_table();
3676 if (!new_table)
3677 return NULL;
3678
3679 spin_lock_irqsave(&iommu_table_lock, flags);
3680
3681 table = irq_lookup_table[devid];
3682 if (table)
3683 goto out_unlock;
3684
3685 table = irq_lookup_table[alias];
3686 if (table) {
3687 set_remap_table_entry(iommu, devid, table);
3688 goto out_wait;
3689 }
3690
3691 table = new_table;
3692 new_table = NULL;
3693
3694 set_remap_table_entry(iommu, devid, table);
3695 if (devid != alias)
3696 set_remap_table_entry(iommu, alias, table);
3697
3698 out_wait:
3699 iommu_completion_wait(iommu);
3700
3701 out_unlock:
3702 spin_unlock_irqrestore(&iommu_table_lock, flags);
3703
3704 if (new_table) {
3705 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3706 kfree(new_table);
3707 }
3708 return table;
3709 }
3710
3711 static int alloc_irq_index(u16 devid, int count, bool align)
3712 {
3713 struct irq_remap_table *table;
3714 int index, c, alignment = 1;
3715 unsigned long flags;
3716 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3717
3718 if (!iommu)
3719 return -ENODEV;
3720
3721 table = alloc_irq_table(devid);
3722 if (!table)
3723 return -ENODEV;
3724
3725 if (align)
3726 alignment = roundup_pow_of_two(count);
3727
3728 raw_spin_lock_irqsave(&table->lock, flags);
3729
3730 /* Scan table for free entries */
3731 for (index = ALIGN(table->min_index, alignment), c = 0;
3732 index < MAX_IRQS_PER_TABLE;) {
3733 if (!iommu->irte_ops->is_allocated(table, index)) {
3734 c += 1;
3735 } else {
3736 c = 0;
3737 index = ALIGN(index + 1, alignment);
3738 continue;
3739 }
3740
3741 if (c == count) {
3742 for (; c != 0; --c)
3743 iommu->irte_ops->set_allocated(table, index - c + 1);
3744
3745 index -= count - 1;
3746 goto out;
3747 }
3748
3749 index++;
3750 }
3751
3752 index = -ENOSPC;
3753
3754 out:
3755 raw_spin_unlock_irqrestore(&table->lock, flags);
3756
3757 return index;
3758 }
3759
3760 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3761 struct amd_ir_data *data)
3762 {
3763 struct irq_remap_table *table;
3764 struct amd_iommu *iommu;
3765 unsigned long flags;
3766 struct irte_ga *entry;
3767
3768 iommu = amd_iommu_rlookup_table[devid];
3769 if (iommu == NULL)
3770 return -EINVAL;
3771
3772 table = get_irq_table(devid);
3773 if (!table)
3774 return -ENOMEM;
3775
3776 raw_spin_lock_irqsave(&table->lock, flags);
3777
3778 entry = (struct irte_ga *)table->table;
3779 entry = &entry[index];
3780 entry->lo.fields_remap.valid = 0;
3781 entry->hi.val = irte->hi.val;
3782 entry->lo.val = irte->lo.val;
3783 entry->lo.fields_remap.valid = 1;
3784 if (data)
3785 data->ref = entry;
3786
3787 raw_spin_unlock_irqrestore(&table->lock, flags);
3788
3789 iommu_flush_irt(iommu, devid);
3790 iommu_completion_wait(iommu);
3791
3792 return 0;
3793 }
3794
3795 static int modify_irte(u16 devid, int index, union irte *irte)
3796 {
3797 struct irq_remap_table *table;
3798 struct amd_iommu *iommu;
3799 unsigned long flags;
3800
3801 iommu = amd_iommu_rlookup_table[devid];
3802 if (iommu == NULL)
3803 return -EINVAL;
3804
3805 table = get_irq_table(devid);
3806 if (!table)
3807 return -ENOMEM;
3808
3809 raw_spin_lock_irqsave(&table->lock, flags);
3810 table->table[index] = irte->val;
3811 raw_spin_unlock_irqrestore(&table->lock, flags);
3812
3813 iommu_flush_irt(iommu, devid);
3814 iommu_completion_wait(iommu);
3815
3816 return 0;
3817 }
3818
3819 static void free_irte(u16 devid, int index)
3820 {
3821 struct irq_remap_table *table;
3822 struct amd_iommu *iommu;
3823 unsigned long flags;
3824
3825 iommu = amd_iommu_rlookup_table[devid];
3826 if (iommu == NULL)
3827 return;
3828
3829 table = get_irq_table(devid);
3830 if (!table)
3831 return;
3832
3833 raw_spin_lock_irqsave(&table->lock, flags);
3834 iommu->irte_ops->clear_allocated(table, index);
3835 raw_spin_unlock_irqrestore(&table->lock, flags);
3836
3837 iommu_flush_irt(iommu, devid);
3838 iommu_completion_wait(iommu);
3839 }
3840
3841 static void irte_prepare(void *entry,
3842 u32 delivery_mode, u32 dest_mode,
3843 u8 vector, u32 dest_apicid, int devid)
3844 {
3845 union irte *irte = (union irte *) entry;
3846
3847 irte->val = 0;
3848 irte->fields.vector = vector;
3849 irte->fields.int_type = delivery_mode;
3850 irte->fields.destination = dest_apicid;
3851 irte->fields.dm = dest_mode;
3852 irte->fields.valid = 1;
3853 }
3854
3855 static void irte_ga_prepare(void *entry,
3856 u32 delivery_mode, u32 dest_mode,
3857 u8 vector, u32 dest_apicid, int devid)
3858 {
3859 struct irte_ga *irte = (struct irte_ga *) entry;
3860
3861 irte->lo.val = 0;
3862 irte->hi.val = 0;
3863 irte->lo.fields_remap.int_type = delivery_mode;
3864 irte->lo.fields_remap.dm = dest_mode;
3865 irte->hi.fields.vector = vector;
3866 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3867 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3868 irte->lo.fields_remap.valid = 1;
3869 }
3870
3871 static void irte_activate(void *entry, u16 devid, u16 index)
3872 {
3873 union irte *irte = (union irte *) entry;
3874
3875 irte->fields.valid = 1;
3876 modify_irte(devid, index, irte);
3877 }
3878
3879 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3880 {
3881 struct irte_ga *irte = (struct irte_ga *) entry;
3882
3883 irte->lo.fields_remap.valid = 1;
3884 modify_irte_ga(devid, index, irte, NULL);
3885 }
3886
3887 static void irte_deactivate(void *entry, u16 devid, u16 index)
3888 {
3889 union irte *irte = (union irte *) entry;
3890
3891 irte->fields.valid = 0;
3892 modify_irte(devid, index, irte);
3893 }
3894
3895 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3896 {
3897 struct irte_ga *irte = (struct irte_ga *) entry;
3898
3899 irte->lo.fields_remap.valid = 0;
3900 modify_irte_ga(devid, index, irte, NULL);
3901 }
3902
3903 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3904 u8 vector, u32 dest_apicid)
3905 {
3906 union irte *irte = (union irte *) entry;
3907
3908 irte->fields.vector = vector;
3909 irte->fields.destination = dest_apicid;
3910 modify_irte(devid, index, irte);
3911 }
3912
3913 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3914 u8 vector, u32 dest_apicid)
3915 {
3916 struct irte_ga *irte = (struct irte_ga *) entry;
3917
3918 if (!irte->lo.fields_remap.guest_mode) {
3919 irte->hi.fields.vector = vector;
3920 irte->lo.fields_remap.destination =
3921 APICID_TO_IRTE_DEST_LO(dest_apicid);
3922 irte->hi.fields.destination =
3923 APICID_TO_IRTE_DEST_HI(dest_apicid);
3924 modify_irte_ga(devid, index, irte, NULL);
3925 }
3926 }
3927
3928 #define IRTE_ALLOCATED (~1U)
3929 static void irte_set_allocated(struct irq_remap_table *table, int index)
3930 {
3931 table->table[index] = IRTE_ALLOCATED;
3932 }
3933
3934 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3935 {
3936 struct irte_ga *ptr = (struct irte_ga *)table->table;
3937 struct irte_ga *irte = &ptr[index];
3938
3939 memset(&irte->lo.val, 0, sizeof(u64));
3940 memset(&irte->hi.val, 0, sizeof(u64));
3941 irte->hi.fields.vector = 0xff;
3942 }
3943
3944 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3945 {
3946 union irte *ptr = (union irte *)table->table;
3947 union irte *irte = &ptr[index];
3948
3949 return irte->val != 0;
3950 }
3951
3952 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3953 {
3954 struct irte_ga *ptr = (struct irte_ga *)table->table;
3955 struct irte_ga *irte = &ptr[index];
3956
3957 return irte->hi.fields.vector != 0;
3958 }
3959
3960 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3961 {
3962 table->table[index] = 0;
3963 }
3964
3965 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3966 {
3967 struct irte_ga *ptr = (struct irte_ga *)table->table;
3968 struct irte_ga *irte = &ptr[index];
3969
3970 memset(&irte->lo.val, 0, sizeof(u64));
3971 memset(&irte->hi.val, 0, sizeof(u64));
3972 }
3973
3974 static int get_devid(struct irq_alloc_info *info)
3975 {
3976 int devid = -1;
3977
3978 switch (info->type) {
3979 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3980 devid = get_ioapic_devid(info->ioapic_id);
3981 break;
3982 case X86_IRQ_ALLOC_TYPE_HPET:
3983 devid = get_hpet_devid(info->hpet_id);
3984 break;
3985 case X86_IRQ_ALLOC_TYPE_MSI:
3986 case X86_IRQ_ALLOC_TYPE_MSIX:
3987 devid = get_device_id(&info->msi_dev->dev);
3988 break;
3989 default:
3990 BUG_ON(1);
3991 break;
3992 }
3993
3994 return devid;
3995 }
3996
3997 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3998 {
3999 struct amd_iommu *iommu;
4000 int devid;
4001
4002 if (!info)
4003 return NULL;
4004
4005 devid = get_devid(info);
4006 if (devid >= 0) {
4007 iommu = amd_iommu_rlookup_table[devid];
4008 if (iommu)
4009 return iommu->ir_domain;
4010 }
4011
4012 return NULL;
4013 }
4014
4015 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4016 {
4017 struct amd_iommu *iommu;
4018 int devid;
4019
4020 if (!info)
4021 return NULL;
4022
4023 switch (info->type) {
4024 case X86_IRQ_ALLOC_TYPE_MSI:
4025 case X86_IRQ_ALLOC_TYPE_MSIX:
4026 devid = get_device_id(&info->msi_dev->dev);
4027 if (devid < 0)
4028 return NULL;
4029
4030 iommu = amd_iommu_rlookup_table[devid];
4031 if (iommu)
4032 return iommu->msi_domain;
4033 break;
4034 default:
4035 break;
4036 }
4037
4038 return NULL;
4039 }
4040
4041 struct irq_remap_ops amd_iommu_irq_ops = {
4042 .prepare = amd_iommu_prepare,
4043 .enable = amd_iommu_enable,
4044 .disable = amd_iommu_disable,
4045 .reenable = amd_iommu_reenable,
4046 .enable_faulting = amd_iommu_enable_faulting,
4047 .get_ir_irq_domain = get_ir_irq_domain,
4048 .get_irq_domain = get_irq_domain,
4049 };
4050
4051 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4052 struct irq_cfg *irq_cfg,
4053 struct irq_alloc_info *info,
4054 int devid, int index, int sub_handle)
4055 {
4056 struct irq_2_irte *irte_info = &data->irq_2_irte;
4057 struct msi_msg *msg = &data->msi_entry;
4058 struct IO_APIC_route_entry *entry;
4059 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4060
4061 if (!iommu)
4062 return;
4063
4064 data->irq_2_irte.devid = devid;
4065 data->irq_2_irte.index = index + sub_handle;
4066 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4067 apic->irq_dest_mode, irq_cfg->vector,
4068 irq_cfg->dest_apicid, devid);
4069
4070 switch (info->type) {
4071 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4072 /* Setup IOAPIC entry */
4073 entry = info->ioapic_entry;
4074 info->ioapic_entry = NULL;
4075 memset(entry, 0, sizeof(*entry));
4076 entry->vector = index;
4077 entry->mask = 0;
4078 entry->trigger = info->ioapic_trigger;
4079 entry->polarity = info->ioapic_polarity;
4080 /* Mask level triggered irqs. */
4081 if (info->ioapic_trigger)
4082 entry->mask = 1;
4083 break;
4084
4085 case X86_IRQ_ALLOC_TYPE_HPET:
4086 case X86_IRQ_ALLOC_TYPE_MSI:
4087 case X86_IRQ_ALLOC_TYPE_MSIX:
4088 msg->address_hi = MSI_ADDR_BASE_HI;
4089 msg->address_lo = MSI_ADDR_BASE_LO;
4090 msg->data = irte_info->index;
4091 break;
4092
4093 default:
4094 BUG_ON(1);
4095 break;
4096 }
4097 }
4098
4099 struct amd_irte_ops irte_32_ops = {
4100 .prepare = irte_prepare,
4101 .activate = irte_activate,
4102 .deactivate = irte_deactivate,
4103 .set_affinity = irte_set_affinity,
4104 .set_allocated = irte_set_allocated,
4105 .is_allocated = irte_is_allocated,
4106 .clear_allocated = irte_clear_allocated,
4107 };
4108
4109 struct amd_irte_ops irte_128_ops = {
4110 .prepare = irte_ga_prepare,
4111 .activate = irte_ga_activate,
4112 .deactivate = irte_ga_deactivate,
4113 .set_affinity = irte_ga_set_affinity,
4114 .set_allocated = irte_ga_set_allocated,
4115 .is_allocated = irte_ga_is_allocated,
4116 .clear_allocated = irte_ga_clear_allocated,
4117 };
4118
4119 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4120 unsigned int nr_irqs, void *arg)
4121 {
4122 struct irq_alloc_info *info = arg;
4123 struct irq_data *irq_data;
4124 struct amd_ir_data *data = NULL;
4125 struct irq_cfg *cfg;
4126 int i, ret, devid;
4127 int index;
4128
4129 if (!info)
4130 return -EINVAL;
4131 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4132 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4133 return -EINVAL;
4134
4135 /*
4136 * With IRQ remapping enabled, don't need contiguous CPU vectors
4137 * to support multiple MSI interrupts.
4138 */
4139 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4140 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4141
4142 devid = get_devid(info);
4143 if (devid < 0)
4144 return -EINVAL;
4145
4146 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4147 if (ret < 0)
4148 return ret;
4149
4150 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4151 struct irq_remap_table *table;
4152 struct amd_iommu *iommu;
4153
4154 table = alloc_irq_table(devid);
4155 if (table) {
4156 if (!table->min_index) {
4157 /*
4158 * Keep the first 32 indexes free for IOAPIC
4159 * interrupts.
4160 */
4161 table->min_index = 32;
4162 iommu = amd_iommu_rlookup_table[devid];
4163 for (i = 0; i < 32; ++i)
4164 iommu->irte_ops->set_allocated(table, i);
4165 }
4166 WARN_ON(table->min_index != 32);
4167 index = info->ioapic_pin;
4168 } else {
4169 index = -ENOMEM;
4170 }
4171 } else {
4172 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4173
4174 index = alloc_irq_index(devid, nr_irqs, align);
4175 }
4176 if (index < 0) {
4177 pr_warn("Failed to allocate IRTE\n");
4178 ret = index;
4179 goto out_free_parent;
4180 }
4181
4182 for (i = 0; i < nr_irqs; i++) {
4183 irq_data = irq_domain_get_irq_data(domain, virq + i);
4184 cfg = irqd_cfg(irq_data);
4185 if (!irq_data || !cfg) {
4186 ret = -EINVAL;
4187 goto out_free_data;
4188 }
4189
4190 ret = -ENOMEM;
4191 data = kzalloc(sizeof(*data), GFP_KERNEL);
4192 if (!data)
4193 goto out_free_data;
4194
4195 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4196 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4197 else
4198 data->entry = kzalloc(sizeof(struct irte_ga),
4199 GFP_KERNEL);
4200 if (!data->entry) {
4201 kfree(data);
4202 goto out_free_data;
4203 }
4204
4205 irq_data->hwirq = (devid << 16) + i;
4206 irq_data->chip_data = data;
4207 irq_data->chip = &amd_ir_chip;
4208 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4209 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4210 }
4211
4212 return 0;
4213
4214 out_free_data:
4215 for (i--; i >= 0; i--) {
4216 irq_data = irq_domain_get_irq_data(domain, virq + i);
4217 if (irq_data)
4218 kfree(irq_data->chip_data);
4219 }
4220 for (i = 0; i < nr_irqs; i++)
4221 free_irte(devid, index + i);
4222 out_free_parent:
4223 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4224 return ret;
4225 }
4226
4227 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4228 unsigned int nr_irqs)
4229 {
4230 struct irq_2_irte *irte_info;
4231 struct irq_data *irq_data;
4232 struct amd_ir_data *data;
4233 int i;
4234
4235 for (i = 0; i < nr_irqs; i++) {
4236 irq_data = irq_domain_get_irq_data(domain, virq + i);
4237 if (irq_data && irq_data->chip_data) {
4238 data = irq_data->chip_data;
4239 irte_info = &data->irq_2_irte;
4240 free_irte(irte_info->devid, irte_info->index);
4241 kfree(data->entry);
4242 kfree(data);
4243 }
4244 }
4245 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4246 }
4247
4248 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4249 struct amd_ir_data *ir_data,
4250 struct irq_2_irte *irte_info,
4251 struct irq_cfg *cfg);
4252
4253 static int irq_remapping_activate(struct irq_domain *domain,
4254 struct irq_data *irq_data, bool reserve)
4255 {
4256 struct amd_ir_data *data = irq_data->chip_data;
4257 struct irq_2_irte *irte_info = &data->irq_2_irte;
4258 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4259 struct irq_cfg *cfg = irqd_cfg(irq_data);
4260
4261 if (!iommu)
4262 return 0;
4263
4264 iommu->irte_ops->activate(data->entry, irte_info->devid,
4265 irte_info->index);
4266 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4267 return 0;
4268 }
4269
4270 static void irq_remapping_deactivate(struct irq_domain *domain,
4271 struct irq_data *irq_data)
4272 {
4273 struct amd_ir_data *data = irq_data->chip_data;
4274 struct irq_2_irte *irte_info = &data->irq_2_irte;
4275 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4276
4277 if (iommu)
4278 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4279 irte_info->index);
4280 }
4281
4282 static const struct irq_domain_ops amd_ir_domain_ops = {
4283 .alloc = irq_remapping_alloc,
4284 .free = irq_remapping_free,
4285 .activate = irq_remapping_activate,
4286 .deactivate = irq_remapping_deactivate,
4287 };
4288
4289 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4290 {
4291 struct amd_iommu *iommu;
4292 struct amd_iommu_pi_data *pi_data = vcpu_info;
4293 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4294 struct amd_ir_data *ir_data = data->chip_data;
4295 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4296 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4297 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4298
4299 /* Note:
4300 * This device has never been set up for guest mode.
4301 * we should not modify the IRTE
4302 */
4303 if (!dev_data || !dev_data->use_vapic)
4304 return 0;
4305
4306 pi_data->ir_data = ir_data;
4307
4308 /* Note:
4309 * SVM tries to set up for VAPIC mode, but we are in
4310 * legacy mode. So, we force legacy mode instead.
4311 */
4312 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4313 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4314 __func__);
4315 pi_data->is_guest_mode = false;
4316 }
4317
4318 iommu = amd_iommu_rlookup_table[irte_info->devid];
4319 if (iommu == NULL)
4320 return -EINVAL;
4321
4322 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4323 if (pi_data->is_guest_mode) {
4324 /* Setting */
4325 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4326 irte->hi.fields.vector = vcpu_pi_info->vector;
4327 irte->lo.fields_vapic.ga_log_intr = 1;
4328 irte->lo.fields_vapic.guest_mode = 1;
4329 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4330
4331 ir_data->cached_ga_tag = pi_data->ga_tag;
4332 } else {
4333 /* Un-Setting */
4334 struct irq_cfg *cfg = irqd_cfg(data);
4335
4336 irte->hi.val = 0;
4337 irte->lo.val = 0;
4338 irte->hi.fields.vector = cfg->vector;
4339 irte->lo.fields_remap.guest_mode = 0;
4340 irte->lo.fields_remap.destination =
4341 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4342 irte->hi.fields.destination =
4343 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4344 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4345 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4346
4347 /*
4348 * This communicates the ga_tag back to the caller
4349 * so that it can do all the necessary clean up.
4350 */
4351 ir_data->cached_ga_tag = 0;
4352 }
4353
4354 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4355 }
4356
4357
4358 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4359 struct amd_ir_data *ir_data,
4360 struct irq_2_irte *irte_info,
4361 struct irq_cfg *cfg)
4362 {
4363
4364 /*
4365 * Atomically updates the IRTE with the new destination, vector
4366 * and flushes the interrupt entry cache.
4367 */
4368 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4369 irte_info->index, cfg->vector,
4370 cfg->dest_apicid);
4371 }
4372
4373 static int amd_ir_set_affinity(struct irq_data *data,
4374 const struct cpumask *mask, bool force)
4375 {
4376 struct amd_ir_data *ir_data = data->chip_data;
4377 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4378 struct irq_cfg *cfg = irqd_cfg(data);
4379 struct irq_data *parent = data->parent_data;
4380 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4381 int ret;
4382
4383 if (!iommu)
4384 return -ENODEV;
4385
4386 ret = parent->chip->irq_set_affinity(parent, mask, force);
4387 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4388 return ret;
4389
4390 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4391 /*
4392 * After this point, all the interrupts will start arriving
4393 * at the new destination. So, time to cleanup the previous
4394 * vector allocation.
4395 */
4396 send_cleanup_vector(cfg);
4397
4398 return IRQ_SET_MASK_OK_DONE;
4399 }
4400
4401 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4402 {
4403 struct amd_ir_data *ir_data = irq_data->chip_data;
4404
4405 *msg = ir_data->msi_entry;
4406 }
4407
4408 static struct irq_chip amd_ir_chip = {
4409 .name = "AMD-IR",
4410 .irq_ack = apic_ack_irq,
4411 .irq_set_affinity = amd_ir_set_affinity,
4412 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4413 .irq_compose_msi_msg = ir_compose_msi_msg,
4414 };
4415
4416 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4417 {
4418 struct fwnode_handle *fn;
4419
4420 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4421 if (!fn)
4422 return -ENOMEM;
4423 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4424 irq_domain_free_fwnode(fn);
4425 if (!iommu->ir_domain)
4426 return -ENOMEM;
4427
4428 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4429 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4430 "AMD-IR-MSI",
4431 iommu->index);
4432 return 0;
4433 }
4434
4435 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4436 {
4437 unsigned long flags;
4438 struct amd_iommu *iommu;
4439 struct irq_remap_table *table;
4440 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4441 int devid = ir_data->irq_2_irte.devid;
4442 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4443 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4444
4445 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4446 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4447 return 0;
4448
4449 iommu = amd_iommu_rlookup_table[devid];
4450 if (!iommu)
4451 return -ENODEV;
4452
4453 table = get_irq_table(devid);
4454 if (!table)
4455 return -ENODEV;
4456
4457 raw_spin_lock_irqsave(&table->lock, flags);
4458
4459 if (ref->lo.fields_vapic.guest_mode) {
4460 if (cpu >= 0) {
4461 ref->lo.fields_vapic.destination =
4462 APICID_TO_IRTE_DEST_LO(cpu);
4463 ref->hi.fields.destination =
4464 APICID_TO_IRTE_DEST_HI(cpu);
4465 }
4466 ref->lo.fields_vapic.is_run = is_run;
4467 barrier();
4468 }
4469
4470 raw_spin_unlock_irqrestore(&table->lock, flags);
4471
4472 iommu_flush_irt(iommu, devid);
4473 iommu_completion_wait(iommu);
4474 return 0;
4475 }
4476 EXPORT_SYMBOL(amd_iommu_update_ga);
4477 #endif
Linux with added FPC-III support